1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * libahci.c - Common AHCI SATA low-level routines
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/bitops.h>
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/module.h>
23 #include <linux/nospec.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/device.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/pci.h>
33 #include "ahci.h"
34 #include "libata.h"
35
36 static int ahci_skip_host_reset;
37 int ahci_ignore_sss;
38 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
39
40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
42
43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
45
46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
47 unsigned hints);
48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
50 size_t size);
51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
52 ssize_t size);
53
54
55
56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
58 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
59 static int ahci_port_start(struct ata_port *ap);
60 static void ahci_port_stop(struct ata_port *ap);
61 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
62 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
63 static void ahci_freeze(struct ata_port *ap);
64 static void ahci_thaw(struct ata_port *ap);
65 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
66 static void ahci_enable_fbs(struct ata_port *ap);
67 static void ahci_disable_fbs(struct ata_port *ap);
68 static void ahci_pmp_attach(struct ata_port *ap);
69 static void ahci_pmp_detach(struct ata_port *ap);
70 static int ahci_softreset(struct ata_link *link, unsigned int *class,
71 unsigned long deadline);
72 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
73 unsigned long deadline);
74 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
75 unsigned long deadline);
76 static void ahci_postreset(struct ata_link *link, unsigned int *class);
77 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
78 static void ahci_dev_config(struct ata_device *dev);
79 #ifdef CONFIG_PM
80 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
81 #endif
82 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
83 static ssize_t ahci_activity_store(struct ata_device *dev,
84 enum sw_activity val);
85 static void ahci_init_sw_activity(struct ata_link *link);
86
87 static ssize_t ahci_show_host_caps(struct device *dev,
88 struct device_attribute *attr, char *buf);
89 static ssize_t ahci_show_host_cap2(struct device *dev,
90 struct device_attribute *attr, char *buf);
91 static ssize_t ahci_show_host_version(struct device *dev,
92 struct device_attribute *attr, char *buf);
93 static ssize_t ahci_show_port_cmd(struct device *dev,
94 struct device_attribute *attr, char *buf);
95 static ssize_t ahci_read_em_buffer(struct device *dev,
96 struct device_attribute *attr, char *buf);
97 static ssize_t ahci_store_em_buffer(struct device *dev,
98 struct device_attribute *attr,
99 const char *buf, size_t size);
100 static ssize_t ahci_show_em_supported(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
103
104 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
105 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
106 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
107 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
108 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
109 ahci_read_em_buffer, ahci_store_em_buffer);
110 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
111
112 static struct attribute *ahci_shost_attrs[] = {
113 &dev_attr_link_power_management_policy.attr,
114 &dev_attr_em_message_type.attr,
115 &dev_attr_em_message.attr,
116 &dev_attr_ahci_host_caps.attr,
117 &dev_attr_ahci_host_cap2.attr,
118 &dev_attr_ahci_host_version.attr,
119 &dev_attr_ahci_port_cmd.attr,
120 &dev_attr_em_buffer.attr,
121 &dev_attr_em_message_supported.attr,
122 NULL
123 };
124
125 static const struct attribute_group ahci_shost_attr_group = {
126 .attrs = ahci_shost_attrs
127 };
128
129 const struct attribute_group *ahci_shost_groups[] = {
130 &ahci_shost_attr_group,
131 NULL
132 };
133 EXPORT_SYMBOL_GPL(ahci_shost_groups);
134
135 static struct attribute *ahci_sdev_attrs[] = {
136 &dev_attr_sw_activity.attr,
137 &dev_attr_unload_heads.attr,
138 &dev_attr_ncq_prio_supported.attr,
139 &dev_attr_ncq_prio_enable.attr,
140 NULL
141 };
142
143 static const struct attribute_group ahci_sdev_attr_group = {
144 .attrs = ahci_sdev_attrs
145 };
146
147 const struct attribute_group *ahci_sdev_groups[] = {
148 &ahci_sdev_attr_group,
149 NULL
150 };
151 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
152
153 struct ata_port_operations ahci_ops = {
154 .inherits = &sata_pmp_port_ops,
155
156 .qc_defer = ahci_pmp_qc_defer,
157 .qc_prep = ahci_qc_prep,
158 .qc_issue = ahci_qc_issue,
159 .qc_fill_rtf = ahci_qc_fill_rtf,
160
161 .freeze = ahci_freeze,
162 .thaw = ahci_thaw,
163 .softreset = ahci_softreset,
164 .hardreset = ahci_hardreset,
165 .postreset = ahci_postreset,
166 .pmp_softreset = ahci_softreset,
167 .error_handler = ahci_error_handler,
168 .post_internal_cmd = ahci_post_internal_cmd,
169 .dev_config = ahci_dev_config,
170
171 .scr_read = ahci_scr_read,
172 .scr_write = ahci_scr_write,
173 .pmp_attach = ahci_pmp_attach,
174 .pmp_detach = ahci_pmp_detach,
175
176 .set_lpm = ahci_set_lpm,
177 .em_show = ahci_led_show,
178 .em_store = ahci_led_store,
179 .sw_activity_show = ahci_activity_show,
180 .sw_activity_store = ahci_activity_store,
181 .transmit_led_message = ahci_transmit_led_message,
182 #ifdef CONFIG_PM
183 .port_suspend = ahci_port_suspend,
184 .port_resume = ahci_port_resume,
185 #endif
186 .port_start = ahci_port_start,
187 .port_stop = ahci_port_stop,
188 };
189 EXPORT_SYMBOL_GPL(ahci_ops);
190
191 struct ata_port_operations ahci_pmp_retry_srst_ops = {
192 .inherits = &ahci_ops,
193 .softreset = ahci_pmp_retry_softreset,
194 };
195 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
196
197 static bool ahci_em_messages __read_mostly = true;
198 module_param(ahci_em_messages, bool, 0444);
199 /* add other LED protocol types when they become supported */
200 MODULE_PARM_DESC(ahci_em_messages,
201 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
202
203 /* device sleep idle timeout in ms */
204 static int devslp_idle_timeout __read_mostly = 1000;
205 module_param(devslp_idle_timeout, int, 0644);
206 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
207
ahci_enable_ahci(void __iomem * mmio)208 static void ahci_enable_ahci(void __iomem *mmio)
209 {
210 int i;
211 u32 tmp;
212
213 /* turn on AHCI_EN */
214 tmp = readl(mmio + HOST_CTL);
215 if (tmp & HOST_AHCI_EN)
216 return;
217
218 /* Some controllers need AHCI_EN to be written multiple times.
219 * Try a few times before giving up.
220 */
221 for (i = 0; i < 5; i++) {
222 tmp |= HOST_AHCI_EN;
223 writel(tmp, mmio + HOST_CTL);
224 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
225 if (tmp & HOST_AHCI_EN)
226 return;
227 msleep(10);
228 }
229
230 WARN_ON(1);
231 }
232
233 /**
234 * ahci_rpm_get_port - Make sure the port is powered on
235 * @ap: Port to power on
236 *
237 * Whenever there is need to access the AHCI host registers outside of
238 * normal execution paths, call this function to make sure the host is
239 * actually powered on.
240 */
ahci_rpm_get_port(struct ata_port * ap)241 static int ahci_rpm_get_port(struct ata_port *ap)
242 {
243 return pm_runtime_get_sync(ap->dev);
244 }
245
246 /**
247 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
248 * @ap: Port to power down
249 *
250 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
251 * if it has no more active users.
252 */
ahci_rpm_put_port(struct ata_port * ap)253 static void ahci_rpm_put_port(struct ata_port *ap)
254 {
255 pm_runtime_put(ap->dev);
256 }
257
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)258 static ssize_t ahci_show_host_caps(struct device *dev,
259 struct device_attribute *attr, char *buf)
260 {
261 struct Scsi_Host *shost = class_to_shost(dev);
262 struct ata_port *ap = ata_shost_to_port(shost);
263 struct ahci_host_priv *hpriv = ap->host->private_data;
264
265 return sprintf(buf, "%x\n", hpriv->cap);
266 }
267
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)268 static ssize_t ahci_show_host_cap2(struct device *dev,
269 struct device_attribute *attr, char *buf)
270 {
271 struct Scsi_Host *shost = class_to_shost(dev);
272 struct ata_port *ap = ata_shost_to_port(shost);
273 struct ahci_host_priv *hpriv = ap->host->private_data;
274
275 return sprintf(buf, "%x\n", hpriv->cap2);
276 }
277
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)278 static ssize_t ahci_show_host_version(struct device *dev,
279 struct device_attribute *attr, char *buf)
280 {
281 struct Scsi_Host *shost = class_to_shost(dev);
282 struct ata_port *ap = ata_shost_to_port(shost);
283 struct ahci_host_priv *hpriv = ap->host->private_data;
284
285 return sprintf(buf, "%x\n", hpriv->version);
286 }
287
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)288 static ssize_t ahci_show_port_cmd(struct device *dev,
289 struct device_attribute *attr, char *buf)
290 {
291 struct Scsi_Host *shost = class_to_shost(dev);
292 struct ata_port *ap = ata_shost_to_port(shost);
293 void __iomem *port_mmio = ahci_port_base(ap);
294 ssize_t ret;
295
296 ahci_rpm_get_port(ap);
297 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
298 ahci_rpm_put_port(ap);
299
300 return ret;
301 }
302
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)303 static ssize_t ahci_read_em_buffer(struct device *dev,
304 struct device_attribute *attr, char *buf)
305 {
306 struct Scsi_Host *shost = class_to_shost(dev);
307 struct ata_port *ap = ata_shost_to_port(shost);
308 struct ahci_host_priv *hpriv = ap->host->private_data;
309 void __iomem *mmio = hpriv->mmio;
310 void __iomem *em_mmio = mmio + hpriv->em_loc;
311 u32 em_ctl, msg;
312 unsigned long flags;
313 size_t count;
314 int i;
315
316 ahci_rpm_get_port(ap);
317 spin_lock_irqsave(ap->lock, flags);
318
319 em_ctl = readl(mmio + HOST_EM_CTL);
320 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
321 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
322 spin_unlock_irqrestore(ap->lock, flags);
323 ahci_rpm_put_port(ap);
324 return -EINVAL;
325 }
326
327 if (!(em_ctl & EM_CTL_MR)) {
328 spin_unlock_irqrestore(ap->lock, flags);
329 ahci_rpm_put_port(ap);
330 return -EAGAIN;
331 }
332
333 if (!(em_ctl & EM_CTL_SMB))
334 em_mmio += hpriv->em_buf_sz;
335
336 count = hpriv->em_buf_sz;
337
338 /* the count should not be larger than PAGE_SIZE */
339 if (count > PAGE_SIZE) {
340 if (printk_ratelimit())
341 ata_port_warn(ap,
342 "EM read buffer size too large: "
343 "buffer size %u, page size %lu\n",
344 hpriv->em_buf_sz, PAGE_SIZE);
345 count = PAGE_SIZE;
346 }
347
348 for (i = 0; i < count; i += 4) {
349 msg = readl(em_mmio + i);
350 buf[i] = msg & 0xff;
351 buf[i + 1] = (msg >> 8) & 0xff;
352 buf[i + 2] = (msg >> 16) & 0xff;
353 buf[i + 3] = (msg >> 24) & 0xff;
354 }
355
356 spin_unlock_irqrestore(ap->lock, flags);
357 ahci_rpm_put_port(ap);
358
359 return i;
360 }
361
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)362 static ssize_t ahci_store_em_buffer(struct device *dev,
363 struct device_attribute *attr,
364 const char *buf, size_t size)
365 {
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
370 void __iomem *em_mmio = mmio + hpriv->em_loc;
371 const unsigned char *msg_buf = buf;
372 u32 em_ctl, msg;
373 unsigned long flags;
374 int i;
375
376 /* check size validity */
377 if (!(ap->flags & ATA_FLAG_EM) ||
378 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
379 size % 4 || size > hpriv->em_buf_sz)
380 return -EINVAL;
381
382 ahci_rpm_get_port(ap);
383 spin_lock_irqsave(ap->lock, flags);
384
385 em_ctl = readl(mmio + HOST_EM_CTL);
386 if (em_ctl & EM_CTL_TM) {
387 spin_unlock_irqrestore(ap->lock, flags);
388 ahci_rpm_put_port(ap);
389 return -EBUSY;
390 }
391
392 for (i = 0; i < size; i += 4) {
393 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
394 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
395 writel(msg, em_mmio + i);
396 }
397
398 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
399
400 spin_unlock_irqrestore(ap->lock, flags);
401 ahci_rpm_put_port(ap);
402
403 return size;
404 }
405
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)406 static ssize_t ahci_show_em_supported(struct device *dev,
407 struct device_attribute *attr, char *buf)
408 {
409 struct Scsi_Host *shost = class_to_shost(dev);
410 struct ata_port *ap = ata_shost_to_port(shost);
411 struct ahci_host_priv *hpriv = ap->host->private_data;
412 void __iomem *mmio = hpriv->mmio;
413 u32 em_ctl;
414
415 ahci_rpm_get_port(ap);
416 em_ctl = readl(mmio + HOST_EM_CTL);
417 ahci_rpm_put_port(ap);
418
419 return sprintf(buf, "%s%s%s%s\n",
420 em_ctl & EM_CTL_LED ? "led " : "",
421 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
422 em_ctl & EM_CTL_SES ? "ses-2 " : "",
423 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
424 }
425
426 /**
427 * ahci_save_initial_config - Save and fixup initial config values
428 * @dev: target AHCI device
429 * @hpriv: host private area to store config values
430 *
431 * Some registers containing configuration info might be setup by
432 * BIOS and might be cleared on reset. This function saves the
433 * initial values of those registers into @hpriv such that they
434 * can be restored after controller reset.
435 *
436 * If inconsistent, config values are fixed up by this function.
437 *
438 * If it is not set already this function sets hpriv->start_engine to
439 * ahci_start_engine.
440 *
441 * LOCKING:
442 * None.
443 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)444 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
445 {
446 void __iomem *mmio = hpriv->mmio;
447 void __iomem *port_mmio;
448 unsigned long port_map;
449 u32 cap, cap2, vers;
450 int i;
451
452 /* make sure AHCI mode is enabled before accessing CAP */
453 ahci_enable_ahci(mmio);
454
455 /*
456 * Values prefixed with saved_ are written back to the HBA and ports
457 * registers after reset. Values without are used for driver operation.
458 */
459
460 /*
461 * Override HW-init HBA capability fields with the platform-specific
462 * values. The rest of the HBA capabilities are defined as Read-only
463 * and can't be modified in CSR anyway.
464 */
465 cap = readl(mmio + HOST_CAP);
466 if (hpriv->saved_cap)
467 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
468 hpriv->saved_cap = cap;
469
470 /* CAP2 register is only defined for AHCI 1.2 and later */
471 vers = readl(mmio + HOST_VERSION);
472 if ((vers >> 16) > 1 ||
473 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
474 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
475 else
476 hpriv->saved_cap2 = cap2 = 0;
477
478 /* some chips have errata preventing 64bit use */
479 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
480 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
481 cap &= ~HOST_CAP_64;
482 }
483
484 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
485 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
486 cap &= ~HOST_CAP_NCQ;
487 }
488
489 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
490 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
491 cap |= HOST_CAP_NCQ;
492 }
493
494 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
495 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
496 cap &= ~HOST_CAP_PMP;
497 }
498
499 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
500 dev_info(dev,
501 "controller can't do SNTF, turning off CAP_SNTF\n");
502 cap &= ~HOST_CAP_SNTF;
503 }
504
505 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
506 dev_info(dev,
507 "controller can't do DEVSLP, turning off\n");
508 cap2 &= ~HOST_CAP2_SDS;
509 cap2 &= ~HOST_CAP2_SADM;
510 }
511
512 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
513 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
514 cap |= HOST_CAP_FBS;
515 }
516
517 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
518 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
519 cap &= ~HOST_CAP_FBS;
520 }
521
522 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
523 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
524 cap |= HOST_CAP_ALPM;
525 }
526
527 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
528 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
529 cap &= ~HOST_CAP_SXS;
530 }
531
532 /* Override the HBA ports mapping if the platform needs it */
533 port_map = readl(mmio + HOST_PORTS_IMPL);
534 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
535 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
536 port_map, hpriv->saved_port_map);
537 port_map = hpriv->saved_port_map;
538 } else {
539 hpriv->saved_port_map = port_map;
540 }
541
542 if (hpriv->mask_port_map) {
543 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
544 port_map,
545 port_map & hpriv->mask_port_map);
546 port_map &= hpriv->mask_port_map;
547 }
548
549 /* cross check port_map and cap.n_ports */
550 if (port_map) {
551 int map_ports = 0;
552
553 for (i = 0; i < AHCI_MAX_PORTS; i++)
554 if (port_map & (1 << i))
555 map_ports++;
556
557 /* If PI has more ports than n_ports, whine, clear
558 * port_map and let it be generated from n_ports.
559 */
560 if (map_ports > ahci_nr_ports(cap)) {
561 dev_warn(dev,
562 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
563 port_map, ahci_nr_ports(cap));
564 port_map = 0;
565 }
566 }
567
568 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
569 if (!port_map && vers < 0x10300) {
570 port_map = (1 << ahci_nr_ports(cap)) - 1;
571 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
572
573 /* write the fixed up value to the PI register */
574 hpriv->saved_port_map = port_map;
575 }
576
577 /*
578 * Preserve the ports capabilities defined by the platform. Note there
579 * is no need in storing the rest of the P#.CMD fields since they are
580 * volatile.
581 */
582 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
583 if (hpriv->saved_port_cap[i])
584 continue;
585
586 port_mmio = __ahci_port_base(hpriv, i);
587 hpriv->saved_port_cap[i] =
588 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
589 }
590
591 /* record values to use during operation */
592 hpriv->cap = cap;
593 hpriv->cap2 = cap2;
594 hpriv->version = vers;
595 hpriv->port_map = port_map;
596
597 if (!hpriv->start_engine)
598 hpriv->start_engine = ahci_start_engine;
599
600 if (!hpriv->stop_engine)
601 hpriv->stop_engine = ahci_stop_engine;
602
603 if (!hpriv->irq_handler)
604 hpriv->irq_handler = ahci_single_level_irq_intr;
605 }
606 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
607
608 /**
609 * ahci_restore_initial_config - Restore initial config
610 * @host: target ATA host
611 *
612 * Restore initial config stored by ahci_save_initial_config().
613 *
614 * LOCKING:
615 * None.
616 */
ahci_restore_initial_config(struct ata_host * host)617 static void ahci_restore_initial_config(struct ata_host *host)
618 {
619 struct ahci_host_priv *hpriv = host->private_data;
620 unsigned long port_map = hpriv->port_map;
621 void __iomem *mmio = hpriv->mmio;
622 void __iomem *port_mmio;
623 int i;
624
625 writel(hpriv->saved_cap, mmio + HOST_CAP);
626 if (hpriv->saved_cap2)
627 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
628 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
629 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
630
631 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
632 port_mmio = __ahci_port_base(hpriv, i);
633 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
634 }
635 }
636
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)637 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
638 {
639 static const int offset[] = {
640 [SCR_STATUS] = PORT_SCR_STAT,
641 [SCR_CONTROL] = PORT_SCR_CTL,
642 [SCR_ERROR] = PORT_SCR_ERR,
643 [SCR_ACTIVE] = PORT_SCR_ACT,
644 [SCR_NOTIFICATION] = PORT_SCR_NTF,
645 };
646 struct ahci_host_priv *hpriv = ap->host->private_data;
647
648 if (sc_reg < ARRAY_SIZE(offset) &&
649 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
650 return offset[sc_reg];
651 return 0;
652 }
653
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)654 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
655 {
656 void __iomem *port_mmio = ahci_port_base(link->ap);
657 int offset = ahci_scr_offset(link->ap, sc_reg);
658
659 if (offset) {
660 *val = readl(port_mmio + offset);
661 return 0;
662 }
663 return -EINVAL;
664 }
665
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)666 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
667 {
668 void __iomem *port_mmio = ahci_port_base(link->ap);
669 int offset = ahci_scr_offset(link->ap, sc_reg);
670
671 if (offset) {
672 writel(val, port_mmio + offset);
673 return 0;
674 }
675 return -EINVAL;
676 }
677
ahci_start_engine(struct ata_port * ap)678 void ahci_start_engine(struct ata_port *ap)
679 {
680 void __iomem *port_mmio = ahci_port_base(ap);
681 u32 tmp;
682
683 /* start DMA */
684 tmp = readl(port_mmio + PORT_CMD);
685 tmp |= PORT_CMD_START;
686 writel(tmp, port_mmio + PORT_CMD);
687 readl(port_mmio + PORT_CMD); /* flush */
688 }
689 EXPORT_SYMBOL_GPL(ahci_start_engine);
690
ahci_stop_engine(struct ata_port * ap)691 int ahci_stop_engine(struct ata_port *ap)
692 {
693 void __iomem *port_mmio = ahci_port_base(ap);
694 struct ahci_host_priv *hpriv = ap->host->private_data;
695 u32 tmp;
696
697 /*
698 * On some controllers, stopping a port's DMA engine while the port
699 * is in ALPM state (partial or slumber) results in failures on
700 * subsequent DMA engine starts. For those controllers, put the
701 * port back in active state before stopping its DMA engine.
702 */
703 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
704 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
705 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
706 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
707 return -EIO;
708 }
709
710 tmp = readl(port_mmio + PORT_CMD);
711
712 /* check if the HBA is idle */
713 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
714 return 0;
715
716 /*
717 * Don't try to issue commands but return with ENODEV if the
718 * AHCI controller not available anymore (e.g. due to PCIe hot
719 * unplugging). Otherwise a 500ms delay for each port is added.
720 */
721 if (tmp == 0xffffffff) {
722 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
723 return -ENODEV;
724 }
725
726 /* setting HBA to idle */
727 tmp &= ~PORT_CMD_START;
728 writel(tmp, port_mmio + PORT_CMD);
729
730 /* wait for engine to stop. This could be as long as 500 msec */
731 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
732 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
733 if (tmp & PORT_CMD_LIST_ON)
734 return -EIO;
735
736 return 0;
737 }
738 EXPORT_SYMBOL_GPL(ahci_stop_engine);
739
ahci_start_fis_rx(struct ata_port * ap)740 void ahci_start_fis_rx(struct ata_port *ap)
741 {
742 void __iomem *port_mmio = ahci_port_base(ap);
743 struct ahci_host_priv *hpriv = ap->host->private_data;
744 struct ahci_port_priv *pp = ap->private_data;
745 u32 tmp;
746
747 /* set FIS registers */
748 if (hpriv->cap & HOST_CAP_64)
749 writel((pp->cmd_slot_dma >> 16) >> 16,
750 port_mmio + PORT_LST_ADDR_HI);
751 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
752
753 if (hpriv->cap & HOST_CAP_64)
754 writel((pp->rx_fis_dma >> 16) >> 16,
755 port_mmio + PORT_FIS_ADDR_HI);
756 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
757
758 /* enable FIS reception */
759 tmp = readl(port_mmio + PORT_CMD);
760 tmp |= PORT_CMD_FIS_RX;
761 writel(tmp, port_mmio + PORT_CMD);
762
763 /* flush */
764 readl(port_mmio + PORT_CMD);
765 }
766 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
767
ahci_stop_fis_rx(struct ata_port * ap)768 static int ahci_stop_fis_rx(struct ata_port *ap)
769 {
770 void __iomem *port_mmio = ahci_port_base(ap);
771 u32 tmp;
772
773 /* disable FIS reception */
774 tmp = readl(port_mmio + PORT_CMD);
775 tmp &= ~PORT_CMD_FIS_RX;
776 writel(tmp, port_mmio + PORT_CMD);
777
778 /* wait for completion, spec says 500ms, give it 1000 */
779 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
780 PORT_CMD_FIS_ON, 10, 1000);
781 if (tmp & PORT_CMD_FIS_ON)
782 return -EBUSY;
783
784 return 0;
785 }
786
ahci_power_up(struct ata_port * ap)787 static void ahci_power_up(struct ata_port *ap)
788 {
789 struct ahci_host_priv *hpriv = ap->host->private_data;
790 void __iomem *port_mmio = ahci_port_base(ap);
791 u32 cmd;
792
793 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
794
795 /* spin up device */
796 if (hpriv->cap & HOST_CAP_SSS) {
797 cmd |= PORT_CMD_SPIN_UP;
798 writel(cmd, port_mmio + PORT_CMD);
799 }
800
801 /* wake up link */
802 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
803 }
804
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)805 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
806 unsigned int hints)
807 {
808 struct ata_port *ap = link->ap;
809 struct ahci_host_priv *hpriv = ap->host->private_data;
810 struct ahci_port_priv *pp = ap->private_data;
811 void __iomem *port_mmio = ahci_port_base(ap);
812
813 if (policy != ATA_LPM_MAX_POWER) {
814 /* wakeup flag only applies to the max power policy */
815 hints &= ~ATA_LPM_WAKE_ONLY;
816
817 /*
818 * Disable interrupts on Phy Ready. This keeps us from
819 * getting woken up due to spurious phy ready
820 * interrupts.
821 */
822 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
823 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
824
825 sata_link_scr_lpm(link, policy, false);
826 }
827
828 if (hpriv->cap & HOST_CAP_ALPM) {
829 u32 cmd = readl(port_mmio + PORT_CMD);
830
831 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
832 if (!(hints & ATA_LPM_WAKE_ONLY))
833 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
834 cmd |= PORT_CMD_ICC_ACTIVE;
835
836 writel(cmd, port_mmio + PORT_CMD);
837 readl(port_mmio + PORT_CMD);
838
839 /* wait 10ms to be sure we've come out of LPM state */
840 ata_msleep(ap, 10);
841
842 if (hints & ATA_LPM_WAKE_ONLY)
843 return 0;
844 } else {
845 cmd |= PORT_CMD_ALPE;
846 if (policy == ATA_LPM_MIN_POWER)
847 cmd |= PORT_CMD_ASP;
848 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
849 cmd &= ~PORT_CMD_ASP;
850
851 /* write out new cmd value */
852 writel(cmd, port_mmio + PORT_CMD);
853 }
854 }
855
856 /* set aggressive device sleep */
857 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
858 (hpriv->cap2 & HOST_CAP2_SADM) &&
859 (link->device->flags & ATA_DFLAG_DEVSLP)) {
860 if (policy == ATA_LPM_MIN_POWER ||
861 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
862 ahci_set_aggressive_devslp(ap, true);
863 else
864 ahci_set_aggressive_devslp(ap, false);
865 }
866
867 if (policy == ATA_LPM_MAX_POWER) {
868 sata_link_scr_lpm(link, policy, false);
869
870 /* turn PHYRDY IRQ back on */
871 pp->intr_mask |= PORT_IRQ_PHYRDY;
872 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
873 }
874
875 return 0;
876 }
877
878 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)879 static void ahci_power_down(struct ata_port *ap)
880 {
881 struct ahci_host_priv *hpriv = ap->host->private_data;
882 void __iomem *port_mmio = ahci_port_base(ap);
883 u32 cmd, scontrol;
884
885 if (!(hpriv->cap & HOST_CAP_SSS))
886 return;
887
888 /* put device into listen mode, first set PxSCTL.DET to 0 */
889 scontrol = readl(port_mmio + PORT_SCR_CTL);
890 scontrol &= ~0xf;
891 writel(scontrol, port_mmio + PORT_SCR_CTL);
892
893 /* then set PxCMD.SUD to 0 */
894 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
895 cmd &= ~PORT_CMD_SPIN_UP;
896 writel(cmd, port_mmio + PORT_CMD);
897 }
898 #endif
899
ahci_start_port(struct ata_port * ap)900 static void ahci_start_port(struct ata_port *ap)
901 {
902 struct ahci_host_priv *hpriv = ap->host->private_data;
903 struct ahci_port_priv *pp = ap->private_data;
904 struct ata_link *link;
905 struct ahci_em_priv *emp;
906 ssize_t rc;
907 int i;
908
909 /* enable FIS reception */
910 ahci_start_fis_rx(ap);
911
912 /* enable DMA */
913 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
914 hpriv->start_engine(ap);
915
916 /* turn on LEDs */
917 if (ap->flags & ATA_FLAG_EM) {
918 ata_for_each_link(link, ap, EDGE) {
919 emp = &pp->em_priv[link->pmp];
920
921 /* EM Transmit bit maybe busy during init */
922 for (i = 0; i < EM_MAX_RETRY; i++) {
923 rc = ap->ops->transmit_led_message(ap,
924 emp->led_state,
925 4);
926 /*
927 * If busy, give a breather but do not
928 * release EH ownership by using msleep()
929 * instead of ata_msleep(). EM Transmit
930 * bit is busy for the whole host and
931 * releasing ownership will cause other
932 * ports to fail the same way.
933 */
934 if (rc == -EBUSY)
935 msleep(1);
936 else
937 break;
938 }
939 }
940 }
941
942 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
943 ata_for_each_link(link, ap, EDGE)
944 ahci_init_sw_activity(link);
945
946 }
947
ahci_deinit_port(struct ata_port * ap,const char ** emsg)948 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
949 {
950 int rc;
951 struct ahci_host_priv *hpriv = ap->host->private_data;
952
953 /* disable DMA */
954 rc = hpriv->stop_engine(ap);
955 if (rc) {
956 *emsg = "failed to stop engine";
957 return rc;
958 }
959
960 /* disable FIS reception */
961 rc = ahci_stop_fis_rx(ap);
962 if (rc) {
963 *emsg = "failed stop FIS RX";
964 return rc;
965 }
966
967 return 0;
968 }
969
ahci_reset_controller(struct ata_host * host)970 int ahci_reset_controller(struct ata_host *host)
971 {
972 struct ahci_host_priv *hpriv = host->private_data;
973 void __iomem *mmio = hpriv->mmio;
974 u32 tmp;
975
976 /* we must be in AHCI mode, before using anything
977 * AHCI-specific, such as HOST_RESET.
978 */
979 ahci_enable_ahci(mmio);
980
981 /* global controller reset */
982 if (!ahci_skip_host_reset) {
983 tmp = readl(mmio + HOST_CTL);
984 if ((tmp & HOST_RESET) == 0) {
985 writel(tmp | HOST_RESET, mmio + HOST_CTL);
986 readl(mmio + HOST_CTL); /* flush */
987 }
988
989 /*
990 * to perform host reset, OS should set HOST_RESET
991 * and poll until this bit is read to be "0".
992 * reset must complete within 1 second, or
993 * the hardware should be considered fried.
994 */
995 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
996 HOST_RESET, 10, 1000);
997
998 if (tmp & HOST_RESET) {
999 dev_err(host->dev, "controller reset failed (0x%x)\n",
1000 tmp);
1001 return -EIO;
1002 }
1003
1004 /* turn on AHCI mode */
1005 ahci_enable_ahci(mmio);
1006
1007 /* Some registers might be cleared on reset. Restore
1008 * initial values.
1009 */
1010 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
1011 ahci_restore_initial_config(host);
1012 } else
1013 dev_info(host->dev, "skipping global host reset\n");
1014
1015 return 0;
1016 }
1017 EXPORT_SYMBOL_GPL(ahci_reset_controller);
1018
ahci_sw_activity(struct ata_link * link)1019 static void ahci_sw_activity(struct ata_link *link)
1020 {
1021 struct ata_port *ap = link->ap;
1022 struct ahci_port_priv *pp = ap->private_data;
1023 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1024
1025 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1026 return;
1027
1028 emp->activity++;
1029 if (!timer_pending(&emp->timer))
1030 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1031 }
1032
ahci_sw_activity_blink(struct timer_list * t)1033 static void ahci_sw_activity_blink(struct timer_list *t)
1034 {
1035 struct ahci_em_priv *emp = from_timer(emp, t, timer);
1036 struct ata_link *link = emp->link;
1037 struct ata_port *ap = link->ap;
1038
1039 unsigned long led_message = emp->led_state;
1040 u32 activity_led_state;
1041 unsigned long flags;
1042
1043 led_message &= EM_MSG_LED_VALUE;
1044 led_message |= ap->port_no | (link->pmp << 8);
1045
1046 /* check to see if we've had activity. If so,
1047 * toggle state of LED and reset timer. If not,
1048 * turn LED to desired idle state.
1049 */
1050 spin_lock_irqsave(ap->lock, flags);
1051 if (emp->saved_activity != emp->activity) {
1052 emp->saved_activity = emp->activity;
1053 /* get the current LED state */
1054 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1055
1056 if (activity_led_state)
1057 activity_led_state = 0;
1058 else
1059 activity_led_state = 1;
1060
1061 /* clear old state */
1062 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1063
1064 /* toggle state */
1065 led_message |= (activity_led_state << 16);
1066 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1067 } else {
1068 /* switch to idle */
1069 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1070 if (emp->blink_policy == BLINK_OFF)
1071 led_message |= (1 << 16);
1072 }
1073 spin_unlock_irqrestore(ap->lock, flags);
1074 ap->ops->transmit_led_message(ap, led_message, 4);
1075 }
1076
ahci_init_sw_activity(struct ata_link * link)1077 static void ahci_init_sw_activity(struct ata_link *link)
1078 {
1079 struct ata_port *ap = link->ap;
1080 struct ahci_port_priv *pp = ap->private_data;
1081 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1082
1083 /* init activity stats, setup timer */
1084 emp->saved_activity = emp->activity = 0;
1085 emp->link = link;
1086 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1087
1088 /* check our blink policy and set flag for link if it's enabled */
1089 if (emp->blink_policy)
1090 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1091 }
1092
ahci_reset_em(struct ata_host * host)1093 int ahci_reset_em(struct ata_host *host)
1094 {
1095 struct ahci_host_priv *hpriv = host->private_data;
1096 void __iomem *mmio = hpriv->mmio;
1097 u32 em_ctl;
1098
1099 em_ctl = readl(mmio + HOST_EM_CTL);
1100 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1101 return -EINVAL;
1102
1103 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1104 return 0;
1105 }
1106 EXPORT_SYMBOL_GPL(ahci_reset_em);
1107
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1108 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1109 ssize_t size)
1110 {
1111 struct ahci_host_priv *hpriv = ap->host->private_data;
1112 struct ahci_port_priv *pp = ap->private_data;
1113 void __iomem *mmio = hpriv->mmio;
1114 u32 em_ctl;
1115 u32 message[] = {0, 0};
1116 unsigned long flags;
1117 int pmp;
1118 struct ahci_em_priv *emp;
1119
1120 /* get the slot number from the message */
1121 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1122 if (pmp < EM_MAX_SLOTS)
1123 emp = &pp->em_priv[pmp];
1124 else
1125 return -EINVAL;
1126
1127 ahci_rpm_get_port(ap);
1128 spin_lock_irqsave(ap->lock, flags);
1129
1130 /*
1131 * if we are still busy transmitting a previous message,
1132 * do not allow
1133 */
1134 em_ctl = readl(mmio + HOST_EM_CTL);
1135 if (em_ctl & EM_CTL_TM) {
1136 spin_unlock_irqrestore(ap->lock, flags);
1137 ahci_rpm_put_port(ap);
1138 return -EBUSY;
1139 }
1140
1141 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1142 /*
1143 * create message header - this is all zero except for
1144 * the message size, which is 4 bytes.
1145 */
1146 message[0] |= (4 << 8);
1147
1148 /* ignore 0:4 of byte zero, fill in port info yourself */
1149 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1150
1151 /* write message to EM_LOC */
1152 writel(message[0], mmio + hpriv->em_loc);
1153 writel(message[1], mmio + hpriv->em_loc+4);
1154
1155 /*
1156 * tell hardware to transmit the message
1157 */
1158 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1159 }
1160
1161 /* save off new led state for port/slot */
1162 emp->led_state = state;
1163
1164 spin_unlock_irqrestore(ap->lock, flags);
1165 ahci_rpm_put_port(ap);
1166
1167 return size;
1168 }
1169
ahci_led_show(struct ata_port * ap,char * buf)1170 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1171 {
1172 struct ahci_port_priv *pp = ap->private_data;
1173 struct ata_link *link;
1174 struct ahci_em_priv *emp;
1175 int rc = 0;
1176
1177 ata_for_each_link(link, ap, EDGE) {
1178 emp = &pp->em_priv[link->pmp];
1179 rc += sprintf(buf, "%lx\n", emp->led_state);
1180 }
1181 return rc;
1182 }
1183
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1184 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1185 size_t size)
1186 {
1187 unsigned int state;
1188 int pmp;
1189 struct ahci_port_priv *pp = ap->private_data;
1190 struct ahci_em_priv *emp;
1191
1192 if (kstrtouint(buf, 0, &state) < 0)
1193 return -EINVAL;
1194
1195 /* get the slot number from the message */
1196 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1197 if (pmp < EM_MAX_SLOTS) {
1198 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1199 emp = &pp->em_priv[pmp];
1200 } else {
1201 return -EINVAL;
1202 }
1203
1204 /* mask off the activity bits if we are in sw_activity
1205 * mode, user should turn off sw_activity before setting
1206 * activity led through em_message
1207 */
1208 if (emp->blink_policy)
1209 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1210
1211 return ap->ops->transmit_led_message(ap, state, size);
1212 }
1213
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1214 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1215 {
1216 struct ata_link *link = dev->link;
1217 struct ata_port *ap = link->ap;
1218 struct ahci_port_priv *pp = ap->private_data;
1219 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1220 u32 port_led_state = emp->led_state;
1221
1222 /* save the desired Activity LED behavior */
1223 if (val == OFF) {
1224 /* clear LFLAG */
1225 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1226
1227 /* set the LED to OFF */
1228 port_led_state &= EM_MSG_LED_VALUE_OFF;
1229 port_led_state |= (ap->port_no | (link->pmp << 8));
1230 ap->ops->transmit_led_message(ap, port_led_state, 4);
1231 } else {
1232 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1233 if (val == BLINK_OFF) {
1234 /* set LED to ON for idle */
1235 port_led_state &= EM_MSG_LED_VALUE_OFF;
1236 port_led_state |= (ap->port_no | (link->pmp << 8));
1237 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1238 ap->ops->transmit_led_message(ap, port_led_state, 4);
1239 }
1240 }
1241 emp->blink_policy = val;
1242 return 0;
1243 }
1244
ahci_activity_show(struct ata_device * dev,char * buf)1245 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1246 {
1247 struct ata_link *link = dev->link;
1248 struct ata_port *ap = link->ap;
1249 struct ahci_port_priv *pp = ap->private_data;
1250 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1251
1252 /* display the saved value of activity behavior for this
1253 * disk.
1254 */
1255 return sprintf(buf, "%d\n", emp->blink_policy);
1256 }
1257
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1258 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1259 int port_no, void __iomem *mmio,
1260 void __iomem *port_mmio)
1261 {
1262 struct ahci_host_priv *hpriv = ap->host->private_data;
1263 const char *emsg = NULL;
1264 int rc;
1265 u32 tmp;
1266
1267 /* make sure port is not active */
1268 rc = ahci_deinit_port(ap, &emsg);
1269 if (rc)
1270 dev_warn(dev, "%s (%d)\n", emsg, rc);
1271
1272 /* clear SError */
1273 tmp = readl(port_mmio + PORT_SCR_ERR);
1274 dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
1275 writel(tmp, port_mmio + PORT_SCR_ERR);
1276
1277 /* clear port IRQ */
1278 tmp = readl(port_mmio + PORT_IRQ_STAT);
1279 dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1280 if (tmp)
1281 writel(tmp, port_mmio + PORT_IRQ_STAT);
1282
1283 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1284
1285 /* mark esata ports */
1286 tmp = readl(port_mmio + PORT_CMD);
1287 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1288 ap->pflags |= ATA_PFLAG_EXTERNAL;
1289 }
1290
ahci_init_controller(struct ata_host * host)1291 void ahci_init_controller(struct ata_host *host)
1292 {
1293 struct ahci_host_priv *hpriv = host->private_data;
1294 void __iomem *mmio = hpriv->mmio;
1295 int i;
1296 void __iomem *port_mmio;
1297 u32 tmp;
1298
1299 for (i = 0; i < host->n_ports; i++) {
1300 struct ata_port *ap = host->ports[i];
1301
1302 port_mmio = ahci_port_base(ap);
1303 if (ata_port_is_dummy(ap))
1304 continue;
1305
1306 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1307 }
1308
1309 tmp = readl(mmio + HOST_CTL);
1310 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1311 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1312 tmp = readl(mmio + HOST_CTL);
1313 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1314 }
1315 EXPORT_SYMBOL_GPL(ahci_init_controller);
1316
ahci_dev_config(struct ata_device * dev)1317 static void ahci_dev_config(struct ata_device *dev)
1318 {
1319 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1320
1321 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1322 dev->max_sectors = 255;
1323 ata_dev_info(dev,
1324 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1325 }
1326 }
1327
ahci_dev_classify(struct ata_port * ap)1328 unsigned int ahci_dev_classify(struct ata_port *ap)
1329 {
1330 void __iomem *port_mmio = ahci_port_base(ap);
1331 struct ata_taskfile tf;
1332 u32 tmp;
1333
1334 tmp = readl(port_mmio + PORT_SIG);
1335 tf.lbah = (tmp >> 24) & 0xff;
1336 tf.lbam = (tmp >> 16) & 0xff;
1337 tf.lbal = (tmp >> 8) & 0xff;
1338 tf.nsect = (tmp) & 0xff;
1339
1340 return ata_port_classify(ap, &tf);
1341 }
1342 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1343
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1344 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1345 u32 opts)
1346 {
1347 dma_addr_t cmd_tbl_dma;
1348
1349 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1350
1351 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1352 pp->cmd_slot[tag].status = 0;
1353 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1354 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1355 }
1356 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1357
ahci_kick_engine(struct ata_port * ap)1358 int ahci_kick_engine(struct ata_port *ap)
1359 {
1360 void __iomem *port_mmio = ahci_port_base(ap);
1361 struct ahci_host_priv *hpriv = ap->host->private_data;
1362 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1363 u32 tmp;
1364 int busy, rc;
1365
1366 /* stop engine */
1367 rc = hpriv->stop_engine(ap);
1368 if (rc)
1369 goto out_restart;
1370
1371 /* need to do CLO?
1372 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1373 */
1374 busy = status & (ATA_BUSY | ATA_DRQ);
1375 if (!busy && !sata_pmp_attached(ap)) {
1376 rc = 0;
1377 goto out_restart;
1378 }
1379
1380 if (!(hpriv->cap & HOST_CAP_CLO)) {
1381 rc = -EOPNOTSUPP;
1382 goto out_restart;
1383 }
1384
1385 /* perform CLO */
1386 tmp = readl(port_mmio + PORT_CMD);
1387 tmp |= PORT_CMD_CLO;
1388 writel(tmp, port_mmio + PORT_CMD);
1389
1390 rc = 0;
1391 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1392 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1393 if (tmp & PORT_CMD_CLO)
1394 rc = -EIO;
1395
1396 /* restart engine */
1397 out_restart:
1398 hpriv->start_engine(ap);
1399 return rc;
1400 }
1401 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1402
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1403 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1404 struct ata_taskfile *tf, int is_cmd, u16 flags,
1405 unsigned long timeout_msec)
1406 {
1407 const u32 cmd_fis_len = 5; /* five dwords */
1408 struct ahci_port_priv *pp = ap->private_data;
1409 void __iomem *port_mmio = ahci_port_base(ap);
1410 u8 *fis = pp->cmd_tbl;
1411 u32 tmp;
1412
1413 /* prep the command */
1414 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1415 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1416
1417 /* set port value for softreset of Port Multiplier */
1418 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1419 tmp = readl(port_mmio + PORT_FBS);
1420 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1421 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1422 writel(tmp, port_mmio + PORT_FBS);
1423 pp->fbs_last_dev = pmp;
1424 }
1425
1426 /* issue & wait */
1427 writel(1, port_mmio + PORT_CMD_ISSUE);
1428
1429 if (timeout_msec) {
1430 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1431 0x1, 0x1, 1, timeout_msec);
1432 if (tmp & 0x1) {
1433 ahci_kick_engine(ap);
1434 return -EBUSY;
1435 }
1436 } else
1437 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1438
1439 return 0;
1440 }
1441
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1442 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1443 int pmp, unsigned long deadline,
1444 int (*check_ready)(struct ata_link *link))
1445 {
1446 struct ata_port *ap = link->ap;
1447 struct ahci_host_priv *hpriv = ap->host->private_data;
1448 struct ahci_port_priv *pp = ap->private_data;
1449 const char *reason = NULL;
1450 unsigned long now, msecs;
1451 struct ata_taskfile tf;
1452 bool fbs_disabled = false;
1453 int rc;
1454
1455 /* prepare for SRST (AHCI-1.1 10.4.1) */
1456 rc = ahci_kick_engine(ap);
1457 if (rc && rc != -EOPNOTSUPP)
1458 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1459
1460 /*
1461 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1462 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1463 * that is attached to port multiplier.
1464 */
1465 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1466 ahci_disable_fbs(ap);
1467 fbs_disabled = true;
1468 }
1469
1470 ata_tf_init(link->device, &tf);
1471
1472 /* issue the first H2D Register FIS */
1473 msecs = 0;
1474 now = jiffies;
1475 if (time_after(deadline, now))
1476 msecs = jiffies_to_msecs(deadline - now);
1477
1478 tf.ctl |= ATA_SRST;
1479 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1480 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1481 rc = -EIO;
1482 reason = "1st FIS failed";
1483 goto fail;
1484 }
1485
1486 /* spec says at least 5us, but be generous and sleep for 1ms */
1487 ata_msleep(ap, 1);
1488
1489 /* issue the second H2D Register FIS */
1490 tf.ctl &= ~ATA_SRST;
1491 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1492
1493 /* wait for link to become ready */
1494 rc = ata_wait_after_reset(link, deadline, check_ready);
1495 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1496 /*
1497 * Workaround for cases where link online status can't
1498 * be trusted. Treat device readiness timeout as link
1499 * offline.
1500 */
1501 ata_link_info(link, "device not ready, treating as offline\n");
1502 *class = ATA_DEV_NONE;
1503 } else if (rc) {
1504 /* link occupied, -ENODEV too is an error */
1505 reason = "device not ready";
1506 goto fail;
1507 } else
1508 *class = ahci_dev_classify(ap);
1509
1510 /* re-enable FBS if disabled before */
1511 if (fbs_disabled)
1512 ahci_enable_fbs(ap);
1513
1514 return 0;
1515
1516 fail:
1517 ata_link_err(link, "softreset failed (%s)\n", reason);
1518 return rc;
1519 }
1520
ahci_check_ready(struct ata_link * link)1521 int ahci_check_ready(struct ata_link *link)
1522 {
1523 void __iomem *port_mmio = ahci_port_base(link->ap);
1524 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1525
1526 return ata_check_ready(status);
1527 }
1528 EXPORT_SYMBOL_GPL(ahci_check_ready);
1529
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1530 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1531 unsigned long deadline)
1532 {
1533 int pmp = sata_srst_pmp(link);
1534
1535 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1536 }
1537 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1538
ahci_bad_pmp_check_ready(struct ata_link * link)1539 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1540 {
1541 void __iomem *port_mmio = ahci_port_base(link->ap);
1542 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1543 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1544
1545 /*
1546 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1547 * which can save timeout delay.
1548 */
1549 if (irq_status & PORT_IRQ_BAD_PMP)
1550 return -EIO;
1551
1552 return ata_check_ready(status);
1553 }
1554
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1555 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1556 unsigned long deadline)
1557 {
1558 struct ata_port *ap = link->ap;
1559 void __iomem *port_mmio = ahci_port_base(ap);
1560 int pmp = sata_srst_pmp(link);
1561 int rc;
1562 u32 irq_sts;
1563
1564 rc = ahci_do_softreset(link, class, pmp, deadline,
1565 ahci_bad_pmp_check_ready);
1566
1567 /*
1568 * Soft reset fails with IPMS set when PMP is enabled but
1569 * SATA HDD/ODD is connected to SATA port, do soft reset
1570 * again to port 0.
1571 */
1572 if (rc == -EIO) {
1573 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1574 if (irq_sts & PORT_IRQ_BAD_PMP) {
1575 ata_link_warn(link,
1576 "applying PMP SRST workaround "
1577 "and retrying\n");
1578 rc = ahci_do_softreset(link, class, 0, deadline,
1579 ahci_check_ready);
1580 }
1581 }
1582
1583 return rc;
1584 }
1585
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1586 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1587 unsigned long deadline, bool *online)
1588 {
1589 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1590 struct ata_port *ap = link->ap;
1591 struct ahci_port_priv *pp = ap->private_data;
1592 struct ahci_host_priv *hpriv = ap->host->private_data;
1593 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1594 struct ata_taskfile tf;
1595 int rc;
1596
1597 hpriv->stop_engine(ap);
1598
1599 /* clear D2H reception area to properly wait for D2H FIS */
1600 ata_tf_init(link->device, &tf);
1601 tf.status = ATA_BUSY;
1602 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1603
1604 rc = sata_link_hardreset(link, timing, deadline, online,
1605 ahci_check_ready);
1606
1607 hpriv->start_engine(ap);
1608
1609 if (*online)
1610 *class = ahci_dev_classify(ap);
1611
1612 return rc;
1613 }
1614 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1615
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1616 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1617 unsigned long deadline)
1618 {
1619 bool online;
1620
1621 return ahci_do_hardreset(link, class, deadline, &online);
1622 }
1623
ahci_postreset(struct ata_link * link,unsigned int * class)1624 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1625 {
1626 struct ata_port *ap = link->ap;
1627 void __iomem *port_mmio = ahci_port_base(ap);
1628 u32 new_tmp, tmp;
1629
1630 ata_std_postreset(link, class);
1631
1632 /* Make sure port's ATAPI bit is set appropriately */
1633 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1634 if (*class == ATA_DEV_ATAPI)
1635 new_tmp |= PORT_CMD_ATAPI;
1636 else
1637 new_tmp &= ~PORT_CMD_ATAPI;
1638 if (new_tmp != tmp) {
1639 writel(new_tmp, port_mmio + PORT_CMD);
1640 readl(port_mmio + PORT_CMD); /* flush */
1641 }
1642 }
1643
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1644 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1645 {
1646 struct scatterlist *sg;
1647 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1648 unsigned int si;
1649
1650 /*
1651 * Next, the S/G list.
1652 */
1653 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1654 dma_addr_t addr = sg_dma_address(sg);
1655 u32 sg_len = sg_dma_len(sg);
1656
1657 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1658 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1659 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1660 }
1661
1662 return si;
1663 }
1664
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1665 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1666 {
1667 struct ata_port *ap = qc->ap;
1668 struct ahci_port_priv *pp = ap->private_data;
1669
1670 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1671 return ata_std_qc_defer(qc);
1672 else
1673 return sata_pmp_qc_defer_cmd_switch(qc);
1674 }
1675
ahci_qc_prep(struct ata_queued_cmd * qc)1676 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1677 {
1678 struct ata_port *ap = qc->ap;
1679 struct ahci_port_priv *pp = ap->private_data;
1680 int is_atapi = ata_is_atapi(qc->tf.protocol);
1681 void *cmd_tbl;
1682 u32 opts;
1683 const u32 cmd_fis_len = 5; /* five dwords */
1684 unsigned int n_elem;
1685
1686 /*
1687 * Fill in command table information. First, the header,
1688 * a SATA Register - Host to Device command FIS.
1689 */
1690 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1691
1692 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1693 if (is_atapi) {
1694 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1695 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1696 }
1697
1698 n_elem = 0;
1699 if (qc->flags & ATA_QCFLAG_DMAMAP)
1700 n_elem = ahci_fill_sg(qc, cmd_tbl);
1701
1702 /*
1703 * Fill in command slot information.
1704 */
1705 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1706 if (qc->tf.flags & ATA_TFLAG_WRITE)
1707 opts |= AHCI_CMD_WRITE;
1708 if (is_atapi)
1709 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1710
1711 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1712
1713 return AC_ERR_OK;
1714 }
1715
ahci_fbs_dec_intr(struct ata_port * ap)1716 static void ahci_fbs_dec_intr(struct ata_port *ap)
1717 {
1718 struct ahci_port_priv *pp = ap->private_data;
1719 void __iomem *port_mmio = ahci_port_base(ap);
1720 u32 fbs = readl(port_mmio + PORT_FBS);
1721 int retries = 3;
1722
1723 BUG_ON(!pp->fbs_enabled);
1724
1725 /* time to wait for DEC is not specified by AHCI spec,
1726 * add a retry loop for safety.
1727 */
1728 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1729 fbs = readl(port_mmio + PORT_FBS);
1730 while ((fbs & PORT_FBS_DEC) && retries--) {
1731 udelay(1);
1732 fbs = readl(port_mmio + PORT_FBS);
1733 }
1734
1735 if (fbs & PORT_FBS_DEC)
1736 dev_err(ap->host->dev, "failed to clear device error\n");
1737 }
1738
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1739 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1740 {
1741 struct ahci_host_priv *hpriv = ap->host->private_data;
1742 struct ahci_port_priv *pp = ap->private_data;
1743 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1744 struct ata_link *link = NULL;
1745 struct ata_queued_cmd *active_qc;
1746 struct ata_eh_info *active_ehi;
1747 bool fbs_need_dec = false;
1748 u32 serror;
1749
1750 /* determine active link with error */
1751 if (pp->fbs_enabled) {
1752 void __iomem *port_mmio = ahci_port_base(ap);
1753 u32 fbs = readl(port_mmio + PORT_FBS);
1754 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1755
1756 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1757 link = &ap->pmp_link[pmp];
1758 fbs_need_dec = true;
1759 }
1760
1761 } else
1762 ata_for_each_link(link, ap, EDGE)
1763 if (ata_link_active(link))
1764 break;
1765
1766 if (!link)
1767 link = &ap->link;
1768
1769 active_qc = ata_qc_from_tag(ap, link->active_tag);
1770 active_ehi = &link->eh_info;
1771
1772 /* record irq stat */
1773 ata_ehi_clear_desc(host_ehi);
1774 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1775
1776 /* AHCI needs SError cleared; otherwise, it might lock up */
1777 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1778 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1779 host_ehi->serror |= serror;
1780
1781 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1782 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1783 irq_stat &= ~PORT_IRQ_IF_ERR;
1784
1785 if (irq_stat & PORT_IRQ_TF_ERR) {
1786 /* If qc is active, charge it; otherwise, the active
1787 * link. There's no active qc on NCQ errors. It will
1788 * be determined by EH by reading log page 10h.
1789 */
1790 if (active_qc)
1791 active_qc->err_mask |= AC_ERR_DEV;
1792 else
1793 active_ehi->err_mask |= AC_ERR_DEV;
1794
1795 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1796 host_ehi->serror &= ~SERR_INTERNAL;
1797 }
1798
1799 if (irq_stat & PORT_IRQ_UNK_FIS) {
1800 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1801
1802 active_ehi->err_mask |= AC_ERR_HSM;
1803 active_ehi->action |= ATA_EH_RESET;
1804 ata_ehi_push_desc(active_ehi,
1805 "unknown FIS %08x %08x %08x %08x" ,
1806 unk[0], unk[1], unk[2], unk[3]);
1807 }
1808
1809 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1810 active_ehi->err_mask |= AC_ERR_HSM;
1811 active_ehi->action |= ATA_EH_RESET;
1812 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1813 }
1814
1815 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1816 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1817 host_ehi->action |= ATA_EH_RESET;
1818 ata_ehi_push_desc(host_ehi, "host bus error");
1819 }
1820
1821 if (irq_stat & PORT_IRQ_IF_ERR) {
1822 if (fbs_need_dec)
1823 active_ehi->err_mask |= AC_ERR_DEV;
1824 else {
1825 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1826 host_ehi->action |= ATA_EH_RESET;
1827 }
1828
1829 ata_ehi_push_desc(host_ehi, "interface fatal error");
1830 }
1831
1832 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1833 ata_ehi_hotplugged(host_ehi);
1834 ata_ehi_push_desc(host_ehi, "%s",
1835 irq_stat & PORT_IRQ_CONNECT ?
1836 "connection status changed" : "PHY RDY changed");
1837 }
1838
1839 /* okay, let's hand over to EH */
1840
1841 if (irq_stat & PORT_IRQ_FREEZE)
1842 ata_port_freeze(ap);
1843 else if (fbs_need_dec) {
1844 ata_link_abort(link);
1845 ahci_fbs_dec_intr(ap);
1846 } else
1847 ata_port_abort(ap);
1848 }
1849
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1850 static void ahci_handle_port_interrupt(struct ata_port *ap,
1851 void __iomem *port_mmio, u32 status)
1852 {
1853 struct ata_eh_info *ehi = &ap->link.eh_info;
1854 struct ahci_port_priv *pp = ap->private_data;
1855 struct ahci_host_priv *hpriv = ap->host->private_data;
1856 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1857 u32 qc_active = 0;
1858 int rc;
1859
1860 /* ignore BAD_PMP while resetting */
1861 if (unlikely(resetting))
1862 status &= ~PORT_IRQ_BAD_PMP;
1863
1864 if (sata_lpm_ignore_phy_events(&ap->link)) {
1865 status &= ~PORT_IRQ_PHYRDY;
1866 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1867 }
1868
1869 if (unlikely(status & PORT_IRQ_ERROR)) {
1870 ahci_error_intr(ap, status);
1871 return;
1872 }
1873
1874 if (status & PORT_IRQ_SDB_FIS) {
1875 /* If SNotification is available, leave notification
1876 * handling to sata_async_notification(). If not,
1877 * emulate it by snooping SDB FIS RX area.
1878 *
1879 * Snooping FIS RX area is probably cheaper than
1880 * poking SNotification but some constrollers which
1881 * implement SNotification, ICH9 for example, don't
1882 * store AN SDB FIS into receive area.
1883 */
1884 if (hpriv->cap & HOST_CAP_SNTF)
1885 sata_async_notification(ap);
1886 else {
1887 /* If the 'N' bit in word 0 of the FIS is set,
1888 * we just received asynchronous notification.
1889 * Tell libata about it.
1890 *
1891 * Lack of SNotification should not appear in
1892 * ahci 1.2, so the workaround is unnecessary
1893 * when FBS is enabled.
1894 */
1895 if (pp->fbs_enabled)
1896 WARN_ON_ONCE(1);
1897 else {
1898 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1899 u32 f0 = le32_to_cpu(f[0]);
1900 if (f0 & (1 << 15))
1901 sata_async_notification(ap);
1902 }
1903 }
1904 }
1905
1906 /* pp->active_link is not reliable once FBS is enabled, both
1907 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1908 * NCQ and non-NCQ commands may be in flight at the same time.
1909 */
1910 if (pp->fbs_enabled) {
1911 if (ap->qc_active) {
1912 qc_active = readl(port_mmio + PORT_SCR_ACT);
1913 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1914 }
1915 } else {
1916 /* pp->active_link is valid iff any command is in flight */
1917 if (ap->qc_active && pp->active_link->sactive)
1918 qc_active = readl(port_mmio + PORT_SCR_ACT);
1919 else
1920 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1921 }
1922
1923
1924 rc = ata_qc_complete_multiple(ap, qc_active);
1925
1926 /* while resetting, invalid completions are expected */
1927 if (unlikely(rc < 0 && !resetting)) {
1928 ehi->err_mask |= AC_ERR_HSM;
1929 ehi->action |= ATA_EH_RESET;
1930 ata_port_freeze(ap);
1931 }
1932 }
1933
ahci_port_intr(struct ata_port * ap)1934 static void ahci_port_intr(struct ata_port *ap)
1935 {
1936 void __iomem *port_mmio = ahci_port_base(ap);
1937 u32 status;
1938
1939 status = readl(port_mmio + PORT_IRQ_STAT);
1940 writel(status, port_mmio + PORT_IRQ_STAT);
1941
1942 ahci_handle_port_interrupt(ap, port_mmio, status);
1943 }
1944
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1945 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1946 {
1947 struct ata_port *ap = dev_instance;
1948 void __iomem *port_mmio = ahci_port_base(ap);
1949 u32 status;
1950
1951 status = readl(port_mmio + PORT_IRQ_STAT);
1952 writel(status, port_mmio + PORT_IRQ_STAT);
1953
1954 spin_lock(ap->lock);
1955 ahci_handle_port_interrupt(ap, port_mmio, status);
1956 spin_unlock(ap->lock);
1957
1958 return IRQ_HANDLED;
1959 }
1960
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1961 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1962 {
1963 unsigned int i, handled = 0;
1964
1965 for (i = 0; i < host->n_ports; i++) {
1966 struct ata_port *ap;
1967
1968 if (!(irq_masked & (1 << i)))
1969 continue;
1970
1971 ap = host->ports[i];
1972 if (ap) {
1973 ahci_port_intr(ap);
1974 } else {
1975 if (ata_ratelimit())
1976 dev_warn(host->dev,
1977 "interrupt on disabled port %u\n", i);
1978 }
1979
1980 handled = 1;
1981 }
1982
1983 return handled;
1984 }
1985 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1986
ahci_single_level_irq_intr(int irq,void * dev_instance)1987 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1988 {
1989 struct ata_host *host = dev_instance;
1990 struct ahci_host_priv *hpriv;
1991 unsigned int rc = 0;
1992 void __iomem *mmio;
1993 u32 irq_stat, irq_masked;
1994
1995 hpriv = host->private_data;
1996 mmio = hpriv->mmio;
1997
1998 /* sigh. 0xffffffff is a valid return from h/w */
1999 irq_stat = readl(mmio + HOST_IRQ_STAT);
2000 if (!irq_stat)
2001 return IRQ_NONE;
2002
2003 irq_masked = irq_stat & hpriv->port_map;
2004
2005 spin_lock(&host->lock);
2006
2007 rc = ahci_handle_port_intr(host, irq_masked);
2008
2009 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2010 * it should be cleared after all the port events are cleared;
2011 * otherwise, it will raise a spurious interrupt after each
2012 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2013 * information.
2014 *
2015 * Also, use the unmasked value to clear interrupt as spurious
2016 * pending event on a dummy port might cause screaming IRQ.
2017 */
2018 writel(irq_stat, mmio + HOST_IRQ_STAT);
2019
2020 spin_unlock(&host->lock);
2021
2022 return IRQ_RETVAL(rc);
2023 }
2024
ahci_qc_issue(struct ata_queued_cmd * qc)2025 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2026 {
2027 struct ata_port *ap = qc->ap;
2028 void __iomem *port_mmio = ahci_port_base(ap);
2029 struct ahci_port_priv *pp = ap->private_data;
2030
2031 /* Keep track of the currently active link. It will be used
2032 * in completion path to determine whether NCQ phase is in
2033 * progress.
2034 */
2035 pp->active_link = qc->dev->link;
2036
2037 if (ata_is_ncq(qc->tf.protocol))
2038 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2039
2040 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2041 u32 fbs = readl(port_mmio + PORT_FBS);
2042 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2043 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2044 writel(fbs, port_mmio + PORT_FBS);
2045 pp->fbs_last_dev = qc->dev->link->pmp;
2046 }
2047
2048 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2049
2050 ahci_sw_activity(qc->dev->link);
2051
2052 return 0;
2053 }
2054 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2055
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2056 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2057 {
2058 struct ahci_port_priv *pp = qc->ap->private_data;
2059 u8 *rx_fis = pp->rx_fis;
2060
2061 if (pp->fbs_enabled)
2062 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2063
2064 /*
2065 * After a successful execution of an ATA PIO data-in command,
2066 * the device doesn't send D2H Reg FIS to update the TF and
2067 * the host should take TF and E_Status from the preceding PIO
2068 * Setup FIS.
2069 */
2070 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2071 !(qc->flags & ATA_QCFLAG_FAILED)) {
2072 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2073 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
2074 } else
2075 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2076
2077 return true;
2078 }
2079
ahci_freeze(struct ata_port * ap)2080 static void ahci_freeze(struct ata_port *ap)
2081 {
2082 void __iomem *port_mmio = ahci_port_base(ap);
2083
2084 /* turn IRQ off */
2085 writel(0, port_mmio + PORT_IRQ_MASK);
2086 }
2087
ahci_thaw(struct ata_port * ap)2088 static void ahci_thaw(struct ata_port *ap)
2089 {
2090 struct ahci_host_priv *hpriv = ap->host->private_data;
2091 void __iomem *mmio = hpriv->mmio;
2092 void __iomem *port_mmio = ahci_port_base(ap);
2093 u32 tmp;
2094 struct ahci_port_priv *pp = ap->private_data;
2095
2096 /* clear IRQ */
2097 tmp = readl(port_mmio + PORT_IRQ_STAT);
2098 writel(tmp, port_mmio + PORT_IRQ_STAT);
2099 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2100
2101 /* turn IRQ back on */
2102 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2103 }
2104
ahci_error_handler(struct ata_port * ap)2105 void ahci_error_handler(struct ata_port *ap)
2106 {
2107 struct ahci_host_priv *hpriv = ap->host->private_data;
2108
2109 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2110 /* restart engine */
2111 hpriv->stop_engine(ap);
2112 hpriv->start_engine(ap);
2113 }
2114
2115 sata_pmp_error_handler(ap);
2116
2117 if (!ata_dev_enabled(ap->link.device))
2118 hpriv->stop_engine(ap);
2119 }
2120 EXPORT_SYMBOL_GPL(ahci_error_handler);
2121
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2122 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2123 {
2124 struct ata_port *ap = qc->ap;
2125
2126 /* make DMA engine forget about the failed command */
2127 if (qc->flags & ATA_QCFLAG_FAILED)
2128 ahci_kick_engine(ap);
2129 }
2130
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2131 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2132 {
2133 struct ahci_host_priv *hpriv = ap->host->private_data;
2134 void __iomem *port_mmio = ahci_port_base(ap);
2135 struct ata_device *dev = ap->link.device;
2136 u32 devslp, dm, dito, mdat, deto, dito_conf;
2137 int rc;
2138 unsigned int err_mask;
2139
2140 devslp = readl(port_mmio + PORT_DEVSLP);
2141 if (!(devslp & PORT_DEVSLP_DSP)) {
2142 dev_info(ap->host->dev, "port does not support device sleep\n");
2143 return;
2144 }
2145
2146 /* disable device sleep */
2147 if (!sleep) {
2148 if (devslp & PORT_DEVSLP_ADSE) {
2149 writel(devslp & ~PORT_DEVSLP_ADSE,
2150 port_mmio + PORT_DEVSLP);
2151 err_mask = ata_dev_set_feature(dev,
2152 SETFEATURES_SATA_DISABLE,
2153 SATA_DEVSLP);
2154 if (err_mask && err_mask != AC_ERR_DEV)
2155 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2156 }
2157 return;
2158 }
2159
2160 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2161 dito = devslp_idle_timeout / (dm + 1);
2162 if (dito > 0x3ff)
2163 dito = 0x3ff;
2164
2165 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2166
2167 /* device sleep was already enabled and same dito */
2168 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2169 return;
2170
2171 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2172 rc = hpriv->stop_engine(ap);
2173 if (rc)
2174 return;
2175
2176 /* Use the nominal value 10 ms if the read MDAT is zero,
2177 * the nominal value of DETO is 20 ms.
2178 */
2179 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2180 ATA_LOG_DEVSLP_VALID_MASK) {
2181 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2182 ATA_LOG_DEVSLP_MDAT_MASK;
2183 if (!mdat)
2184 mdat = 10;
2185 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2186 if (!deto)
2187 deto = 20;
2188 } else {
2189 mdat = 10;
2190 deto = 20;
2191 }
2192
2193 /* Make dito, mdat, deto bits to 0s */
2194 devslp &= ~GENMASK_ULL(24, 2);
2195 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2196 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2197 (deto << PORT_DEVSLP_DETO_OFFSET) |
2198 PORT_DEVSLP_ADSE);
2199 writel(devslp, port_mmio + PORT_DEVSLP);
2200
2201 hpriv->start_engine(ap);
2202
2203 /* enable device sleep feature for the drive */
2204 err_mask = ata_dev_set_feature(dev,
2205 SETFEATURES_SATA_ENABLE,
2206 SATA_DEVSLP);
2207 if (err_mask && err_mask != AC_ERR_DEV)
2208 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2209 }
2210
ahci_enable_fbs(struct ata_port * ap)2211 static void ahci_enable_fbs(struct ata_port *ap)
2212 {
2213 struct ahci_host_priv *hpriv = ap->host->private_data;
2214 struct ahci_port_priv *pp = ap->private_data;
2215 void __iomem *port_mmio = ahci_port_base(ap);
2216 u32 fbs;
2217 int rc;
2218
2219 if (!pp->fbs_supported)
2220 return;
2221
2222 fbs = readl(port_mmio + PORT_FBS);
2223 if (fbs & PORT_FBS_EN) {
2224 pp->fbs_enabled = true;
2225 pp->fbs_last_dev = -1; /* initialization */
2226 return;
2227 }
2228
2229 rc = hpriv->stop_engine(ap);
2230 if (rc)
2231 return;
2232
2233 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2234 fbs = readl(port_mmio + PORT_FBS);
2235 if (fbs & PORT_FBS_EN) {
2236 dev_info(ap->host->dev, "FBS is enabled\n");
2237 pp->fbs_enabled = true;
2238 pp->fbs_last_dev = -1; /* initialization */
2239 } else
2240 dev_err(ap->host->dev, "Failed to enable FBS\n");
2241
2242 hpriv->start_engine(ap);
2243 }
2244
ahci_disable_fbs(struct ata_port * ap)2245 static void ahci_disable_fbs(struct ata_port *ap)
2246 {
2247 struct ahci_host_priv *hpriv = ap->host->private_data;
2248 struct ahci_port_priv *pp = ap->private_data;
2249 void __iomem *port_mmio = ahci_port_base(ap);
2250 u32 fbs;
2251 int rc;
2252
2253 if (!pp->fbs_supported)
2254 return;
2255
2256 fbs = readl(port_mmio + PORT_FBS);
2257 if ((fbs & PORT_FBS_EN) == 0) {
2258 pp->fbs_enabled = false;
2259 return;
2260 }
2261
2262 rc = hpriv->stop_engine(ap);
2263 if (rc)
2264 return;
2265
2266 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2267 fbs = readl(port_mmio + PORT_FBS);
2268 if (fbs & PORT_FBS_EN)
2269 dev_err(ap->host->dev, "Failed to disable FBS\n");
2270 else {
2271 dev_info(ap->host->dev, "FBS is disabled\n");
2272 pp->fbs_enabled = false;
2273 }
2274
2275 hpriv->start_engine(ap);
2276 }
2277
ahci_pmp_attach(struct ata_port * ap)2278 static void ahci_pmp_attach(struct ata_port *ap)
2279 {
2280 void __iomem *port_mmio = ahci_port_base(ap);
2281 struct ahci_port_priv *pp = ap->private_data;
2282 u32 cmd;
2283
2284 cmd = readl(port_mmio + PORT_CMD);
2285 cmd |= PORT_CMD_PMP;
2286 writel(cmd, port_mmio + PORT_CMD);
2287
2288 ahci_enable_fbs(ap);
2289
2290 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2291
2292 /*
2293 * We must not change the port interrupt mask register if the
2294 * port is marked frozen, the value in pp->intr_mask will be
2295 * restored later when the port is thawed.
2296 *
2297 * Note that during initialization, the port is marked as
2298 * frozen since the irq handler is not yet registered.
2299 */
2300 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2301 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2302 }
2303
ahci_pmp_detach(struct ata_port * ap)2304 static void ahci_pmp_detach(struct ata_port *ap)
2305 {
2306 void __iomem *port_mmio = ahci_port_base(ap);
2307 struct ahci_port_priv *pp = ap->private_data;
2308 u32 cmd;
2309
2310 ahci_disable_fbs(ap);
2311
2312 cmd = readl(port_mmio + PORT_CMD);
2313 cmd &= ~PORT_CMD_PMP;
2314 writel(cmd, port_mmio + PORT_CMD);
2315
2316 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2317
2318 /* see comment above in ahci_pmp_attach() */
2319 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2320 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2321 }
2322
ahci_port_resume(struct ata_port * ap)2323 int ahci_port_resume(struct ata_port *ap)
2324 {
2325 ahci_rpm_get_port(ap);
2326
2327 ahci_power_up(ap);
2328 ahci_start_port(ap);
2329
2330 if (sata_pmp_attached(ap))
2331 ahci_pmp_attach(ap);
2332 else
2333 ahci_pmp_detach(ap);
2334
2335 return 0;
2336 }
2337 EXPORT_SYMBOL_GPL(ahci_port_resume);
2338
2339 #ifdef CONFIG_PM
ahci_handle_s2idle(struct ata_port * ap)2340 static void ahci_handle_s2idle(struct ata_port *ap)
2341 {
2342 void __iomem *port_mmio = ahci_port_base(ap);
2343 u32 devslp;
2344
2345 if (pm_suspend_via_firmware())
2346 return;
2347 devslp = readl(port_mmio + PORT_DEVSLP);
2348 if ((devslp & PORT_DEVSLP_ADSE))
2349 ata_msleep(ap, devslp_idle_timeout);
2350 }
2351
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2352 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2353 {
2354 const char *emsg = NULL;
2355 int rc;
2356
2357 rc = ahci_deinit_port(ap, &emsg);
2358 if (rc == 0)
2359 ahci_power_down(ap);
2360 else {
2361 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2362 ata_port_freeze(ap);
2363 }
2364
2365 if (acpi_storage_d3(ap->host->dev))
2366 ahci_handle_s2idle(ap);
2367
2368 ahci_rpm_put_port(ap);
2369 return rc;
2370 }
2371 #endif
2372
ahci_port_start(struct ata_port * ap)2373 static int ahci_port_start(struct ata_port *ap)
2374 {
2375 struct ahci_host_priv *hpriv = ap->host->private_data;
2376 struct device *dev = ap->host->dev;
2377 struct ahci_port_priv *pp;
2378 void *mem;
2379 dma_addr_t mem_dma;
2380 size_t dma_sz, rx_fis_sz;
2381
2382 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2383 if (!pp)
2384 return -ENOMEM;
2385
2386 if (ap->host->n_ports > 1) {
2387 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2388 if (!pp->irq_desc) {
2389 devm_kfree(dev, pp);
2390 return -ENOMEM;
2391 }
2392 snprintf(pp->irq_desc, 8,
2393 "%s%d", dev_driver_string(dev), ap->port_no);
2394 }
2395
2396 /* check FBS capability */
2397 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2398 void __iomem *port_mmio = ahci_port_base(ap);
2399 u32 cmd = readl(port_mmio + PORT_CMD);
2400 if (cmd & PORT_CMD_FBSCP)
2401 pp->fbs_supported = true;
2402 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2403 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2404 ap->port_no);
2405 pp->fbs_supported = true;
2406 } else
2407 dev_warn(dev, "port %d is not capable of FBS\n",
2408 ap->port_no);
2409 }
2410
2411 if (pp->fbs_supported) {
2412 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2413 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2414 } else {
2415 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2416 rx_fis_sz = AHCI_RX_FIS_SZ;
2417 }
2418
2419 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2420 if (!mem)
2421 return -ENOMEM;
2422
2423 /*
2424 * First item in chunk of DMA memory: 32-slot command table,
2425 * 32 bytes each in size
2426 */
2427 pp->cmd_slot = mem;
2428 pp->cmd_slot_dma = mem_dma;
2429
2430 mem += AHCI_CMD_SLOT_SZ;
2431 mem_dma += AHCI_CMD_SLOT_SZ;
2432
2433 /*
2434 * Second item: Received-FIS area
2435 */
2436 pp->rx_fis = mem;
2437 pp->rx_fis_dma = mem_dma;
2438
2439 mem += rx_fis_sz;
2440 mem_dma += rx_fis_sz;
2441
2442 /*
2443 * Third item: data area for storing a single command
2444 * and its scatter-gather table
2445 */
2446 pp->cmd_tbl = mem;
2447 pp->cmd_tbl_dma = mem_dma;
2448
2449 /*
2450 * Save off initial list of interrupts to be enabled.
2451 * This could be changed later
2452 */
2453 pp->intr_mask = DEF_PORT_IRQ;
2454
2455 /*
2456 * Switch to per-port locking in case each port has its own MSI vector.
2457 */
2458 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2459 spin_lock_init(&pp->lock);
2460 ap->lock = &pp->lock;
2461 }
2462
2463 ap->private_data = pp;
2464
2465 /* engage engines, captain */
2466 return ahci_port_resume(ap);
2467 }
2468
ahci_port_stop(struct ata_port * ap)2469 static void ahci_port_stop(struct ata_port *ap)
2470 {
2471 const char *emsg = NULL;
2472 struct ahci_host_priv *hpriv = ap->host->private_data;
2473 void __iomem *host_mmio = hpriv->mmio;
2474 int rc;
2475
2476 /* de-initialize port */
2477 rc = ahci_deinit_port(ap, &emsg);
2478 if (rc)
2479 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2480
2481 /*
2482 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2483 * re-enabling INTx.
2484 */
2485 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2486
2487 ahci_rpm_put_port(ap);
2488 }
2489
ahci_print_info(struct ata_host * host,const char * scc_s)2490 void ahci_print_info(struct ata_host *host, const char *scc_s)
2491 {
2492 struct ahci_host_priv *hpriv = host->private_data;
2493 u32 vers, cap, cap2, impl, speed;
2494 const char *speed_s;
2495
2496 vers = hpriv->version;
2497 cap = hpriv->cap;
2498 cap2 = hpriv->cap2;
2499 impl = hpriv->port_map;
2500
2501 speed = (cap >> 20) & 0xf;
2502 if (speed == 1)
2503 speed_s = "1.5";
2504 else if (speed == 2)
2505 speed_s = "3";
2506 else if (speed == 3)
2507 speed_s = "6";
2508 else
2509 speed_s = "?";
2510
2511 dev_info(host->dev,
2512 "AHCI %02x%02x.%02x%02x "
2513 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2514 ,
2515
2516 (vers >> 24) & 0xff,
2517 (vers >> 16) & 0xff,
2518 (vers >> 8) & 0xff,
2519 vers & 0xff,
2520
2521 ((cap >> 8) & 0x1f) + 1,
2522 (cap & 0x1f) + 1,
2523 speed_s,
2524 impl,
2525 scc_s);
2526
2527 dev_info(host->dev,
2528 "flags: "
2529 "%s%s%s%s%s%s%s"
2530 "%s%s%s%s%s%s%s"
2531 "%s%s%s%s%s%s%s"
2532 "%s%s\n"
2533 ,
2534
2535 cap & HOST_CAP_64 ? "64bit " : "",
2536 cap & HOST_CAP_NCQ ? "ncq " : "",
2537 cap & HOST_CAP_SNTF ? "sntf " : "",
2538 cap & HOST_CAP_MPS ? "ilck " : "",
2539 cap & HOST_CAP_SSS ? "stag " : "",
2540 cap & HOST_CAP_ALPM ? "pm " : "",
2541 cap & HOST_CAP_LED ? "led " : "",
2542 cap & HOST_CAP_CLO ? "clo " : "",
2543 cap & HOST_CAP_ONLY ? "only " : "",
2544 cap & HOST_CAP_PMP ? "pmp " : "",
2545 cap & HOST_CAP_FBS ? "fbs " : "",
2546 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2547 cap & HOST_CAP_SSC ? "slum " : "",
2548 cap & HOST_CAP_PART ? "part " : "",
2549 cap & HOST_CAP_CCC ? "ccc " : "",
2550 cap & HOST_CAP_EMS ? "ems " : "",
2551 cap & HOST_CAP_SXS ? "sxs " : "",
2552 cap2 & HOST_CAP2_DESO ? "deso " : "",
2553 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2554 cap2 & HOST_CAP2_SDS ? "sds " : "",
2555 cap2 & HOST_CAP2_APST ? "apst " : "",
2556 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2557 cap2 & HOST_CAP2_BOH ? "boh " : ""
2558 );
2559 }
2560 EXPORT_SYMBOL_GPL(ahci_print_info);
2561
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2562 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2563 struct ata_port_info *pi)
2564 {
2565 u8 messages;
2566 void __iomem *mmio = hpriv->mmio;
2567 u32 em_loc = readl(mmio + HOST_EM_LOC);
2568 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2569
2570 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2571 return;
2572
2573 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2574
2575 if (messages) {
2576 /* store em_loc */
2577 hpriv->em_loc = ((em_loc >> 16) * 4);
2578 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2579 hpriv->em_msg_type = messages;
2580 pi->flags |= ATA_FLAG_EM;
2581 if (!(em_ctl & EM_CTL_ALHD))
2582 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2583 }
2584 }
2585 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2586
ahci_host_activate_multi_irqs(struct ata_host * host,struct scsi_host_template * sht)2587 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2588 struct scsi_host_template *sht)
2589 {
2590 struct ahci_host_priv *hpriv = host->private_data;
2591 int i, rc;
2592
2593 rc = ata_host_start(host);
2594 if (rc)
2595 return rc;
2596 /*
2597 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2598 * allocated. That is one MSI per port, starting from @irq.
2599 */
2600 for (i = 0; i < host->n_ports; i++) {
2601 struct ahci_port_priv *pp = host->ports[i]->private_data;
2602 int irq = hpriv->get_irq_vector(host, i);
2603
2604 /* Do not receive interrupts sent by dummy ports */
2605 if (!pp) {
2606 disable_irq(irq);
2607 continue;
2608 }
2609
2610 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2611 0, pp->irq_desc, host->ports[i]);
2612
2613 if (rc)
2614 return rc;
2615 ata_port_desc(host->ports[i], "irq %d", irq);
2616 }
2617
2618 return ata_host_register(host, sht);
2619 }
2620
2621 /**
2622 * ahci_host_activate - start AHCI host, request IRQs and register it
2623 * @host: target ATA host
2624 * @sht: scsi_host_template to use when registering the host
2625 *
2626 * LOCKING:
2627 * Inherited from calling layer (may sleep).
2628 *
2629 * RETURNS:
2630 * 0 on success, -errno otherwise.
2631 */
ahci_host_activate(struct ata_host * host,struct scsi_host_template * sht)2632 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2633 {
2634 struct ahci_host_priv *hpriv = host->private_data;
2635 int irq = hpriv->irq;
2636 int rc;
2637
2638 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2639 if (hpriv->irq_handler &&
2640 hpriv->irq_handler != ahci_single_level_irq_intr)
2641 dev_warn(host->dev,
2642 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2643 if (!hpriv->get_irq_vector) {
2644 dev_err(host->dev,
2645 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2646 return -EIO;
2647 }
2648
2649 rc = ahci_host_activate_multi_irqs(host, sht);
2650 } else {
2651 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2652 IRQF_SHARED, sht);
2653 }
2654
2655
2656 return rc;
2657 }
2658 EXPORT_SYMBOL_GPL(ahci_host_activate);
2659
2660 MODULE_AUTHOR("Jeff Garzik");
2661 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2662 MODULE_LICENSE("GPL");
2663