1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copied from arch/arm64/include/asm/hwcap.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8 #ifndef _ASM_RISCV_HWCAP_H
9 #define _ASM_RISCV_HWCAP_H
10
11 #include <asm/errno.h>
12 #include <linux/bits.h>
13 #include <uapi/asm/hwcap.h>
14
15 #ifndef __ASSEMBLY__
16 #include <linux/jump_label.h>
17 /*
18 * This yields a mask that user programs can use to figure out what
19 * instruction set this cpu supports.
20 */
21 #define ELF_HWCAP (elf_hwcap)
22
23 enum {
24 CAP_HWCAP = 1,
25 };
26
27 extern unsigned long elf_hwcap;
28
29 #define RISCV_ISA_EXT_a ('a' - 'a')
30 #define RISCV_ISA_EXT_c ('c' - 'a')
31 #define RISCV_ISA_EXT_d ('d' - 'a')
32 #define RISCV_ISA_EXT_f ('f' - 'a')
33 #define RISCV_ISA_EXT_h ('h' - 'a')
34 #define RISCV_ISA_EXT_i ('i' - 'a')
35 #define RISCV_ISA_EXT_m ('m' - 'a')
36 #define RISCV_ISA_EXT_s ('s' - 'a')
37 #define RISCV_ISA_EXT_u ('u' - 'a')
38
39 /*
40 * Increse this to higher value as kernel support more ISA extensions.
41 */
42 #define RISCV_ISA_EXT_MAX 64
43 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
44
45 /* The base ID for multi-letter ISA extensions */
46 #define RISCV_ISA_EXT_BASE 26
47
48 /*
49 * This enum represent the logical ID for each multi-letter RISC-V ISA extension.
50 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
51 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
52 * extensions while all the multi-letter extensions should define the next
53 * available logical extension id.
54 */
55 enum riscv_isa_ext_id {
56 RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
57 RISCV_ISA_EXT_SVPBMT,
58 RISCV_ISA_EXT_ZICBOM,
59 RISCV_ISA_EXT_ZIHINTPAUSE,
60 RISCV_ISA_EXT_SSTC,
61 RISCV_ISA_EXT_SVINVAL,
62 RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
63 };
64
65 /*
66 * This enum represents the logical ID for each RISC-V ISA extension static
67 * keys. We can use static key to optimize code path if some ISA extensions
68 * are available.
69 */
70 enum riscv_isa_ext_key {
71 RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
72 RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
73 RISCV_ISA_EXT_KEY_SVINVAL,
74 RISCV_ISA_EXT_KEY_MAX,
75 };
76
77 struct riscv_isa_ext_data {
78 /* Name of the extension displayed to userspace via /proc/cpuinfo */
79 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
80 /* The logical ISA extension ID */
81 unsigned int isa_ext_id;
82 };
83
84 extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
85
riscv_isa_ext2key(int num)86 static __always_inline int riscv_isa_ext2key(int num)
87 {
88 switch (num) {
89 case RISCV_ISA_EXT_f:
90 return RISCV_ISA_EXT_KEY_FPU;
91 case RISCV_ISA_EXT_d:
92 return RISCV_ISA_EXT_KEY_FPU;
93 case RISCV_ISA_EXT_ZIHINTPAUSE:
94 return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
95 case RISCV_ISA_EXT_SVINVAL:
96 return RISCV_ISA_EXT_KEY_SVINVAL;
97 default:
98 return -EINVAL;
99 }
100 }
101
102 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
103
104 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
105
106 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
107 #define riscv_isa_extension_available(isa_bitmap, ext) \
108 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
109
110 #endif
111
112 #endif /* _ASM_RISCV_HWCAP_H */
113