1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * This control block defines the PACA which defines the processor
4  * specific data for each logical processor on the system.
5  * There are some pointers defined that are utilized by PLIC.
6  *
7  * C 2001 PPC 64 Team, IBM Corp
8  */
9 #ifndef _ASM_POWERPC_PACA_H
10 #define _ASM_POWERPC_PACA_H
11 #ifdef __KERNEL__
12 
13 #ifdef CONFIG_PPC64
14 
15 #include <linux/cache.h>
16 #include <linux/string.h>
17 #include <asm/types.h>
18 #include <asm/lppaca.h>
19 #include <asm/mmu.h>
20 #include <asm/page.h>
21 #ifdef CONFIG_PPC_BOOK3E_64
22 #include <asm/exception-64e.h>
23 #else
24 #include <asm/exception-64s.h>
25 #endif
26 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
27 #include <asm/kvm_book3s_asm.h>
28 #endif
29 #include <asm/accounting.h>
30 #include <asm/hmi.h>
31 #include <asm/cpuidle.h>
32 #include <asm/atomic.h>
33 #include <asm/mce.h>
34 
35 #include <asm-generic/mmiowb_types.h>
36 
37 register struct paca_struct *local_paca asm("r13");
38 
39 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
40 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
41 /*
42  * Add standard checks that preemption cannot occur when using get_paca():
43  * otherwise the paca_struct it points to may be the wrong one just after.
44  */
45 #define get_paca()	((void) debug_smp_processor_id(), local_paca)
46 #else
47 #define get_paca()	local_paca
48 #endif
49 
50 #ifdef CONFIG_PPC_PSERIES
51 #define get_lppaca()	(get_paca()->lppaca_ptr)
52 #endif
53 
54 #define get_slb_shadow()	(get_paca()->slb_shadow_ptr)
55 
56 struct task_struct;
57 struct rtas_args;
58 
59 /*
60  * Defines the layout of the paca.
61  *
62  * This structure is not directly accessed by firmware or the service
63  * processor.
64  */
65 struct paca_struct {
66 #ifdef CONFIG_PPC_PSERIES
67 	/*
68 	 * Because hw_cpu_id, unlike other paca fields, is accessed
69 	 * routinely from other CPUs (from the IRQ code), we stick to
70 	 * read-only (after boot) fields in the first cacheline to
71 	 * avoid cacheline bouncing.
72 	 */
73 
74 	struct lppaca *lppaca_ptr;	/* Pointer to LpPaca for PLIC */
75 #endif /* CONFIG_PPC_PSERIES */
76 
77 	/*
78 	 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
79 	 * load lock_token and paca_index with a single lwz
80 	 * instruction.  They must travel together and be properly
81 	 * aligned.
82 	 */
83 #ifdef __BIG_ENDIAN__
84 	u16 lock_token;			/* Constant 0x8000, used in locks */
85 	u16 paca_index;			/* Logical processor number */
86 #else
87 	u16 paca_index;			/* Logical processor number */
88 	u16 lock_token;			/* Constant 0x8000, used in locks */
89 #endif
90 
91 	u64 kernel_toc;			/* Kernel TOC address */
92 	u64 kernelbase;			/* Base address of kernel */
93 	u64 kernel_msr;			/* MSR while running in kernel */
94 	void *emergency_sp;		/* pointer to emergency stack */
95 	u64 data_offset;		/* per cpu data offset */
96 	s16 hw_cpu_id;			/* Physical processor number */
97 	u8 cpu_start;			/* At startup, processor spins until */
98 					/* this becomes non-zero. */
99 	u8 kexec_state;		/* set when kexec down has irqs off */
100 #ifdef CONFIG_PPC_BOOK3S_64
101 #ifdef CONFIG_PPC_64S_HASH_MMU
102 	struct slb_shadow *slb_shadow_ptr;
103 #endif
104 	struct dtl_entry *dispatch_log;
105 	struct dtl_entry *dispatch_log_end;
106 #endif
107 	u64 dscr_default;		/* per-CPU default DSCR */
108 
109 #ifdef CONFIG_PPC_BOOK3S_64
110 	/*
111 	 * Now, starting in cacheline 2, the exception save areas
112 	 */
113 	/* used for most interrupts/exceptions */
114 	u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
115 
116 #ifdef CONFIG_PPC_64S_HASH_MMU
117 	/* SLB related definitions */
118 	u16 vmalloc_sllp;
119 	u8 slb_cache_ptr;
120 	u8 stab_rr;			/* stab/slb round-robin counter */
121 #ifdef CONFIG_DEBUG_VM
122 	u8 in_kernel_slb_handler;
123 #endif
124 	u32 slb_used_bitmap;		/* Bitmaps for first 32 SLB entries. */
125 	u32 slb_kern_bitmap;
126 	u32 slb_cache[SLB_CACHE_ENTRIES];
127 #endif
128 #endif /* CONFIG_PPC_BOOK3S_64 */
129 
130 #ifdef CONFIG_PPC_BOOK3E_64
131 	u64 exgen[8] __aligned(0x40);
132 	/* Keep pgd in the same cacheline as the start of extlb */
133 	pgd_t *pgd __aligned(0x40); /* Current PGD */
134 	pgd_t *kernel_pgd;		/* Kernel PGD */
135 
136 	/* Shared by all threads of a core -- points to tcd of first thread */
137 	struct tlb_core_data *tcd_ptr;
138 
139 	/*
140 	 * We can have up to 3 levels of reentrancy in the TLB miss handler,
141 	 * in each of four exception levels (normal, crit, mcheck, debug).
142 	 */
143 	u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
144 	u64 exmc[8];		/* used for machine checks */
145 	u64 excrit[8];		/* used for crit interrupts */
146 	u64 exdbg[8];		/* used for debug interrupts */
147 
148 	/* Kernel stack pointers for use by special exceptions */
149 	void *mc_kstack;
150 	void *crit_kstack;
151 	void *dbg_kstack;
152 
153 	struct tlb_core_data tcd;
154 #endif /* CONFIG_PPC_BOOK3E_64 */
155 
156 #ifdef CONFIG_PPC_64S_HASH_MMU
157 	unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
158 	unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
159 #endif
160 
161 	/*
162 	 * then miscellaneous read-write fields
163 	 */
164 	struct task_struct *__current;	/* Pointer to current */
165 	u64 kstack;			/* Saved Kernel stack addr */
166 	u64 saved_r1;			/* r1 save for RTAS calls or PM or EE=0 */
167 	u64 saved_msr;			/* MSR saved here by enter_rtas */
168 #ifdef CONFIG_PPC64
169 	u64 exit_save_r1;		/* Syscall/interrupt R1 save */
170 #endif
171 #ifdef CONFIG_PPC_BOOK3E_64
172 	u16 trap_save;			/* Used when bad stack is encountered */
173 #endif
174 #ifdef CONFIG_PPC_BOOK3S_64
175 	u8 hsrr_valid;			/* HSRRs set for HRFID */
176 	u8 srr_valid;			/* SRRs set for RFID */
177 #endif
178 	u8 irq_soft_mask;		/* mask for irq soft masking */
179 	u8 irq_happened;		/* irq happened while soft-disabled */
180 	u8 irq_work_pending;		/* IRQ_WORK interrupt while soft-disable */
181 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
182 	u8 pmcregs_in_use;		/* pseries puts this in lppaca */
183 #endif
184 	u64 sprg_vdso;			/* Saved user-visible sprg */
185 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
186 	u64 tm_scratch;                 /* TM scratch area for reclaim */
187 #endif
188 
189 #ifdef CONFIG_PPC_POWERNV
190 	/* PowerNV idle fields */
191 	/* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
192 	unsigned long idle_state;
193 	union {
194 		/* P7/P8 specific fields */
195 		struct {
196 			/* PNV_THREAD_RUNNING/NAP/SLEEP	*/
197 			u8 thread_idle_state;
198 			/* Mask to denote subcore sibling threads */
199 			u8 subcore_sibling_mask;
200 		};
201 
202 		/* P9 specific fields */
203 		struct {
204 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
205 			/* The PSSCR value that the kernel requested before going to stop */
206 			u64 requested_psscr;
207 			/* Flag to request this thread not to stop */
208 			atomic_t dont_stop;
209 #endif
210 		};
211 	};
212 #endif
213 
214 #ifdef CONFIG_PPC_BOOK3S_64
215 	/* Non-maskable exceptions that are not performance critical */
216 	u64 exnmi[EX_SIZE];	/* used for system reset (nmi) */
217 	u64 exmc[EX_SIZE];	/* used for machine checks */
218 #endif
219 #ifdef CONFIG_PPC_BOOK3S_64
220 	/* Exclusive stacks for system reset and machine check exception. */
221 	void *nmi_emergency_sp;
222 	void *mc_emergency_sp;
223 
224 	u16 in_nmi;			/* In nmi handler */
225 
226 	/*
227 	 * Flag to check whether we are in machine check early handler
228 	 * and already using emergency stack.
229 	 */
230 	u16 in_mce;
231 	u8 hmi_event_available;		/* HMI event is available */
232 	u8 hmi_p9_special_emu;		/* HMI P9 special emulation */
233 	u32 hmi_irqs;			/* HMI irq stat */
234 #endif
235 	u8 ftrace_enabled;		/* Hard disable ftrace */
236 
237 	/* Stuff for accurate time accounting */
238 	struct cpu_accounting_data accounting;
239 	u64 dtl_ridx;			/* read index in dispatch log */
240 	struct dtl_entry *dtl_curr;	/* pointer corresponding to dtl_ridx */
241 
242 #ifdef CONFIG_KVM_BOOK3S_HANDLER
243 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
244 	/* We use this to store guest state in */
245 	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
246 #endif
247 	struct kvmppc_host_state kvm_hstate;
248 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
249 	/*
250 	 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
251 	 * more details
252 	 */
253 	struct sibling_subcore_state *sibling_subcore_state;
254 #endif
255 #endif
256 #ifdef CONFIG_PPC_BOOK3S_64
257 	/*
258 	 * rfi fallback flush must be in its own cacheline to prevent
259 	 * other paca data leaking into the L1d
260 	 */
261 	u64 exrfi[EX_SIZE] __aligned(0x80);
262 	void *rfi_flush_fallback_area;
263 	u64 l1d_flush_size;
264 #endif
265 #ifdef CONFIG_PPC_PSERIES
266 	u8 *mce_data_buf;		/* buffer to hold per cpu rtas errlog */
267 #endif /* CONFIG_PPC_PSERIES */
268 
269 #ifdef CONFIG_PPC_BOOK3S_64
270 #ifdef CONFIG_PPC_64S_HASH_MMU
271 	/* Capture SLB related old contents in MCE handler. */
272 	struct slb_entry *mce_faulty_slbs;
273 	u16 slb_save_cache_ptr;
274 #endif
275 #endif /* CONFIG_PPC_BOOK3S_64 */
276 #ifdef CONFIG_STACKPROTECTOR
277 	unsigned long canary;
278 #endif
279 #ifdef CONFIG_MMIOWB
280 	struct mmiowb_state mmiowb_state;
281 #endif
282 #ifdef CONFIG_PPC_BOOK3S_64
283 	struct mce_info *mce_info;
284 	u8 mce_pending_irq_work;
285 #endif /* CONFIG_PPC_BOOK3S_64 */
286 } ____cacheline_aligned;
287 
288 extern void copy_mm_to_paca(struct mm_struct *mm);
289 extern struct paca_struct **paca_ptrs;
290 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
291 extern void setup_paca(struct paca_struct *new_paca);
292 extern void allocate_paca_ptrs(void);
293 extern void allocate_paca(int cpu);
294 extern void free_unused_pacas(void);
295 
296 #else /* CONFIG_PPC64 */
297 
allocate_paca_ptrs(void)298 static inline void allocate_paca_ptrs(void) { }
allocate_paca(int cpu)299 static inline void allocate_paca(int cpu) { }
free_unused_pacas(void)300 static inline void free_unused_pacas(void) { }
301 
302 #endif /* CONFIG_PPC64 */
303 
304 #endif /* __KERNEL__ */
305 #endif /* _ASM_POWERPC_PACA_H */
306