1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5 
6 #define ARCH_HAS_IOREMAP_WC
7 #ifdef CONFIG_PPC32
8 #define ARCH_HAS_IOREMAP_WT
9 #endif
10 
11 /*
12  */
13 
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG	0x60
17 #define FDC_BASE	0x3f0
18 
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22  * has legacy ISA devices ?
23  */
24 #define arch_has_dev_port()	(isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26 
27 #include <linux/device.h>
28 #include <linux/compiler.h>
29 #include <linux/mm.h>
30 #include <asm/page.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
35 #include <asm/mmu.h>
36 
37 #define SIO_CONFIG_RA	0x398
38 #define SIO_CONFIG_RD	0x399
39 
40 /* 32 bits uses slightly different variables for the various IO
41  * bases. Most of this file only uses _IO_BASE though which we
42  * define properly based on the platform
43  */
44 #ifndef CONFIG_PCI
45 #define _IO_BASE	0
46 #define _ISA_MEM_BASE	0
47 #define PCI_DRAM_OFFSET 0
48 #elif defined(CONFIG_PPC32)
49 #define _IO_BASE	isa_io_base
50 #define _ISA_MEM_BASE	isa_mem_base
51 #define PCI_DRAM_OFFSET	pci_dram_offset
52 #else
53 #define _IO_BASE	pci_io_base
54 #define _ISA_MEM_BASE	isa_mem_base
55 #define PCI_DRAM_OFFSET	0
56 #endif
57 
58 extern unsigned long isa_io_base;
59 extern unsigned long pci_io_base;
60 extern unsigned long pci_dram_offset;
61 
62 extern resource_size_t isa_mem_base;
63 
64 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
65  * is not set or addresses cannot be translated to MMIO. This is typically
66  * set when the platform supports "special" PIO accesses via a non memory
67  * mapped mechanism, and allows things like the early udbg UART code to
68  * function.
69  */
70 extern bool isa_io_special;
71 
72 #ifdef CONFIG_PPC32
73 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
74 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
75 #endif
76 #endif
77 
78 /*
79  *
80  * Low level MMIO accessors
81  *
82  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
83  * specific and thus shouldn't be used in generic code. The accessors
84  * provided here are:
85  *
86  *	in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
87  *	out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
88  *	_insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
89  *
90  * Those operate directly on a kernel virtual address. Note that the prototype
91  * for the out_* accessors has the arguments in opposite order from the usual
92  * linux PCI accessors. Unlike those, they take the address first and the value
93  * next.
94  *
95  * Note: I might drop the _ns suffix on the stream operations soon as it is
96  * simply normal for stream operations to not swap in the first place.
97  *
98  */
99 
100 #define DEF_MMIO_IN_X(name, size, insn)				\
101 static inline u##size name(const volatile u##size __iomem *addr)	\
102 {									\
103 	u##size ret;							\
104 	__asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"	\
105 		: "=r" (ret) : "Z" (*addr) : "memory");			\
106 	return ret;							\
107 }
108 
109 #define DEF_MMIO_OUT_X(name, size, insn)				\
110 static inline void name(volatile u##size __iomem *addr, u##size val)	\
111 {									\
112 	__asm__ __volatile__("sync;"#insn" %1,%y0"			\
113 		: "=Z" (*addr) : "r" (val) : "memory");			\
114 	mmiowb_set_pending();						\
115 }
116 
117 #define DEF_MMIO_IN_D(name, size, insn)				\
118 static inline u##size name(const volatile u##size __iomem *addr)	\
119 {									\
120 	u##size ret;							\
121 	__asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
122 		: "=r" (ret) : "m<>" (*addr) : "memory");	\
123 	return ret;							\
124 }
125 
126 #define DEF_MMIO_OUT_D(name, size, insn)				\
127 static inline void name(volatile u##size __iomem *addr, u##size val)	\
128 {									\
129 	__asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"			\
130 		: "=m<>" (*addr) : "r" (val) : "memory");	\
131 	mmiowb_set_pending();						\
132 }
133 
134 DEF_MMIO_IN_D(in_8,     8, lbz);
135 DEF_MMIO_OUT_D(out_8,   8, stb);
136 
137 #ifdef __BIG_ENDIAN__
138 DEF_MMIO_IN_D(in_be16, 16, lhz);
139 DEF_MMIO_IN_D(in_be32, 32, lwz);
140 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
141 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
142 
143 DEF_MMIO_OUT_D(out_be16, 16, sth);
144 DEF_MMIO_OUT_D(out_be32, 32, stw);
145 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
146 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
147 #else
148 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
149 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
150 DEF_MMIO_IN_D(in_le16, 16, lhz);
151 DEF_MMIO_IN_D(in_le32, 32, lwz);
152 
153 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
154 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
155 DEF_MMIO_OUT_D(out_le16, 16, sth);
156 DEF_MMIO_OUT_D(out_le32, 32, stw);
157 
158 #endif /* __BIG_ENDIAN */
159 
160 #ifdef __powerpc64__
161 
162 #ifdef __BIG_ENDIAN__
163 DEF_MMIO_OUT_D(out_be64, 64, std);
164 DEF_MMIO_IN_D(in_be64, 64, ld);
165 
166 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)167 static inline u64 in_le64(const volatile u64 __iomem *addr)
168 {
169 	return swab64(in_be64(addr));
170 }
171 
out_le64(volatile u64 __iomem * addr,u64 val)172 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
173 {
174 	out_be64(addr, swab64(val));
175 }
176 #else
177 DEF_MMIO_OUT_D(out_le64, 64, std);
178 DEF_MMIO_IN_D(in_le64, 64, ld);
179 
180 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)181 static inline u64 in_be64(const volatile u64 __iomem *addr)
182 {
183 	return swab64(in_le64(addr));
184 }
185 
out_be64(volatile u64 __iomem * addr,u64 val)186 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
187 {
188 	out_le64(addr, swab64(val));
189 }
190 
191 #endif
192 #endif /* __powerpc64__ */
193 
194 /*
195  * Low level IO stream instructions are defined out of line for now
196  */
197 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
198 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
199 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
200 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
201 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
202 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
203 
204 /* The _ns naming is historical and will be removed. For now, just #define
205  * the non _ns equivalent names
206  */
207 #define _insw	_insw_ns
208 #define _insl	_insl_ns
209 #define _outsw	_outsw_ns
210 #define _outsl	_outsl_ns
211 
212 
213 /*
214  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
215  */
216 
217 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
218 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
219 			   unsigned long n);
220 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
221 			 unsigned long n);
222 
223 /*
224  *
225  * PCI and standard ISA accessors
226  *
227  * Those are globally defined linux accessors for devices on PCI or ISA
228  * busses. They follow the Linux defined semantics. The current implementation
229  * for PowerPC is as close as possible to the x86 version of these, and thus
230  * provides fairly heavy weight barriers for the non-raw versions
231  *
232  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
233  * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
234  * own implementation of some or all of the accessors.
235  */
236 
237 /*
238  * Include the EEH definitions when EEH is enabled only so they don't get
239  * in the way when building for 32 bits
240  */
241 #ifdef CONFIG_EEH
242 #include <asm/eeh.h>
243 #endif
244 
245 /* Shortcut to the MMIO argument pointer */
246 #define PCI_IO_ADDR	volatile void __iomem *
247 
248 /* Indirect IO address tokens:
249  *
250  * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
251  * on all MMIOs. (Note that this is all 64 bits only for now)
252  *
253  * To help platforms who may need to differentiate MMIO addresses in
254  * their hooks, a bitfield is reserved for use by the platform near the
255  * top of MMIO addresses (not PIO, those have to cope the hard way).
256  *
257  * The highest address in the kernel virtual space are:
258  *
259  *  d0003fffffffffff	# with Hash MMU
260  *  c00fffffffffffff	# with Radix MMU
261  *
262  * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
263  * that can be used for the field.
264  *
265  * The direct IO mapping operations will then mask off those bits
266  * before doing the actual access, though that only happen when
267  * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
268  * mechanism
269  *
270  * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
271  * all PIO functions call through a hook.
272  */
273 
274 #ifdef CONFIG_PPC_INDIRECT_MMIO
275 #define PCI_IO_IND_TOKEN_SHIFT	52
276 #define PCI_IO_IND_TOKEN_MASK	(0xfful << PCI_IO_IND_TOKEN_SHIFT)
277 #define PCI_FIX_ADDR(addr)						\
278 	((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
279 #define PCI_GET_ADDR_TOKEN(addr)					\
280 	(((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> 		\
281 		PCI_IO_IND_TOKEN_SHIFT)
282 #define PCI_SET_ADDR_TOKEN(addr, token) 				\
283 do {									\
284 	unsigned long __a = (unsigned long)(addr);			\
285 	__a &= ~PCI_IO_IND_TOKEN_MASK;					\
286 	__a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;	\
287 	(addr) = (void __iomem *)__a;					\
288 } while(0)
289 #else
290 #define PCI_FIX_ADDR(addr) (addr)
291 #endif
292 
293 
294 /*
295  * Non ordered and non-swapping "raw" accessors
296  */
297 
__raw_readb(const volatile void __iomem * addr)298 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
299 {
300 	return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
301 }
302 #define __raw_readb __raw_readb
303 
__raw_readw(const volatile void __iomem * addr)304 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
305 {
306 	return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
307 }
308 #define __raw_readw __raw_readw
309 
__raw_readl(const volatile void __iomem * addr)310 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
311 {
312 	return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
313 }
314 #define __raw_readl __raw_readl
315 
__raw_writeb(unsigned char v,volatile void __iomem * addr)316 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
317 {
318 	*(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
319 }
320 #define __raw_writeb __raw_writeb
321 
__raw_writew(unsigned short v,volatile void __iomem * addr)322 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
323 {
324 	*(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
325 }
326 #define __raw_writew __raw_writew
327 
__raw_writel(unsigned int v,volatile void __iomem * addr)328 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
329 {
330 	*(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
331 }
332 #define __raw_writel __raw_writel
333 
334 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)335 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
336 {
337 	return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
338 }
339 #define __raw_readq __raw_readq
340 
__raw_writeq(unsigned long v,volatile void __iomem * addr)341 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
342 {
343 	*(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
344 }
345 #define __raw_writeq __raw_writeq
346 
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)347 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
348 {
349 	__raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
350 }
351 #define __raw_writeq_be __raw_writeq_be
352 
353 /*
354  * Real mode versions of the above. Those instructions are only supposed
355  * to be used in hypervisor real mode as per the architecture spec.
356  */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)357 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
358 {
359 	__asm__ __volatile__(".machine push;   \
360 			      .machine power6; \
361 			      stbcix %0,0,%1;  \
362 			      .machine pop;"
363 		: : "r" (val), "r" (paddr) : "memory");
364 }
365 
__raw_rm_writew(u16 val,volatile void __iomem * paddr)366 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
367 {
368 	__asm__ __volatile__(".machine push;   \
369 			      .machine power6; \
370 			      sthcix %0,0,%1;  \
371 			      .machine pop;"
372 		: : "r" (val), "r" (paddr) : "memory");
373 }
374 
__raw_rm_writel(u32 val,volatile void __iomem * paddr)375 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
376 {
377 	__asm__ __volatile__(".machine push;   \
378 			      .machine power6; \
379 			      stwcix %0,0,%1;  \
380 			      .machine pop;"
381 		: : "r" (val), "r" (paddr) : "memory");
382 }
383 
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)384 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
385 {
386 	__asm__ __volatile__(".machine push;   \
387 			      .machine power6; \
388 			      stdcix %0,0,%1;  \
389 			      .machine pop;"
390 		: : "r" (val), "r" (paddr) : "memory");
391 }
392 
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)393 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
394 {
395 	__raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
396 }
397 
__raw_rm_readb(volatile void __iomem * paddr)398 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
399 {
400 	u8 ret;
401 	__asm__ __volatile__(".machine push;   \
402 			      .machine power6; \
403 			      lbzcix %0,0, %1; \
404 			      .machine pop;"
405 			     : "=r" (ret) : "r" (paddr) : "memory");
406 	return ret;
407 }
408 
__raw_rm_readw(volatile void __iomem * paddr)409 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
410 {
411 	u16 ret;
412 	__asm__ __volatile__(".machine push;   \
413 			      .machine power6; \
414 			      lhzcix %0,0, %1; \
415 			      .machine pop;"
416 			     : "=r" (ret) : "r" (paddr) : "memory");
417 	return ret;
418 }
419 
__raw_rm_readl(volatile void __iomem * paddr)420 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
421 {
422 	u32 ret;
423 	__asm__ __volatile__(".machine push;   \
424 			      .machine power6; \
425 			      lwzcix %0,0, %1; \
426 			      .machine pop;"
427 			     : "=r" (ret) : "r" (paddr) : "memory");
428 	return ret;
429 }
430 
__raw_rm_readq(volatile void __iomem * paddr)431 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
432 {
433 	u64 ret;
434 	__asm__ __volatile__(".machine push;   \
435 			      .machine power6; \
436 			      ldcix %0,0, %1;  \
437 			      .machine pop;"
438 			     : "=r" (ret) : "r" (paddr) : "memory");
439 	return ret;
440 }
441 #endif /* __powerpc64__ */
442 
443 /*
444  *
445  * PCI PIO and MMIO accessors.
446  *
447  *
448  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
449  * machine checks (which they occasionally do when probing non existing
450  * IO ports on some platforms, like PowerMac and 8xx).
451  * I always found it to be of dubious reliability and I am tempted to get
452  * rid of it one of these days. So if you think it's important to keep it,
453  * please voice up asap. We never had it for 64 bits and I do not intend
454  * to port it over
455  */
456 
457 #ifdef CONFIG_PPC32
458 
459 #define __do_in_asm(name, op)				\
460 static inline unsigned int name(unsigned int port)	\
461 {							\
462 	unsigned int x;					\
463 	__asm__ __volatile__(				\
464 		"sync\n"				\
465 		"0:"	op "	%0,0,%1\n"		\
466 		"1:	twi	0,%0,0\n"		\
467 		"2:	isync\n"			\
468 		"3:	nop\n"				\
469 		"4:\n"					\
470 		".section .fixup,\"ax\"\n"		\
471 		"5:	li	%0,-1\n"		\
472 		"	b	4b\n"			\
473 		".previous\n"				\
474 		EX_TABLE(0b, 5b)			\
475 		EX_TABLE(1b, 5b)			\
476 		EX_TABLE(2b, 5b)			\
477 		EX_TABLE(3b, 5b)			\
478 		: "=&r" (x)				\
479 		: "r" (port + _IO_BASE)			\
480 		: "memory");  				\
481 	return x;					\
482 }
483 
484 #define __do_out_asm(name, op)				\
485 static inline void name(unsigned int val, unsigned int port) \
486 {							\
487 	__asm__ __volatile__(				\
488 		"sync\n"				\
489 		"0:" op " %0,0,%1\n"			\
490 		"1:	sync\n"				\
491 		"2:\n"					\
492 		EX_TABLE(0b, 2b)			\
493 		EX_TABLE(1b, 2b)			\
494 		: : "r" (val), "r" (port + _IO_BASE)	\
495 		: "memory");   	   	   		\
496 }
497 
498 __do_in_asm(_rec_inb, "lbzx")
499 __do_in_asm(_rec_inw, "lhbrx")
500 __do_in_asm(_rec_inl, "lwbrx")
501 __do_out_asm(_rec_outb, "stbx")
502 __do_out_asm(_rec_outw, "sthbrx")
503 __do_out_asm(_rec_outl, "stwbrx")
504 
505 #endif /* CONFIG_PPC32 */
506 
507 /* The "__do_*" operations below provide the actual "base" implementation
508  * for each of the defined accessors. Some of them use the out_* functions
509  * directly, some of them still use EEH, though we might change that in the
510  * future. Those macros below provide the necessary argument swapping and
511  * handling of the IO base for PIO.
512  *
513  * They are themselves used by the macros that define the actual accessors
514  * and can be used by the hooks if any.
515  *
516  * Note that PIO operations are always defined in terms of their corresonding
517  * MMIO operations. That allows platforms like iSeries who want to modify the
518  * behaviour of both to only hook on the MMIO version and get both. It's also
519  * possible to hook directly at the toplevel PIO operation if they have to
520  * be handled differently
521  */
522 #define __do_writeb(val, addr)	out_8(PCI_FIX_ADDR(addr), val)
523 #define __do_writew(val, addr)	out_le16(PCI_FIX_ADDR(addr), val)
524 #define __do_writel(val, addr)	out_le32(PCI_FIX_ADDR(addr), val)
525 #define __do_writeq(val, addr)	out_le64(PCI_FIX_ADDR(addr), val)
526 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
527 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
528 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
529 
530 #ifdef CONFIG_EEH
531 #define __do_readb(addr)	eeh_readb(PCI_FIX_ADDR(addr))
532 #define __do_readw(addr)	eeh_readw(PCI_FIX_ADDR(addr))
533 #define __do_readl(addr)	eeh_readl(PCI_FIX_ADDR(addr))
534 #define __do_readq(addr)	eeh_readq(PCI_FIX_ADDR(addr))
535 #define __do_readw_be(addr)	eeh_readw_be(PCI_FIX_ADDR(addr))
536 #define __do_readl_be(addr)	eeh_readl_be(PCI_FIX_ADDR(addr))
537 #define __do_readq_be(addr)	eeh_readq_be(PCI_FIX_ADDR(addr))
538 #else /* CONFIG_EEH */
539 #define __do_readb(addr)	in_8(PCI_FIX_ADDR(addr))
540 #define __do_readw(addr)	in_le16(PCI_FIX_ADDR(addr))
541 #define __do_readl(addr)	in_le32(PCI_FIX_ADDR(addr))
542 #define __do_readq(addr)	in_le64(PCI_FIX_ADDR(addr))
543 #define __do_readw_be(addr)	in_be16(PCI_FIX_ADDR(addr))
544 #define __do_readl_be(addr)	in_be32(PCI_FIX_ADDR(addr))
545 #define __do_readq_be(addr)	in_be64(PCI_FIX_ADDR(addr))
546 #endif /* !defined(CONFIG_EEH) */
547 
548 #ifdef CONFIG_PPC32
549 #define __do_outb(val, port)	_rec_outb(val, port)
550 #define __do_outw(val, port)	_rec_outw(val, port)
551 #define __do_outl(val, port)	_rec_outl(val, port)
552 #define __do_inb(port)		_rec_inb(port)
553 #define __do_inw(port)		_rec_inw(port)
554 #define __do_inl(port)		_rec_inl(port)
555 #else /* CONFIG_PPC32 */
556 #define __do_outb(val, port)	writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
557 #define __do_outw(val, port)	writew(val,(PCI_IO_ADDR)_IO_BASE+port);
558 #define __do_outl(val, port)	writel(val,(PCI_IO_ADDR)_IO_BASE+port);
559 #define __do_inb(port)		readb((PCI_IO_ADDR)_IO_BASE + port);
560 #define __do_inw(port)		readw((PCI_IO_ADDR)_IO_BASE + port);
561 #define __do_inl(port)		readl((PCI_IO_ADDR)_IO_BASE + port);
562 #endif /* !CONFIG_PPC32 */
563 
564 #ifdef CONFIG_EEH
565 #define __do_readsb(a, b, n)	eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
566 #define __do_readsw(a, b, n)	eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
567 #define __do_readsl(a, b, n)	eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
568 #else /* CONFIG_EEH */
569 #define __do_readsb(a, b, n)	_insb(PCI_FIX_ADDR(a), (b), (n))
570 #define __do_readsw(a, b, n)	_insw(PCI_FIX_ADDR(a), (b), (n))
571 #define __do_readsl(a, b, n)	_insl(PCI_FIX_ADDR(a), (b), (n))
572 #endif /* !CONFIG_EEH */
573 #define __do_writesb(a, b, n)	_outsb(PCI_FIX_ADDR(a),(b),(n))
574 #define __do_writesw(a, b, n)	_outsw(PCI_FIX_ADDR(a),(b),(n))
575 #define __do_writesl(a, b, n)	_outsl(PCI_FIX_ADDR(a),(b),(n))
576 
577 #define __do_insb(p, b, n)	readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
578 #define __do_insw(p, b, n)	readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
579 #define __do_insl(p, b, n)	readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
580 #define __do_outsb(p, b, n)	writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
581 #define __do_outsw(p, b, n)	writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
582 #define __do_outsl(p, b, n)	writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
583 
584 #define __do_memset_io(addr, c, n)	\
585 				_memset_io(PCI_FIX_ADDR(addr), c, n)
586 #define __do_memcpy_toio(dst, src, n)	\
587 				_memcpy_toio(PCI_FIX_ADDR(dst), src, n)
588 
589 #ifdef CONFIG_EEH
590 #define __do_memcpy_fromio(dst, src, n)	\
591 				eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
592 #else /* CONFIG_EEH */
593 #define __do_memcpy_fromio(dst, src, n)	\
594 				_memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
595 #endif /* !CONFIG_EEH */
596 
597 #ifdef CONFIG_PPC_INDIRECT_PIO
598 #define DEF_PCI_HOOK_pio(x)	x
599 #else
600 #define DEF_PCI_HOOK_pio(x)	NULL
601 #endif
602 
603 #ifdef CONFIG_PPC_INDIRECT_MMIO
604 #define DEF_PCI_HOOK_mem(x)	x
605 #else
606 #define DEF_PCI_HOOK_mem(x)	NULL
607 #endif
608 
609 /* Structure containing all the hooks */
610 extern struct ppc_pci_io {
611 
612 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)	ret (*name) at;
613 #define DEF_PCI_AC_NORET(name, at, al, space, aa)	void (*name) at;
614 
615 #include <asm/io-defs.h>
616 
617 #undef DEF_PCI_AC_RET
618 #undef DEF_PCI_AC_NORET
619 
620 } ppc_pci_io;
621 
622 /* The inline wrappers */
623 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)		\
624 static inline ret name at					\
625 {								\
626 	if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)	\
627 		return ppc_pci_io.name al;			\
628 	return __do_##name al;					\
629 }
630 
631 #define DEF_PCI_AC_NORET(name, at, al, space, aa)		\
632 static inline void name at					\
633 {								\
634 	if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)		\
635 		ppc_pci_io.name al;				\
636 	else							\
637 		__do_##name al;					\
638 }
639 
640 #include <asm/io-defs.h>
641 
642 #undef DEF_PCI_AC_RET
643 #undef DEF_PCI_AC_NORET
644 
645 /* Some drivers check for the presence of readq & writeq with
646  * a #ifdef, so we make them happy here.
647  */
648 #define readb readb
649 #define readw readw
650 #define readl readl
651 #define writeb writeb
652 #define writew writew
653 #define writel writel
654 #define readsb readsb
655 #define readsw readsw
656 #define readsl readsl
657 #define writesb writesb
658 #define writesw writesw
659 #define writesl writesl
660 #define inb inb
661 #define inw inw
662 #define inl inl
663 #define outb outb
664 #define outw outw
665 #define outl outl
666 #define insb insb
667 #define insw insw
668 #define insl insl
669 #define outsb outsb
670 #define outsw outsw
671 #define outsl outsl
672 #ifdef __powerpc64__
673 #define readq	readq
674 #define writeq	writeq
675 #endif
676 #define memset_io memset_io
677 #define memcpy_fromio memcpy_fromio
678 #define memcpy_toio memcpy_toio
679 
680 /*
681  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
682  * access
683  */
684 #define xlate_dev_mem_ptr(p)	__va(p)
685 
686 /*
687  * We don't do relaxed operations yet, at least not with this semantic
688  */
689 #define readb_relaxed(addr)	readb(addr)
690 #define readw_relaxed(addr)	readw(addr)
691 #define readl_relaxed(addr)	readl(addr)
692 #define readq_relaxed(addr)	readq(addr)
693 #define writeb_relaxed(v, addr)	writeb(v, addr)
694 #define writew_relaxed(v, addr)	writew(v, addr)
695 #define writel_relaxed(v, addr)	writel(v, addr)
696 #define writeq_relaxed(v, addr)	writeq(v, addr)
697 
698 #ifdef CONFIG_GENERIC_IOMAP
699 #include <asm-generic/iomap.h>
700 #else
701 /*
702  * Here comes the implementation of the IOMAP interfaces.
703  */
ioread16be(const void __iomem * addr)704 static inline unsigned int ioread16be(const void __iomem *addr)
705 {
706 	return readw_be(addr);
707 }
708 #define ioread16be ioread16be
709 
ioread32be(const void __iomem * addr)710 static inline unsigned int ioread32be(const void __iomem *addr)
711 {
712 	return readl_be(addr);
713 }
714 #define ioread32be ioread32be
715 
716 #ifdef __powerpc64__
ioread64_lo_hi(const void __iomem * addr)717 static inline u64 ioread64_lo_hi(const void __iomem *addr)
718 {
719 	return readq(addr);
720 }
721 #define ioread64_lo_hi ioread64_lo_hi
722 
ioread64_hi_lo(const void __iomem * addr)723 static inline u64 ioread64_hi_lo(const void __iomem *addr)
724 {
725 	return readq(addr);
726 }
727 #define ioread64_hi_lo ioread64_hi_lo
728 
ioread64be(const void __iomem * addr)729 static inline u64 ioread64be(const void __iomem *addr)
730 {
731 	return readq_be(addr);
732 }
733 #define ioread64be ioread64be
734 
ioread64be_lo_hi(const void __iomem * addr)735 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
736 {
737 	return readq_be(addr);
738 }
739 #define ioread64be_lo_hi ioread64be_lo_hi
740 
ioread64be_hi_lo(const void __iomem * addr)741 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
742 {
743 	return readq_be(addr);
744 }
745 #define ioread64be_hi_lo ioread64be_hi_lo
746 #endif /* __powerpc64__ */
747 
iowrite16be(u16 val,void __iomem * addr)748 static inline void iowrite16be(u16 val, void __iomem *addr)
749 {
750 	writew_be(val, addr);
751 }
752 #define iowrite16be iowrite16be
753 
iowrite32be(u32 val,void __iomem * addr)754 static inline void iowrite32be(u32 val, void __iomem *addr)
755 {
756 	writel_be(val, addr);
757 }
758 #define iowrite32be iowrite32be
759 
760 #ifdef __powerpc64__
iowrite64_lo_hi(u64 val,void __iomem * addr)761 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
762 {
763 	writeq(val, addr);
764 }
765 #define iowrite64_lo_hi iowrite64_lo_hi
766 
iowrite64_hi_lo(u64 val,void __iomem * addr)767 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
768 {
769 	writeq(val, addr);
770 }
771 #define iowrite64_hi_lo iowrite64_hi_lo
772 
iowrite64be(u64 val,void __iomem * addr)773 static inline void iowrite64be(u64 val, void __iomem *addr)
774 {
775 	writeq_be(val, addr);
776 }
777 #define iowrite64be iowrite64be
778 
iowrite64be_lo_hi(u64 val,void __iomem * addr)779 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
780 {
781 	writeq_be(val, addr);
782 }
783 #define iowrite64be_lo_hi iowrite64be_lo_hi
784 
iowrite64be_hi_lo(u64 val,void __iomem * addr)785 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
786 {
787 	writeq_be(val, addr);
788 }
789 #define iowrite64be_hi_lo iowrite64be_hi_lo
790 #endif /* __powerpc64__ */
791 
792 struct pci_dev;
793 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
794 #define pci_iounmap pci_iounmap
795 void __iomem *ioport_map(unsigned long port, unsigned int len);
796 #define ioport_map ioport_map
797 #endif
798 
iosync(void)799 static inline void iosync(void)
800 {
801         __asm__ __volatile__ ("sync" : : : "memory");
802 }
803 
804 /* Enforce in-order execution of data I/O.
805  * No distinction between read/write on PPC; use eieio for all three.
806  * Those are fairly week though. They don't provide a barrier between
807  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
808  * they only provide barriers between 2 __raw MMIO operations and
809  * possibly break write combining.
810  */
811 #define iobarrier_rw() eieio()
812 #define iobarrier_r()  eieio()
813 #define iobarrier_w()  eieio()
814 
815 
816 /*
817  * output pause versions need a delay at least for the
818  * w83c105 ide controller in a p610.
819  */
820 #define inb_p(port)             inb(port)
821 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
822 #define inw_p(port)             inw(port)
823 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
824 #define inl_p(port)             inl(port)
825 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
826 
827 
828 #define IO_SPACE_LIMIT ~(0UL)
829 
830 /**
831  * ioremap     -   map bus memory into CPU space
832  * @address:   bus address of the memory
833  * @size:      size of the resource to map
834  *
835  * ioremap performs a platform specific sequence of operations to
836  * make bus memory CPU accessible via the readb/readw/readl/writeb/
837  * writew/writel functions and the other mmio helpers. The returned
838  * address is not guaranteed to be usable directly as a virtual
839  * address.
840  *
841  * We provide a few variations of it:
842  *
843  * * ioremap is the standard one and provides non-cacheable guarded mappings
844  *   and can be hooked by the platform via ppc_md
845  *
846  * * ioremap_prot allows to specify the page flags as an argument and can
847  *   also be hooked by the platform via ppc_md.
848  *
849  * * ioremap_wc enables write combining
850  *
851  * * ioremap_wt enables write through
852  *
853  * * ioremap_coherent maps coherent cached memory
854  *
855  * * iounmap undoes such a mapping and can be hooked
856  *
857  * * __ioremap_caller is the same as above but takes an explicit caller
858  *   reference rather than using __builtin_return_address(0)
859  *
860  */
861 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
862 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
863 				  unsigned long flags);
864 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
865 #define ioremap_wc ioremap_wc
866 
867 #ifdef CONFIG_PPC32
868 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
869 #define ioremap_wt ioremap_wt
870 #endif
871 
872 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
873 #define ioremap_uc(addr, size)		ioremap((addr), (size))
874 #define ioremap_cache(addr, size) \
875 	ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
876 
877 extern void iounmap(volatile void __iomem *addr);
878 
879 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
880 
881 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
882 			unsigned long size, pgprot_t prot);
883 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
884 			 pgprot_t prot, void *caller);
885 
886 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
887 				      pgprot_t prot, void *caller);
888 
889 /*
890  * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
891  * which needs some additional definitions here. They basically allow PIO
892  * space overall to be 1GB. This will work as long as we never try to use
893  * iomap to map MMIO below 1GB which should be fine on ppc64
894  */
895 #define HAVE_ARCH_PIO_SIZE		1
896 #define PIO_OFFSET			0x00000000UL
897 #define PIO_MASK			(FULL_IO_SIZE - 1)
898 #define PIO_RESERVED			(FULL_IO_SIZE)
899 
900 #define mmio_read16be(addr)		readw_be(addr)
901 #define mmio_read32be(addr)		readl_be(addr)
902 #define mmio_read64be(addr)		readq_be(addr)
903 #define mmio_write16be(val, addr)	writew_be(val, addr)
904 #define mmio_write32be(val, addr)	writel_be(val, addr)
905 #define mmio_write64be(val, addr)	writeq_be(val, addr)
906 #define mmio_insb(addr, dst, count)	readsb(addr, dst, count)
907 #define mmio_insw(addr, dst, count)	readsw(addr, dst, count)
908 #define mmio_insl(addr, dst, count)	readsl(addr, dst, count)
909 #define mmio_outsb(addr, src, count)	writesb(addr, src, count)
910 #define mmio_outsw(addr, src, count)	writesw(addr, src, count)
911 #define mmio_outsl(addr, src, count)	writesl(addr, src, count)
912 
913 /**
914  *	virt_to_phys	-	map virtual addresses to physical
915  *	@address: address to remap
916  *
917  *	The returned physical address is the physical (CPU) mapping for
918  *	the memory address given. It is only valid to use this function on
919  *	addresses directly mapped or allocated via kmalloc.
920  *
921  *	This function does not give bus mappings for DMA transfers. In
922  *	almost all conceivable cases a device driver should not be using
923  *	this function
924  */
virt_to_phys(volatile void * address)925 static inline unsigned long virt_to_phys(volatile void * address)
926 {
927 	WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
928 
929 	return __pa((unsigned long)address);
930 }
931 #define virt_to_phys virt_to_phys
932 
933 /**
934  *	phys_to_virt	-	map physical address to virtual
935  *	@address: address to remap
936  *
937  *	The returned virtual address is a current CPU mapping for
938  *	the memory address given. It is only valid to use this function on
939  *	addresses that have a kernel mapping
940  *
941  *	This function does not handle bus mappings for DMA transfers. In
942  *	almost all conceivable cases a device driver should not be using
943  *	this function
944  */
phys_to_virt(unsigned long address)945 static inline void * phys_to_virt(unsigned long address)
946 {
947 	return (void *)__va(address);
948 }
949 #define phys_to_virt phys_to_virt
950 
951 /*
952  * Change "struct page" to physical address.
953  */
page_to_phys(struct page * page)954 static inline phys_addr_t page_to_phys(struct page *page)
955 {
956 	unsigned long pfn = page_to_pfn(page);
957 
958 	WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
959 
960 	return PFN_PHYS(pfn);
961 }
962 
963 /*
964  * 32 bits still uses virt_to_bus() for it's implementation of DMA
965  * mappings se we have to keep it defined here. We also have some old
966  * drivers (shame shame shame) that use bus_to_virt() and haven't been
967  * fixed yet so I need to define it here.
968  */
969 #ifdef CONFIG_PPC32
970 
virt_to_bus(volatile void * address)971 static inline unsigned long virt_to_bus(volatile void * address)
972 {
973         if (address == NULL)
974 		return 0;
975         return __pa(address) + PCI_DRAM_OFFSET;
976 }
977 #define virt_to_bus virt_to_bus
978 
bus_to_virt(unsigned long address)979 static inline void * bus_to_virt(unsigned long address)
980 {
981         if (address == 0)
982 		return NULL;
983         return __va(address - PCI_DRAM_OFFSET);
984 }
985 #define bus_to_virt bus_to_virt
986 
987 #endif /* CONFIG_PPC32 */
988 
989 /* access ports */
990 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
991 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
992 
993 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
994 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
995 
996 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
997 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
998 
999 /* Clear and set bits in one shot.  These macros can be used to clear and
1000  * set multiple bits in a register using a single read-modify-write.  These
1001  * macros can also be used to set a multiple-bit bit pattern using a mask,
1002  * by specifying the mask in the 'clear' parameter and the new bit pattern
1003  * in the 'set' parameter.
1004  */
1005 
1006 #define clrsetbits(type, addr, clear, set) \
1007 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1008 
1009 #ifdef __powerpc64__
1010 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1011 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1012 #endif
1013 
1014 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1015 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1016 
1017 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1018 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1019 
1020 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1021 
1022 #include <asm-generic/io.h>
1023 
1024 #endif /* __KERNEL__ */
1025 
1026 #endif /* _ASM_POWERPC_IO_H */
1027