1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale Media5200 board Device Tree Source
4 *
5 * Copyright 2009 Secret Lab Technologies Ltd.
6 * Grant Likely <grant.likely@secretlab.ca>
7 * Steven Cavanagh <scavanagh@secretlab.ca>
8 */
9
10/include/ "mpc5200b.dtsi"
11
12&gpt0 { fsl,has-wdt; };
13
14/ {
15	model = "fsl,media5200";
16	compatible = "fsl,media5200";
17
18	aliases {
19		console = &console;
20		ethernet0 = &eth0;
21	};
22
23	chosen {
24		stdout-path = &console;
25	};
26
27	cpus {
28		PowerPC,5200@0 {
29			timebase-frequency = <33000000>;	// 33 MHz, these were configured by U-Boot
30			bus-frequency = <132000000>;		// 132 MHz
31			clock-frequency = <396000000>;		// 396 MHz
32		};
33	};
34
35	memory@0 {
36		reg = <0x00000000 0x08000000>;	// 128MB RAM
37	};
38
39	soc5200@f0000000 {
40		bus-frequency = <132000000>;// 132 MHz
41
42		psc@2000 {	// PSC1
43			status = "disabled";
44		};
45
46		psc@2200 {	// PSC2
47			status = "disabled";
48		};
49
50		psc@2400 {	// PSC3
51			status = "disabled";
52		};
53
54		psc@2600 {	// PSC4
55			status = "disabled";
56		};
57
58		psc@2800 {	// PSC5
59			status = "disabled";
60		};
61
62		// PSC6 in uart mode
63		console: psc@2c00 {		// PSC6
64			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
65		};
66
67		ethernet@3000 {
68			phy-handle = <&phy0>;
69		};
70
71		mdio@3000 {
72			phy0: ethernet-phy@0 {
73				reg = <0>;
74			};
75		};
76
77		usb@1000 {
78			reg = <0x1000 0x100>;
79		};
80	};
81
82	pci@f0000d00 {
83		interrupt-map-mask = <0xf800 0 0 7>;
84		interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85				 0xc000 0 0 2 &media5200_fpga 0 3
86				 0xc000 0 0 3 &media5200_fpga 0 4
87				 0xc000 0 0 4 &media5200_fpga 0 5
88
89				 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
90				 0xc800 0 0 2 &media5200_fpga 0 4
91				 0xc800 0 0 3 &media5200_fpga 0 5
92				 0xc800 0 0 4 &media5200_fpga 0 2
93
94				 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
95				 0xd000 0 0 2 &media5200_fpga 0 5
96
97				 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
98				>;
99		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
100			 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
101			 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
102		interrupt-parent = <&mpc5200_pic>;
103	};
104
105	localbus {
106		ranges = < 0 0 0xfc000000 0x02000000
107			   1 0 0xfe000000 0x02000000
108			   2 0 0xf0010000 0x00010000
109			   3 0 0xf0020000 0x00010000 >;
110		flash@0,0 {
111			compatible = "amd,am29lv28ml", "cfi-flash";
112			reg = <0 0x0 0x2000000>;                // 32 MB
113			bank-width = <4>;                       // Width in bytes of the flash bank
114			device-width = <2>;                     // Two devices on each bank
115		};
116
117		flash@1,0 {
118			compatible = "amd,am29lv28ml", "cfi-flash";
119			reg = <1 0 0x2000000>;                  // 32 MB
120			bank-width = <4>;                       // Width in bytes of the flash bank
121			device-width = <2>;                     // Two devices on each bank
122		};
123
124		media5200_fpga: fpga@2,0 {
125			compatible = "fsl,media5200-fpga";
126			interrupt-controller;
127			#interrupt-cells = <2>;	// 0:bank 1:id; no type field
128			reg = <2 0 0x10000>;
129
130			interrupt-parent = <&mpc5200_pic>;
131			interrupts = <0 0 3	// IRQ bank 0
132			              1 1 3>;	// IRQ bank 1
133		};
134
135		uart@3,0 {
136			compatible = "ti,tl16c752bpt";
137			reg = <3 0 0x10000>;
138			interrupt-parent = <&media5200_fpga>;
139			interrupts = <0 0  0 1>; // 2 irqs
140		};
141	};
142};
143