1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/traps.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 */
7 #ifndef __ASM_TRAP_H
8 #define __ASM_TRAP_H
9
10 #include <linux/list.h>
11 #include <asm/esr.h>
12 #include <asm/sections.h>
13
14 struct pt_regs;
15
16 struct undef_hook {
17 struct list_head node;
18 u32 instr_mask;
19 u32 instr_val;
20 u64 pstate_mask;
21 u64 pstate_val;
22 int (*fn)(struct pt_regs *regs, u32 instr);
23 };
24
25 void register_undef_hook(struct undef_hook *hook);
26 void unregister_undef_hook(struct undef_hook *hook);
27 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);
28 void arm64_notify_segfault(unsigned long addr);
29 void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
30 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
31 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
32
33 /*
34 * Move regs->pc to next instruction and do necessary setup before it
35 * is executed.
36 */
37 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
38
__in_irqentry_text(unsigned long ptr)39 static inline int __in_irqentry_text(unsigned long ptr)
40 {
41 return ptr >= (unsigned long)&__irqentry_text_start &&
42 ptr < (unsigned long)&__irqentry_text_end;
43 }
44
in_entry_text(unsigned long ptr)45 static inline int in_entry_text(unsigned long ptr)
46 {
47 return ptr >= (unsigned long)&__entry_text_start &&
48 ptr < (unsigned long)&__entry_text_end;
49 }
50
51 /*
52 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
53 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
54 * have a ISS-Valid bit in the same position.
55 * If this bit is set, we know its not a RAS SError.
56 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
57 * errors share the same encoding as an all-zeros encoding from a CPU that
58 * doesn't support RAS.
59 */
arm64_is_ras_serror(unsigned long esr)60 static inline bool arm64_is_ras_serror(unsigned long esr)
61 {
62 WARN_ON(preemptible());
63
64 if (esr & ESR_ELx_IDS)
65 return false;
66
67 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
68 return true;
69 else
70 return false;
71 }
72
73 /*
74 * Return the AET bits from a RAS SError's ESR.
75 *
76 * It is implementation defined whether Uncategorized errors are containable.
77 * We treat them as Uncontainable.
78 * Non-RAS SError's are reported as Uncontained/Uncategorized.
79 */
arm64_ras_serror_get_severity(unsigned long esr)80 static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
81 {
82 unsigned long aet = esr & ESR_ELx_AET;
83
84 if (!arm64_is_ras_serror(esr)) {
85 /* Not a RAS error, we can't interpret the ESR. */
86 return ESR_ELx_AET_UC;
87 }
88
89 /*
90 * AET is RES0 if 'the value returned in the DFSC field is not
91 * [ESR_ELx_FSC_SERROR]'
92 */
93 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
94 /* No severity information : Uncategorized */
95 return ESR_ELx_AET_UC;
96 }
97
98 return aet;
99 }
100
101 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
102 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
103 #endif
104