1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012,2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  */
6 
7 #ifndef __ARM64_KVM_MMU_H__
8 #define __ARM64_KVM_MMU_H__
9 
10 #include <asm/page.h>
11 #include <asm/memory.h>
12 #include <asm/mmu.h>
13 #include <asm/cpufeature.h>
14 
15 /*
16  * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
17  * "negative" addresses. This makes it impossible to directly share
18  * mappings with the kernel.
19  *
20  * Instead, give the HYP mode its own VA region at a fixed offset from
21  * the kernel by just masking the top bits (which are all ones for a
22  * kernel address). We need to find out how many bits to mask.
23  *
24  * We want to build a set of page tables that cover both parts of the
25  * idmap (the trampoline page used to initialize EL2), and our normal
26  * runtime VA space, at the same time.
27  *
28  * Given that the kernel uses VA_BITS for its entire address space,
29  * and that half of that space (VA_BITS - 1) is used for the linear
30  * mapping, we can also limit the EL2 space to (VA_BITS - 1).
31  *
32  * The main question is "Within the VA_BITS space, does EL2 use the
33  * top or the bottom half of that space to shadow the kernel's linear
34  * mapping?". As we need to idmap the trampoline page, this is
35  * determined by the range in which this page lives.
36  *
37  * If the page is in the bottom half, we have to use the top half. If
38  * the page is in the top half, we have to use the bottom half:
39  *
40  * T = __pa_symbol(__hyp_idmap_text_start)
41  * if (T & BIT(VA_BITS - 1))
42  *	HYP_VA_MIN = 0  //idmap in upper half
43  * else
44  *	HYP_VA_MIN = 1 << (VA_BITS - 1)
45  * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
46  *
47  * When using VHE, there are no separate hyp mappings and all KVM
48  * functionality is already mapped as part of the main kernel
49  * mappings, and none of this applies in that case.
50  */
51 
52 #ifdef __ASSEMBLY__
53 
54 #include <asm/alternative.h>
55 
56 /*
57  * Convert a kernel VA into a HYP VA.
58  * reg: VA to be converted.
59  *
60  * The actual code generation takes place in kvm_update_va_mask, and
61  * the instructions below are only there to reserve the space and
62  * perform the register allocation (kvm_update_va_mask uses the
63  * specific registers encoded in the instructions).
64  */
65 .macro kern_hyp_va	reg
66 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_update_va_mask
67 	and     \reg, \reg, #1		/* mask with va_mask */
68 	ror	\reg, \reg, #1		/* rotate to the first tag bit */
69 	add	\reg, \reg, #0		/* insert the low 12 bits of the tag */
70 	add	\reg, \reg, #0, lsl 12	/* insert the top 12 bits of the tag */
71 	ror	\reg, \reg, #63		/* rotate back */
72 alternative_cb_end
73 .endm
74 
75 /*
76  * Convert a hypervisor VA to a PA
77  * reg: hypervisor address to be converted in place
78  * tmp: temporary register
79  */
80 .macro hyp_pa reg, tmp
81 	ldr_l	\tmp, hyp_physvirt_offset
82 	add	\reg, \reg, \tmp
83 .endm
84 
85 /*
86  * Convert a hypervisor VA to a kernel image address
87  * reg: hypervisor address to be converted in place
88  * tmp: temporary register
89  *
90  * The actual code generation takes place in kvm_get_kimage_voffset, and
91  * the instructions below are only there to reserve the space and
92  * perform the register allocation (kvm_get_kimage_voffset uses the
93  * specific registers encoded in the instructions).
94  */
95 .macro hyp_kimg_va reg, tmp
96 	/* Convert hyp VA -> PA. */
97 	hyp_pa	\reg, \tmp
98 
99 	/* Load kimage_voffset. */
100 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_get_kimage_voffset
101 	movz	\tmp, #0
102 	movk	\tmp, #0, lsl #16
103 	movk	\tmp, #0, lsl #32
104 	movk	\tmp, #0, lsl #48
105 alternative_cb_end
106 
107 	/* Convert PA -> kimg VA. */
108 	add	\reg, \reg, \tmp
109 .endm
110 
111 #else
112 
113 #include <linux/pgtable.h>
114 #include <asm/pgalloc.h>
115 #include <asm/cache.h>
116 #include <asm/cacheflush.h>
117 #include <asm/mmu_context.h>
118 #include <asm/kvm_host.h>
119 
120 void kvm_update_va_mask(struct alt_instr *alt,
121 			__le32 *origptr, __le32 *updptr, int nr_inst);
122 void kvm_compute_layout(void);
123 void kvm_apply_hyp_relocations(void);
124 
125 #define __hyp_pa(x) (((phys_addr_t)(x)) + hyp_physvirt_offset)
126 
__kern_hyp_va(unsigned long v)127 static __always_inline unsigned long __kern_hyp_va(unsigned long v)
128 {
129 	asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
130 				    "ror %0, %0, #1\n"
131 				    "add %0, %0, #0\n"
132 				    "add %0, %0, #0, lsl 12\n"
133 				    "ror %0, %0, #63\n",
134 				    ARM64_ALWAYS_SYSTEM,
135 				    kvm_update_va_mask)
136 		     : "+r" (v));
137 	return v;
138 }
139 
140 #define kern_hyp_va(v) 	((typeof(v))(__kern_hyp_va((unsigned long)(v))))
141 
142 /*
143  * We currently support using a VM-specified IPA size. For backward
144  * compatibility, the default IPA size is fixed to 40bits.
145  */
146 #define KVM_PHYS_SHIFT	(40)
147 
148 #define kvm_phys_shift(kvm)		VTCR_EL2_IPA(kvm->arch.vtcr)
149 #define kvm_phys_size(kvm)		(_AC(1, ULL) << kvm_phys_shift(kvm))
150 #define kvm_phys_mask(kvm)		(kvm_phys_size(kvm) - _AC(1, ULL))
151 
152 #include <asm/kvm_pgtable.h>
153 #include <asm/stage2_pgtable.h>
154 
155 int kvm_share_hyp(void *from, void *to);
156 void kvm_unshare_hyp(void *from, void *to);
157 int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot);
158 int __create_hyp_mappings(unsigned long start, unsigned long size,
159 			  unsigned long phys, enum kvm_pgtable_prot prot);
160 int hyp_alloc_private_va_range(size_t size, unsigned long *haddr);
161 int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
162 			   void __iomem **kaddr,
163 			   void __iomem **haddr);
164 int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
165 			     void **haddr);
166 void free_hyp_pgds(void);
167 
168 void stage2_unmap_vm(struct kvm *kvm);
169 int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu);
170 void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
171 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
172 			  phys_addr_t pa, unsigned long size, bool writable);
173 
174 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
175 
176 phys_addr_t kvm_mmu_get_httbr(void);
177 phys_addr_t kvm_get_idmap_vector(void);
178 int kvm_mmu_init(u32 *hyp_va_bits);
179 
__kvm_vector_slot2addr(void * base,enum arm64_hyp_spectre_vector slot)180 static inline void *__kvm_vector_slot2addr(void *base,
181 					   enum arm64_hyp_spectre_vector slot)
182 {
183 	int idx = slot - (slot != HYP_VECTOR_DIRECT);
184 
185 	return base + (idx * SZ_2K);
186 }
187 
188 struct kvm;
189 
190 #define kvm_flush_dcache_to_poc(a,l)	\
191 	dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))
192 
vcpu_has_cache_enabled(struct kvm_vcpu * vcpu)193 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
194 {
195 	return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
196 }
197 
__clean_dcache_guest_page(void * va,size_t size)198 static inline void __clean_dcache_guest_page(void *va, size_t size)
199 {
200 	/*
201 	 * With FWB, we ensure that the guest always accesses memory using
202 	 * cacheable attributes, and we don't have to clean to PoC when
203 	 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to
204 	 * PoU is not required either in this case.
205 	 */
206 	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
207 		return;
208 
209 	kvm_flush_dcache_to_poc(va, size);
210 }
211 
__invalidate_icache_guest_page(void * va,size_t size)212 static inline void __invalidate_icache_guest_page(void *va, size_t size)
213 {
214 	if (icache_is_aliasing()) {
215 		/* any kind of VIPT cache */
216 		icache_inval_all_pou();
217 	} else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) {
218 		/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
219 		icache_inval_pou((unsigned long)va, (unsigned long)va + size);
220 	}
221 }
222 
223 void kvm_set_way_flush(struct kvm_vcpu *vcpu);
224 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
225 
kvm_get_vmid_bits(void)226 static inline unsigned int kvm_get_vmid_bits(void)
227 {
228 	int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
229 
230 	return get_vmid_bits(reg);
231 }
232 
233 /*
234  * We are not in the kvm->srcu critical section most of the time, so we take
235  * the SRCU read lock here. Since we copy the data from the user page, we
236  * can immediately drop the lock again.
237  */
kvm_read_guest_lock(struct kvm * kvm,gpa_t gpa,void * data,unsigned long len)238 static inline int kvm_read_guest_lock(struct kvm *kvm,
239 				      gpa_t gpa, void *data, unsigned long len)
240 {
241 	int srcu_idx = srcu_read_lock(&kvm->srcu);
242 	int ret = kvm_read_guest(kvm, gpa, data, len);
243 
244 	srcu_read_unlock(&kvm->srcu, srcu_idx);
245 
246 	return ret;
247 }
248 
kvm_write_guest_lock(struct kvm * kvm,gpa_t gpa,const void * data,unsigned long len)249 static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
250 				       const void *data, unsigned long len)
251 {
252 	int srcu_idx = srcu_read_lock(&kvm->srcu);
253 	int ret = kvm_write_guest(kvm, gpa, data, len);
254 
255 	srcu_read_unlock(&kvm->srcu, srcu_idx);
256 
257 	return ret;
258 }
259 
260 #define kvm_phys_to_vttbr(addr)		phys_to_ttbr(addr)
261 
262 /*
263  * When this is (directly or indirectly) used on the TLB invalidation
264  * path, we rely on a previously issued DSB so that page table updates
265  * and VMID reads are correctly ordered.
266  */
kvm_get_vttbr(struct kvm_s2_mmu * mmu)267 static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
268 {
269 	struct kvm_vmid *vmid = &mmu->vmid;
270 	u64 vmid_field, baddr;
271 	u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
272 
273 	baddr = mmu->pgd_phys;
274 	vmid_field = atomic64_read(&vmid->id) << VTTBR_VMID_SHIFT;
275 	vmid_field &= VTTBR_VMID_MASK(kvm_arm_vmid_bits);
276 	return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
277 }
278 
279 /*
280  * Must be called from hyp code running at EL2 with an updated VTTBR
281  * and interrupts disabled.
282  */
__load_stage2(struct kvm_s2_mmu * mmu,struct kvm_arch * arch)283 static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
284 					  struct kvm_arch *arch)
285 {
286 	write_sysreg(arch->vtcr, vtcr_el2);
287 	write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
288 
289 	/*
290 	 * ARM errata 1165522 and 1530923 require the actual execution of the
291 	 * above before we can switch to the EL1/EL0 translation regime used by
292 	 * the guest.
293 	 */
294 	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
295 }
296 
kvm_s2_mmu_to_kvm(struct kvm_s2_mmu * mmu)297 static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu)
298 {
299 	return container_of(mmu->arch, struct kvm, arch);
300 }
301 #endif /* __ASSEMBLY__ */
302 #endif /* __ARM64_KVM_MMU_H__ */
303