1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10#include <dt-bindings/mux/ti-serdes.h> 11 12/ { 13 cmn_refclk: clock-cmnrefclk { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <0>; 17 }; 18 19 cmn_refclk1: clock-cmnrefclk1 { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 clock-frequency = <0>; 23 }; 24}; 25 26&cbass_main { 27 msmc_ram: sram@70000000 { 28 compatible = "mmio-sram"; 29 reg = <0x0 0x70000000 0x0 0x800000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 ranges = <0x0 0x0 0x70000000 0x800000>; 33 34 atf-sram@0 { 35 reg = <0x0 0x20000>; 36 }; 37 }; 38 39 scm_conf: scm-conf@100000 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x0 0x00100000 0x1c000>; 45 46 serdes_ln_ctrl: mux-controller@4080 { 47 compatible = "mmio-mux"; 48 reg = <0x00004080 0x50>; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 51 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 52 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 53 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 54 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 55 /* SERDES4 lane0/1/2/3 select */ 56 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 57 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 58 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 59 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 60 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 61 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 62 }; 63 64 usb_serdes_mux: mux-controller@4000 { 65 compatible = "mmio-mux"; 66 #mux-control-cells = <1>; 67 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 68 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 69 }; 70 }; 71 72 gic500: interrupt-controller@1800000 { 73 compatible = "arm,gic-v3"; 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 #interrupt-cells = <3>; 78 interrupt-controller; 79 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 80 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 81 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 82 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 83 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 84 85 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 86 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 87 88 gic_its: msi-controller@1820000 { 89 compatible = "arm,gic-v3-its"; 90 reg = <0x00 0x01820000 0x00 0x10000>; 91 socionext,synquacer-pre-its = <0x1000000 0x400000>; 92 msi-controller; 93 #msi-cells = <1>; 94 }; 95 }; 96 97 main_gpio_intr: interrupt-controller@a00000 { 98 compatible = "ti,sci-intr"; 99 reg = <0x00 0x00a00000 0x00 0x800>; 100 ti,intr-trigger-type = <1>; 101 interrupt-controller; 102 interrupt-parent = <&gic500>; 103 #interrupt-cells = <1>; 104 ti,sci = <&dmsc>; 105 ti,sci-dev-id = <131>; 106 ti,interrupt-ranges = <8 392 56>; 107 }; 108 109 main_navss: bus@30000000 { 110 compatible = "simple-mfd"; 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 114 dma-coherent; 115 dma-ranges; 116 117 ti,sci-dev-id = <199>; 118 119 main_navss_intr: interrupt-controller@310e0000 { 120 compatible = "ti,sci-intr"; 121 reg = <0x0 0x310e0000 0x0 0x4000>; 122 ti,intr-trigger-type = <4>; 123 interrupt-controller; 124 interrupt-parent = <&gic500>; 125 #interrupt-cells = <1>; 126 ti,sci = <&dmsc>; 127 ti,sci-dev-id = <213>; 128 ti,interrupt-ranges = <0 64 64>, 129 <64 448 64>, 130 <128 672 64>; 131 }; 132 133 main_udmass_inta: interrupt-controller@33d00000 { 134 compatible = "ti,sci-inta"; 135 reg = <0x0 0x33d00000 0x0 0x100000>; 136 interrupt-controller; 137 interrupt-parent = <&main_navss_intr>; 138 msi-controller; 139 #interrupt-cells = <0>; 140 ti,sci = <&dmsc>; 141 ti,sci-dev-id = <209>; 142 ti,interrupt-ranges = <0 0 256>; 143 }; 144 145 secure_proxy_main: mailbox@32c00000 { 146 compatible = "ti,am654-secure-proxy"; 147 #mbox-cells = <1>; 148 reg-names = "target_data", "rt", "scfg"; 149 reg = <0x00 0x32c00000 0x00 0x100000>, 150 <0x00 0x32400000 0x00 0x100000>, 151 <0x00 0x32800000 0x00 0x100000>; 152 interrupt-names = "rx_011"; 153 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 smmu0: iommu@36600000 { 157 compatible = "arm,smmu-v3"; 158 reg = <0x0 0x36600000 0x0 0x100000>; 159 interrupt-parent = <&gic500>; 160 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 161 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 162 interrupt-names = "eventq", "gerror"; 163 #iommu-cells = <1>; 164 }; 165 166 hwspinlock: spinlock@30e00000 { 167 compatible = "ti,am654-hwspinlock"; 168 reg = <0x00 0x30e00000 0x00 0x1000>; 169 #hwlock-cells = <1>; 170 }; 171 172 mailbox0_cluster0: mailbox@31f80000 { 173 compatible = "ti,am654-mailbox"; 174 reg = <0x00 0x31f80000 0x00 0x200>; 175 #mbox-cells = <1>; 176 ti,mbox-num-users = <4>; 177 ti,mbox-num-fifos = <16>; 178 interrupt-parent = <&main_navss_intr>; 179 }; 180 181 mailbox0_cluster1: mailbox@31f81000 { 182 compatible = "ti,am654-mailbox"; 183 reg = <0x00 0x31f81000 0x00 0x200>; 184 #mbox-cells = <1>; 185 ti,mbox-num-users = <4>; 186 ti,mbox-num-fifos = <16>; 187 interrupt-parent = <&main_navss_intr>; 188 }; 189 190 mailbox0_cluster2: mailbox@31f82000 { 191 compatible = "ti,am654-mailbox"; 192 reg = <0x00 0x31f82000 0x00 0x200>; 193 #mbox-cells = <1>; 194 ti,mbox-num-users = <4>; 195 ti,mbox-num-fifos = <16>; 196 interrupt-parent = <&main_navss_intr>; 197 }; 198 199 mailbox0_cluster3: mailbox@31f83000 { 200 compatible = "ti,am654-mailbox"; 201 reg = <0x00 0x31f83000 0x00 0x200>; 202 #mbox-cells = <1>; 203 ti,mbox-num-users = <4>; 204 ti,mbox-num-fifos = <16>; 205 interrupt-parent = <&main_navss_intr>; 206 }; 207 208 mailbox0_cluster4: mailbox@31f84000 { 209 compatible = "ti,am654-mailbox"; 210 reg = <0x00 0x31f84000 0x00 0x200>; 211 #mbox-cells = <1>; 212 ti,mbox-num-users = <4>; 213 ti,mbox-num-fifos = <16>; 214 interrupt-parent = <&main_navss_intr>; 215 }; 216 217 mailbox0_cluster5: mailbox@31f85000 { 218 compatible = "ti,am654-mailbox"; 219 reg = <0x00 0x31f85000 0x00 0x200>; 220 #mbox-cells = <1>; 221 ti,mbox-num-users = <4>; 222 ti,mbox-num-fifos = <16>; 223 interrupt-parent = <&main_navss_intr>; 224 }; 225 226 mailbox0_cluster6: mailbox@31f86000 { 227 compatible = "ti,am654-mailbox"; 228 reg = <0x00 0x31f86000 0x00 0x200>; 229 #mbox-cells = <1>; 230 ti,mbox-num-users = <4>; 231 ti,mbox-num-fifos = <16>; 232 interrupt-parent = <&main_navss_intr>; 233 }; 234 235 mailbox0_cluster7: mailbox@31f87000 { 236 compatible = "ti,am654-mailbox"; 237 reg = <0x00 0x31f87000 0x00 0x200>; 238 #mbox-cells = <1>; 239 ti,mbox-num-users = <4>; 240 ti,mbox-num-fifos = <16>; 241 interrupt-parent = <&main_navss_intr>; 242 }; 243 244 mailbox0_cluster8: mailbox@31f88000 { 245 compatible = "ti,am654-mailbox"; 246 reg = <0x00 0x31f88000 0x00 0x200>; 247 #mbox-cells = <1>; 248 ti,mbox-num-users = <4>; 249 ti,mbox-num-fifos = <16>; 250 interrupt-parent = <&main_navss_intr>; 251 }; 252 253 mailbox0_cluster9: mailbox@31f89000 { 254 compatible = "ti,am654-mailbox"; 255 reg = <0x00 0x31f89000 0x00 0x200>; 256 #mbox-cells = <1>; 257 ti,mbox-num-users = <4>; 258 ti,mbox-num-fifos = <16>; 259 interrupt-parent = <&main_navss_intr>; 260 }; 261 262 mailbox0_cluster10: mailbox@31f8a000 { 263 compatible = "ti,am654-mailbox"; 264 reg = <0x00 0x31f8a000 0x00 0x200>; 265 #mbox-cells = <1>; 266 ti,mbox-num-users = <4>; 267 ti,mbox-num-fifos = <16>; 268 interrupt-parent = <&main_navss_intr>; 269 }; 270 271 mailbox0_cluster11: mailbox@31f8b000 { 272 compatible = "ti,am654-mailbox"; 273 reg = <0x00 0x31f8b000 0x00 0x200>; 274 #mbox-cells = <1>; 275 ti,mbox-num-users = <4>; 276 ti,mbox-num-fifos = <16>; 277 interrupt-parent = <&main_navss_intr>; 278 }; 279 280 main_ringacc: ringacc@3c000000 { 281 compatible = "ti,am654-navss-ringacc"; 282 reg = <0x0 0x3c000000 0x0 0x400000>, 283 <0x0 0x38000000 0x0 0x400000>, 284 <0x0 0x31120000 0x0 0x100>, 285 <0x0 0x33000000 0x0 0x40000>; 286 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 287 ti,num-rings = <1024>; 288 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 289 ti,sci = <&dmsc>; 290 ti,sci-dev-id = <211>; 291 msi-parent = <&main_udmass_inta>; 292 }; 293 294 main_udmap: dma-controller@31150000 { 295 compatible = "ti,j721e-navss-main-udmap"; 296 reg = <0x0 0x31150000 0x0 0x100>, 297 <0x0 0x34000000 0x0 0x100000>, 298 <0x0 0x35000000 0x0 0x100000>; 299 reg-names = "gcfg", "rchanrt", "tchanrt"; 300 msi-parent = <&main_udmass_inta>; 301 #dma-cells = <1>; 302 303 ti,sci = <&dmsc>; 304 ti,sci-dev-id = <212>; 305 ti,ringacc = <&main_ringacc>; 306 307 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 308 <0x0f>, /* TX_HCHAN */ 309 <0x10>; /* TX_UHCHAN */ 310 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 311 <0x0b>, /* RX_HCHAN */ 312 <0x0c>; /* RX_UHCHAN */ 313 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 314 }; 315 316 cpts@310d0000 { 317 compatible = "ti,j721e-cpts"; 318 reg = <0x0 0x310d0000 0x0 0x400>; 319 reg-names = "cpts"; 320 clocks = <&k3_clks 201 1>; 321 clock-names = "cpts"; 322 interrupts-extended = <&main_navss_intr 391>; 323 interrupt-names = "cpts"; 324 ti,cpts-periodic-outputs = <6>; 325 ti,cpts-ext-ts-inputs = <8>; 326 }; 327 }; 328 329 main_crypto: crypto@4e00000 { 330 compatible = "ti,j721e-sa2ul"; 331 reg = <0x0 0x4e00000 0x0 0x1200>; 332 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 333 #address-cells = <2>; 334 #size-cells = <2>; 335 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 336 337 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 338 <&main_udmap 0x4001>; 339 dma-names = "tx", "rx1", "rx2"; 340 341 rng: rng@4e10000 { 342 compatible = "inside-secure,safexcel-eip76"; 343 reg = <0x0 0x4e10000 0x0 0x7d>; 344 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&k3_clks 264 2>; 346 }; 347 }; 348 349 main_pmx0: pinctrl@11c000 { 350 compatible = "pinctrl-single"; 351 /* Proxy 0 addressing */ 352 reg = <0x0 0x11c000 0x0 0x2b4>; 353 #pinctrl-cells = <1>; 354 pinctrl-single,register-width = <32>; 355 pinctrl-single,function-mask = <0xffffffff>; 356 }; 357 358 serdes_wiz0: wiz@5000000 { 359 compatible = "ti,j721e-wiz-16g"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 364 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 365 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 366 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 367 num-lanes = <2>; 368 #reset-cells = <1>; 369 ranges = <0x5000000 0x0 0x5000000 0x10000>; 370 371 wiz0_pll0_refclk: pll0-refclk { 372 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 373 #clock-cells = <0>; 374 assigned-clocks = <&wiz0_pll0_refclk>; 375 assigned-clock-parents = <&k3_clks 292 11>; 376 }; 377 378 wiz0_pll1_refclk: pll1-refclk { 379 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 380 #clock-cells = <0>; 381 assigned-clocks = <&wiz0_pll1_refclk>; 382 assigned-clock-parents = <&k3_clks 292 0>; 383 }; 384 385 wiz0_refclk_dig: refclk-dig { 386 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 387 #clock-cells = <0>; 388 assigned-clocks = <&wiz0_refclk_dig>; 389 assigned-clock-parents = <&k3_clks 292 11>; 390 }; 391 392 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 393 clocks = <&wiz0_refclk_dig>; 394 #clock-cells = <0>; 395 }; 396 397 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 398 clocks = <&wiz0_pll1_refclk>; 399 #clock-cells = <0>; 400 }; 401 402 serdes0: serdes@5000000 { 403 compatible = "ti,sierra-phy-t0"; 404 reg-names = "serdes"; 405 reg = <0x5000000 0x10000>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 #clock-cells = <1>; 409 resets = <&serdes_wiz0 0>; 410 reset-names = "sierra_reset"; 411 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 412 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 413 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 414 "pll0_refclk", "pll1_refclk"; 415 }; 416 }; 417 418 serdes_wiz1: wiz@5010000 { 419 compatible = "ti,j721e-wiz-16g"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 424 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 425 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 426 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 427 num-lanes = <2>; 428 #reset-cells = <1>; 429 ranges = <0x5010000 0x0 0x5010000 0x10000>; 430 431 wiz1_pll0_refclk: pll0-refclk { 432 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 433 #clock-cells = <0>; 434 assigned-clocks = <&wiz1_pll0_refclk>; 435 assigned-clock-parents = <&k3_clks 293 13>; 436 }; 437 438 wiz1_pll1_refclk: pll1-refclk { 439 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 440 #clock-cells = <0>; 441 assigned-clocks = <&wiz1_pll1_refclk>; 442 assigned-clock-parents = <&k3_clks 293 0>; 443 }; 444 445 wiz1_refclk_dig: refclk-dig { 446 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 447 #clock-cells = <0>; 448 assigned-clocks = <&wiz1_refclk_dig>; 449 assigned-clock-parents = <&k3_clks 293 13>; 450 }; 451 452 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 453 clocks = <&wiz1_refclk_dig>; 454 #clock-cells = <0>; 455 }; 456 457 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 458 clocks = <&wiz1_pll1_refclk>; 459 #clock-cells = <0>; 460 }; 461 462 serdes1: serdes@5010000 { 463 compatible = "ti,sierra-phy-t0"; 464 reg-names = "serdes"; 465 reg = <0x5010000 0x10000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 #clock-cells = <1>; 469 resets = <&serdes_wiz1 0>; 470 reset-names = "sierra_reset"; 471 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 472 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 473 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 474 "pll0_refclk", "pll1_refclk"; 475 }; 476 }; 477 478 serdes_wiz2: wiz@5020000 { 479 compatible = "ti,j721e-wiz-16g"; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 483 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 484 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 485 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 486 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 487 num-lanes = <2>; 488 #reset-cells = <1>; 489 ranges = <0x5020000 0x0 0x5020000 0x10000>; 490 491 wiz2_pll0_refclk: pll0-refclk { 492 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 493 #clock-cells = <0>; 494 assigned-clocks = <&wiz2_pll0_refclk>; 495 assigned-clock-parents = <&k3_clks 294 11>; 496 }; 497 498 wiz2_pll1_refclk: pll1-refclk { 499 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 500 #clock-cells = <0>; 501 assigned-clocks = <&wiz2_pll1_refclk>; 502 assigned-clock-parents = <&k3_clks 294 0>; 503 }; 504 505 wiz2_refclk_dig: refclk-dig { 506 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 507 #clock-cells = <0>; 508 assigned-clocks = <&wiz2_refclk_dig>; 509 assigned-clock-parents = <&k3_clks 294 11>; 510 }; 511 512 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 513 clocks = <&wiz2_refclk_dig>; 514 #clock-cells = <0>; 515 }; 516 517 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 518 clocks = <&wiz2_pll1_refclk>; 519 #clock-cells = <0>; 520 }; 521 522 serdes2: serdes@5020000 { 523 compatible = "ti,sierra-phy-t0"; 524 reg-names = "serdes"; 525 reg = <0x5020000 0x10000>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 #clock-cells = <1>; 529 resets = <&serdes_wiz2 0>; 530 reset-names = "sierra_reset"; 531 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 532 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 533 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 534 "pll0_refclk", "pll1_refclk"; 535 }; 536 }; 537 538 serdes_wiz3: wiz@5030000 { 539 compatible = "ti,j721e-wiz-16g"; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 543 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 544 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 545 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 546 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 547 num-lanes = <2>; 548 #reset-cells = <1>; 549 ranges = <0x5030000 0x0 0x5030000 0x10000>; 550 551 wiz3_pll0_refclk: pll0-refclk { 552 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 553 #clock-cells = <0>; 554 assigned-clocks = <&wiz3_pll0_refclk>; 555 assigned-clock-parents = <&k3_clks 295 9>; 556 }; 557 558 wiz3_pll1_refclk: pll1-refclk { 559 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 560 #clock-cells = <0>; 561 assigned-clocks = <&wiz3_pll1_refclk>; 562 assigned-clock-parents = <&k3_clks 295 0>; 563 }; 564 565 wiz3_refclk_dig: refclk-dig { 566 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 567 #clock-cells = <0>; 568 assigned-clocks = <&wiz3_refclk_dig>; 569 assigned-clock-parents = <&k3_clks 295 9>; 570 }; 571 572 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 573 clocks = <&wiz3_refclk_dig>; 574 #clock-cells = <0>; 575 }; 576 577 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 578 clocks = <&wiz3_pll1_refclk>; 579 #clock-cells = <0>; 580 }; 581 582 serdes3: serdes@5030000 { 583 compatible = "ti,sierra-phy-t0"; 584 reg-names = "serdes"; 585 reg = <0x5030000 0x10000>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 #clock-cells = <1>; 589 resets = <&serdes_wiz3 0>; 590 reset-names = "sierra_reset"; 591 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 592 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 593 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 594 "pll0_refclk", "pll1_refclk"; 595 }; 596 }; 597 598 pcie0_rc: pcie@2900000 { 599 compatible = "ti,j721e-pcie-host"; 600 reg = <0x00 0x02900000 0x00 0x1000>, 601 <0x00 0x02907000 0x00 0x400>, 602 <0x00 0x0d000000 0x00 0x00800000>, 603 <0x00 0x10000000 0x00 0x00001000>; 604 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 605 interrupt-names = "link_state"; 606 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 607 device_type = "pci"; 608 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 609 max-link-speed = <3>; 610 num-lanes = <2>; 611 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 612 clocks = <&k3_clks 239 1>; 613 clock-names = "fck"; 614 #address-cells = <3>; 615 #size-cells = <2>; 616 bus-range = <0x0 0xff>; 617 vendor-id = <0x104c>; 618 device-id = <0xb00d>; 619 msi-map = <0x0 &gic_its 0x0 0x10000>; 620 dma-coherent; 621 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 622 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 623 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 624 }; 625 626 pcie0_ep: pcie-ep@2900000 { 627 compatible = "ti,j721e-pcie-ep"; 628 reg = <0x00 0x02900000 0x00 0x1000>, 629 <0x00 0x02907000 0x00 0x400>, 630 <0x00 0x0d000000 0x00 0x00800000>, 631 <0x00 0x10000000 0x00 0x08000000>; 632 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 633 interrupt-names = "link_state"; 634 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 635 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 636 max-link-speed = <3>; 637 num-lanes = <2>; 638 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 639 clocks = <&k3_clks 239 1>; 640 clock-names = "fck"; 641 max-functions = /bits/ 8 <6>; 642 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 643 dma-coherent; 644 }; 645 646 pcie1_rc: pcie@2910000 { 647 compatible = "ti,j721e-pcie-host"; 648 reg = <0x00 0x02910000 0x00 0x1000>, 649 <0x00 0x02917000 0x00 0x400>, 650 <0x00 0x0d800000 0x00 0x00800000>, 651 <0x00 0x18000000 0x00 0x00001000>; 652 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 653 interrupt-names = "link_state"; 654 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 655 device_type = "pci"; 656 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 657 max-link-speed = <3>; 658 num-lanes = <2>; 659 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 660 clocks = <&k3_clks 240 1>; 661 clock-names = "fck"; 662 #address-cells = <3>; 663 #size-cells = <2>; 664 bus-range = <0x0 0xff>; 665 vendor-id = <0x104c>; 666 device-id = <0xb00d>; 667 msi-map = <0x0 &gic_its 0x10000 0x10000>; 668 dma-coherent; 669 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 670 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 671 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 672 }; 673 674 pcie1_ep: pcie-ep@2910000 { 675 compatible = "ti,j721e-pcie-ep"; 676 reg = <0x00 0x02910000 0x00 0x1000>, 677 <0x00 0x02917000 0x00 0x400>, 678 <0x00 0x0d800000 0x00 0x00800000>, 679 <0x00 0x18000000 0x00 0x08000000>; 680 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 681 interrupt-names = "link_state"; 682 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 683 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 684 max-link-speed = <3>; 685 num-lanes = <2>; 686 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 687 clocks = <&k3_clks 240 1>; 688 clock-names = "fck"; 689 max-functions = /bits/ 8 <6>; 690 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 691 dma-coherent; 692 }; 693 694 pcie2_rc: pcie@2920000 { 695 compatible = "ti,j721e-pcie-host"; 696 reg = <0x00 0x02920000 0x00 0x1000>, 697 <0x00 0x02927000 0x00 0x400>, 698 <0x00 0x0e000000 0x00 0x00800000>, 699 <0x44 0x00000000 0x00 0x00001000>; 700 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 701 interrupt-names = "link_state"; 702 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 703 device_type = "pci"; 704 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 705 max-link-speed = <3>; 706 num-lanes = <2>; 707 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 708 clocks = <&k3_clks 241 1>; 709 clock-names = "fck"; 710 #address-cells = <3>; 711 #size-cells = <2>; 712 bus-range = <0x0 0xff>; 713 vendor-id = <0x104c>; 714 device-id = <0xb00d>; 715 msi-map = <0x0 &gic_its 0x20000 0x10000>; 716 dma-coherent; 717 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 718 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 719 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 720 }; 721 722 pcie2_ep: pcie-ep@2920000 { 723 compatible = "ti,j721e-pcie-ep"; 724 reg = <0x00 0x02920000 0x00 0x1000>, 725 <0x00 0x02927000 0x00 0x400>, 726 <0x00 0x0e000000 0x00 0x00800000>, 727 <0x44 0x00000000 0x00 0x08000000>; 728 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 729 interrupt-names = "link_state"; 730 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 731 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 732 max-link-speed = <3>; 733 num-lanes = <2>; 734 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 735 clocks = <&k3_clks 241 1>; 736 clock-names = "fck"; 737 max-functions = /bits/ 8 <6>; 738 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 739 dma-coherent; 740 }; 741 742 pcie3_rc: pcie@2930000 { 743 compatible = "ti,j721e-pcie-host"; 744 reg = <0x00 0x02930000 0x00 0x1000>, 745 <0x00 0x02937000 0x00 0x400>, 746 <0x00 0x0e800000 0x00 0x00800000>, 747 <0x44 0x10000000 0x00 0x00001000>; 748 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 749 interrupt-names = "link_state"; 750 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 751 device_type = "pci"; 752 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 753 max-link-speed = <3>; 754 num-lanes = <2>; 755 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 756 clocks = <&k3_clks 242 1>; 757 clock-names = "fck"; 758 #address-cells = <3>; 759 #size-cells = <2>; 760 bus-range = <0x0 0xff>; 761 vendor-id = <0x104c>; 762 device-id = <0xb00d>; 763 msi-map = <0x0 &gic_its 0x30000 0x10000>; 764 dma-coherent; 765 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 766 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 767 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 768 }; 769 770 pcie3_ep: pcie-ep@2930000 { 771 compatible = "ti,j721e-pcie-ep"; 772 reg = <0x00 0x02930000 0x00 0x1000>, 773 <0x00 0x02937000 0x00 0x400>, 774 <0x00 0x0e800000 0x00 0x00800000>, 775 <0x44 0x10000000 0x00 0x08000000>; 776 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 777 interrupt-names = "link_state"; 778 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 779 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 780 max-link-speed = <3>; 781 num-lanes = <2>; 782 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 783 clocks = <&k3_clks 242 1>; 784 clock-names = "fck"; 785 max-functions = /bits/ 8 <6>; 786 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 787 dma-coherent; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 }; 791 792 serdes_wiz4: wiz@5050000 { 793 compatible = "ti,am64-wiz-10g"; 794 #address-cells = <1>; 795 #size-cells = <1>; 796 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 797 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 798 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 799 assigned-clocks = <&k3_clks 297 9>; 800 assigned-clock-parents = <&k3_clks 297 10>; 801 assigned-clock-rates = <19200000>; 802 num-lanes = <4>; 803 #reset-cells = <1>; 804 #clock-cells = <1>; 805 ranges = <0x05050000 0x00 0x05050000 0x010000>, 806 <0x0a030a00 0x00 0x0a030a00 0x40>; 807 808 serdes4: serdes@5050000 { 809 /* 810 * Note: we also map DPTX PHY registers as the Torrent 811 * needs to manage those. 812 */ 813 compatible = "ti,j721e-serdes-10g"; 814 reg = <0x05050000 0x010000>, 815 <0x0a030a00 0x40>; /* DPTX PHY */ 816 reg-names = "torrent_phy", "dptx_phy"; 817 818 resets = <&serdes_wiz4 0>; 819 reset-names = "torrent_reset"; 820 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 821 clock-names = "refclk"; 822 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 823 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 824 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 825 assigned-clock-parents = <&k3_clks 297 9>, 826 <&k3_clks 297 9>, 827 <&k3_clks 297 9>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 }; 831 }; 832 833 main_uart0: serial@2800000 { 834 compatible = "ti,j721e-uart", "ti,am654-uart"; 835 reg = <0x00 0x02800000 0x00 0x100>; 836 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 837 clock-frequency = <48000000>; 838 current-speed = <115200>; 839 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 840 clocks = <&k3_clks 146 0>; 841 clock-names = "fclk"; 842 }; 843 844 main_uart1: serial@2810000 { 845 compatible = "ti,j721e-uart", "ti,am654-uart"; 846 reg = <0x00 0x02810000 0x00 0x100>; 847 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 848 clock-frequency = <48000000>; 849 current-speed = <115200>; 850 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 851 clocks = <&k3_clks 278 0>; 852 clock-names = "fclk"; 853 }; 854 855 main_uart2: serial@2820000 { 856 compatible = "ti,j721e-uart", "ti,am654-uart"; 857 reg = <0x00 0x02820000 0x00 0x100>; 858 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 859 clock-frequency = <48000000>; 860 current-speed = <115200>; 861 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 862 clocks = <&k3_clks 279 0>; 863 clock-names = "fclk"; 864 }; 865 866 main_uart3: serial@2830000 { 867 compatible = "ti,j721e-uart", "ti,am654-uart"; 868 reg = <0x00 0x02830000 0x00 0x100>; 869 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 870 clock-frequency = <48000000>; 871 current-speed = <115200>; 872 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 280 0>; 874 clock-names = "fclk"; 875 }; 876 877 main_uart4: serial@2840000 { 878 compatible = "ti,j721e-uart", "ti,am654-uart"; 879 reg = <0x00 0x02840000 0x00 0x100>; 880 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 881 clock-frequency = <48000000>; 882 current-speed = <115200>; 883 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&k3_clks 281 0>; 885 clock-names = "fclk"; 886 }; 887 888 main_uart5: serial@2850000 { 889 compatible = "ti,j721e-uart", "ti,am654-uart"; 890 reg = <0x00 0x02850000 0x00 0x100>; 891 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 892 clock-frequency = <48000000>; 893 current-speed = <115200>; 894 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 895 clocks = <&k3_clks 282 0>; 896 clock-names = "fclk"; 897 }; 898 899 main_uart6: serial@2860000 { 900 compatible = "ti,j721e-uart", "ti,am654-uart"; 901 reg = <0x00 0x02860000 0x00 0x100>; 902 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 903 clock-frequency = <48000000>; 904 current-speed = <115200>; 905 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 906 clocks = <&k3_clks 283 0>; 907 clock-names = "fclk"; 908 }; 909 910 main_uart7: serial@2870000 { 911 compatible = "ti,j721e-uart", "ti,am654-uart"; 912 reg = <0x00 0x02870000 0x00 0x100>; 913 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 914 clock-frequency = <48000000>; 915 current-speed = <115200>; 916 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 917 clocks = <&k3_clks 284 0>; 918 clock-names = "fclk"; 919 }; 920 921 main_uart8: serial@2880000 { 922 compatible = "ti,j721e-uart", "ti,am654-uart"; 923 reg = <0x00 0x02880000 0x00 0x100>; 924 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 925 clock-frequency = <48000000>; 926 current-speed = <115200>; 927 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 928 clocks = <&k3_clks 285 0>; 929 clock-names = "fclk"; 930 }; 931 932 main_uart9: serial@2890000 { 933 compatible = "ti,j721e-uart", "ti,am654-uart"; 934 reg = <0x00 0x02890000 0x00 0x100>; 935 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 936 clock-frequency = <48000000>; 937 current-speed = <115200>; 938 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 939 clocks = <&k3_clks 286 0>; 940 clock-names = "fclk"; 941 }; 942 943 main_gpio0: gpio@600000 { 944 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 945 reg = <0x0 0x00600000 0x0 0x100>; 946 gpio-controller; 947 #gpio-cells = <2>; 948 interrupt-parent = <&main_gpio_intr>; 949 interrupts = <256>, <257>, <258>, <259>, 950 <260>, <261>, <262>, <263>; 951 interrupt-controller; 952 #interrupt-cells = <2>; 953 ti,ngpio = <128>; 954 ti,davinci-gpio-unbanked = <0>; 955 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 956 clocks = <&k3_clks 105 0>; 957 clock-names = "gpio"; 958 }; 959 960 main_gpio1: gpio@601000 { 961 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 962 reg = <0x0 0x00601000 0x0 0x100>; 963 gpio-controller; 964 #gpio-cells = <2>; 965 interrupt-parent = <&main_gpio_intr>; 966 interrupts = <288>, <289>, <290>; 967 interrupt-controller; 968 #interrupt-cells = <2>; 969 ti,ngpio = <36>; 970 ti,davinci-gpio-unbanked = <0>; 971 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 972 clocks = <&k3_clks 106 0>; 973 clock-names = "gpio"; 974 }; 975 976 main_gpio2: gpio@610000 { 977 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 978 reg = <0x0 0x00610000 0x0 0x100>; 979 gpio-controller; 980 #gpio-cells = <2>; 981 interrupt-parent = <&main_gpio_intr>; 982 interrupts = <264>, <265>, <266>, <267>, 983 <268>, <269>, <270>, <271>; 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 ti,ngpio = <128>; 987 ti,davinci-gpio-unbanked = <0>; 988 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 989 clocks = <&k3_clks 107 0>; 990 clock-names = "gpio"; 991 }; 992 993 main_gpio3: gpio@611000 { 994 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 995 reg = <0x0 0x00611000 0x0 0x100>; 996 gpio-controller; 997 #gpio-cells = <2>; 998 interrupt-parent = <&main_gpio_intr>; 999 interrupts = <292>, <293>, <294>; 1000 interrupt-controller; 1001 #interrupt-cells = <2>; 1002 ti,ngpio = <36>; 1003 ti,davinci-gpio-unbanked = <0>; 1004 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1005 clocks = <&k3_clks 108 0>; 1006 clock-names = "gpio"; 1007 }; 1008 1009 main_gpio4: gpio@620000 { 1010 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1011 reg = <0x0 0x00620000 0x0 0x100>; 1012 gpio-controller; 1013 #gpio-cells = <2>; 1014 interrupt-parent = <&main_gpio_intr>; 1015 interrupts = <272>, <273>, <274>, <275>, 1016 <276>, <277>, <278>, <279>; 1017 interrupt-controller; 1018 #interrupt-cells = <2>; 1019 ti,ngpio = <128>; 1020 ti,davinci-gpio-unbanked = <0>; 1021 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1022 clocks = <&k3_clks 109 0>; 1023 clock-names = "gpio"; 1024 }; 1025 1026 main_gpio5: gpio@621000 { 1027 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1028 reg = <0x0 0x00621000 0x0 0x100>; 1029 gpio-controller; 1030 #gpio-cells = <2>; 1031 interrupt-parent = <&main_gpio_intr>; 1032 interrupts = <296>, <297>, <298>; 1033 interrupt-controller; 1034 #interrupt-cells = <2>; 1035 ti,ngpio = <36>; 1036 ti,davinci-gpio-unbanked = <0>; 1037 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1038 clocks = <&k3_clks 110 0>; 1039 clock-names = "gpio"; 1040 }; 1041 1042 main_gpio6: gpio@630000 { 1043 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1044 reg = <0x0 0x00630000 0x0 0x100>; 1045 gpio-controller; 1046 #gpio-cells = <2>; 1047 interrupt-parent = <&main_gpio_intr>; 1048 interrupts = <280>, <281>, <282>, <283>, 1049 <284>, <285>, <286>, <287>; 1050 interrupt-controller; 1051 #interrupt-cells = <2>; 1052 ti,ngpio = <128>; 1053 ti,davinci-gpio-unbanked = <0>; 1054 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1055 clocks = <&k3_clks 111 0>; 1056 clock-names = "gpio"; 1057 }; 1058 1059 main_gpio7: gpio@631000 { 1060 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1061 reg = <0x0 0x00631000 0x0 0x100>; 1062 gpio-controller; 1063 #gpio-cells = <2>; 1064 interrupt-parent = <&main_gpio_intr>; 1065 interrupts = <300>, <301>, <302>; 1066 interrupt-controller; 1067 #interrupt-cells = <2>; 1068 ti,ngpio = <36>; 1069 ti,davinci-gpio-unbanked = <0>; 1070 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1071 clocks = <&k3_clks 112 0>; 1072 clock-names = "gpio"; 1073 }; 1074 1075 main_sdhci0: mmc@4f80000 { 1076 compatible = "ti,j721e-sdhci-8bit"; 1077 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1078 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1079 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1080 clock-names = "clk_ahb", "clk_xin"; 1081 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1082 assigned-clocks = <&k3_clks 91 1>; 1083 assigned-clock-parents = <&k3_clks 91 2>; 1084 bus-width = <8>; 1085 mmc-hs200-1_8v; 1086 mmc-ddr-1_8v; 1087 ti,otap-del-sel-legacy = <0xf>; 1088 ti,otap-del-sel-mmc-hs = <0xf>; 1089 ti,otap-del-sel-ddr52 = <0x5>; 1090 ti,otap-del-sel-hs200 = <0x6>; 1091 ti,otap-del-sel-hs400 = <0x0>; 1092 ti,itap-del-sel-legacy = <0x10>; 1093 ti,itap-del-sel-mmc-hs = <0xa>; 1094 ti,itap-del-sel-ddr52 = <0x3>; 1095 ti,trm-icp = <0x8>; 1096 ti,strobe-sel = <0x77>; 1097 dma-coherent; 1098 }; 1099 1100 main_sdhci1: mmc@4fb0000 { 1101 compatible = "ti,j721e-sdhci-4bit"; 1102 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1103 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1105 clock-names = "clk_ahb", "clk_xin"; 1106 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1107 assigned-clocks = <&k3_clks 92 0>; 1108 assigned-clock-parents = <&k3_clks 92 1>; 1109 ti,otap-del-sel-legacy = <0x0>; 1110 ti,otap-del-sel-sd-hs = <0xf>; 1111 ti,otap-del-sel-sdr12 = <0xf>; 1112 ti,otap-del-sel-sdr25 = <0xf>; 1113 ti,otap-del-sel-sdr50 = <0xc>; 1114 ti,otap-del-sel-ddr50 = <0xc>; 1115 ti,itap-del-sel-legacy = <0x0>; 1116 ti,itap-del-sel-sd-hs = <0x0>; 1117 ti,itap-del-sel-sdr12 = <0x0>; 1118 ti,itap-del-sel-sdr25 = <0x0>; 1119 ti,itap-del-sel-ddr50 = <0x2>; 1120 ti,trm-icp = <0x8>; 1121 ti,clkbuf-sel = <0x7>; 1122 dma-coherent; 1123 sdhci-caps-mask = <0x2 0x0>; 1124 }; 1125 1126 main_sdhci2: mmc@4f98000 { 1127 compatible = "ti,j721e-sdhci-4bit"; 1128 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1129 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1130 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1131 clock-names = "clk_ahb", "clk_xin"; 1132 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1133 assigned-clocks = <&k3_clks 93 0>; 1134 assigned-clock-parents = <&k3_clks 93 1>; 1135 ti,otap-del-sel-legacy = <0x0>; 1136 ti,otap-del-sel-sd-hs = <0xf>; 1137 ti,otap-del-sel-sdr12 = <0xf>; 1138 ti,otap-del-sel-sdr25 = <0xf>; 1139 ti,otap-del-sel-sdr50 = <0xc>; 1140 ti,otap-del-sel-ddr50 = <0xc>; 1141 ti,itap-del-sel-legacy = <0x0>; 1142 ti,itap-del-sel-sd-hs = <0x0>; 1143 ti,itap-del-sel-sdr12 = <0x0>; 1144 ti,itap-del-sel-sdr25 = <0x0>; 1145 ti,itap-del-sel-ddr50 = <0x2>; 1146 ti,trm-icp = <0x8>; 1147 ti,clkbuf-sel = <0x7>; 1148 dma-coherent; 1149 sdhci-caps-mask = <0x2 0x0>; 1150 }; 1151 1152 usbss0: cdns-usb@4104000 { 1153 compatible = "ti,j721e-usb"; 1154 reg = <0x00 0x4104000 0x00 0x100>; 1155 dma-coherent; 1156 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1157 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1158 clock-names = "ref", "lpm"; 1159 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1160 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1161 #address-cells = <2>; 1162 #size-cells = <2>; 1163 ranges; 1164 1165 usb0: usb@6000000 { 1166 compatible = "cdns,usb3"; 1167 reg = <0x00 0x6000000 0x00 0x10000>, 1168 <0x00 0x6010000 0x00 0x10000>, 1169 <0x00 0x6020000 0x00 0x10000>; 1170 reg-names = "otg", "xhci", "dev"; 1171 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1172 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1173 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1174 interrupt-names = "host", 1175 "peripheral", 1176 "otg"; 1177 maximum-speed = "super-speed"; 1178 dr_mode = "otg"; 1179 }; 1180 }; 1181 1182 usbss1: cdns-usb@4114000 { 1183 compatible = "ti,j721e-usb"; 1184 reg = <0x00 0x4114000 0x00 0x100>; 1185 dma-coherent; 1186 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1187 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1188 clock-names = "ref", "lpm"; 1189 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1190 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges; 1194 1195 usb1: usb@6400000 { 1196 compatible = "cdns,usb3"; 1197 reg = <0x00 0x6400000 0x00 0x10000>, 1198 <0x00 0x6410000 0x00 0x10000>, 1199 <0x00 0x6420000 0x00 0x10000>; 1200 reg-names = "otg", "xhci", "dev"; 1201 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1202 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1203 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1204 interrupt-names = "host", 1205 "peripheral", 1206 "otg"; 1207 maximum-speed = "super-speed"; 1208 dr_mode = "otg"; 1209 }; 1210 }; 1211 1212 main_i2c0: i2c@2000000 { 1213 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1214 reg = <0x0 0x2000000 0x0 0x100>; 1215 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 clock-names = "fck"; 1219 clocks = <&k3_clks 187 0>; 1220 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1221 }; 1222 1223 main_i2c1: i2c@2010000 { 1224 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1225 reg = <0x0 0x2010000 0x0 0x100>; 1226 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 clock-names = "fck"; 1230 clocks = <&k3_clks 188 0>; 1231 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1232 }; 1233 1234 main_i2c2: i2c@2020000 { 1235 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1236 reg = <0x0 0x2020000 0x0 0x100>; 1237 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 clock-names = "fck"; 1241 clocks = <&k3_clks 189 0>; 1242 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1243 }; 1244 1245 main_i2c3: i2c@2030000 { 1246 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1247 reg = <0x0 0x2030000 0x0 0x100>; 1248 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 clock-names = "fck"; 1252 clocks = <&k3_clks 190 0>; 1253 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1254 }; 1255 1256 main_i2c4: i2c@2040000 { 1257 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1258 reg = <0x0 0x2040000 0x0 0x100>; 1259 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 clock-names = "fck"; 1263 clocks = <&k3_clks 191 0>; 1264 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1265 }; 1266 1267 main_i2c5: i2c@2050000 { 1268 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1269 reg = <0x0 0x2050000 0x0 0x100>; 1270 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 clock-names = "fck"; 1274 clocks = <&k3_clks 192 0>; 1275 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1276 }; 1277 1278 main_i2c6: i2c@2060000 { 1279 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1280 reg = <0x0 0x2060000 0x0 0x100>; 1281 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 clock-names = "fck"; 1285 clocks = <&k3_clks 193 0>; 1286 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1287 }; 1288 1289 ufs_wrapper: ufs-wrapper@4e80000 { 1290 compatible = "ti,j721e-ufs"; 1291 reg = <0x0 0x4e80000 0x0 0x100>; 1292 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1293 clocks = <&k3_clks 277 1>; 1294 assigned-clocks = <&k3_clks 277 1>; 1295 assigned-clock-parents = <&k3_clks 277 4>; 1296 ranges; 1297 #address-cells = <2>; 1298 #size-cells = <2>; 1299 1300 ufs@4e84000 { 1301 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1302 reg = <0x0 0x4e84000 0x0 0x10000>; 1303 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1304 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1305 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1306 clock-names = "core_clk", "phy_clk", "ref_clk"; 1307 dma-coherent; 1308 }; 1309 }; 1310 1311 mhdp: dp-bridge@a000000 { 1312 compatible = "ti,j721e-mhdp8546"; 1313 /* 1314 * Note: we do not map DPTX PHY area, as that is handled by 1315 * the PHY driver. 1316 */ 1317 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1318 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1319 reg-names = "mhdptx", "j721e-intg"; 1320 1321 clocks = <&k3_clks 151 36>; 1322 1323 interrupt-parent = <&gic500>; 1324 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1325 1326 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1327 1328 dp0_ports: ports { 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 1332 port@0 { 1333 reg = <0>; 1334 }; 1335 1336 port@4 { 1337 reg = <4>; 1338 }; 1339 }; 1340 }; 1341 1342 dss: dss@4a00000 { 1343 compatible = "ti,j721e-dss"; 1344 reg = 1345 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1346 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1347 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1348 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1349 1350 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1351 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1352 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1353 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1354 1355 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1356 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1357 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1358 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1359 1360 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1361 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1362 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1363 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1364 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1365 1366 reg-names = "common_m", "common_s0", 1367 "common_s1", "common_s2", 1368 "vidl1", "vidl2","vid1","vid2", 1369 "ovr1", "ovr2", "ovr3", "ovr4", 1370 "vp1", "vp2", "vp3", "vp4", 1371 "wb"; 1372 1373 clocks = <&k3_clks 152 0>, 1374 <&k3_clks 152 1>, 1375 <&k3_clks 152 4>, 1376 <&k3_clks 152 9>, 1377 <&k3_clks 152 13>; 1378 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1379 1380 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1381 1382 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "common_m", 1387 "common_s0", 1388 "common_s1", 1389 "common_s2"; 1390 1391 dss_ports: ports { 1392 }; 1393 }; 1394 1395 mcasp0: mcasp@2b00000 { 1396 compatible = "ti,am33xx-mcasp-audio"; 1397 reg = <0x0 0x02b00000 0x0 0x2000>, 1398 <0x0 0x02b08000 0x0 0x1000>; 1399 reg-names = "mpu","dat"; 1400 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1402 interrupt-names = "tx", "rx"; 1403 1404 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1405 dma-names = "tx", "rx"; 1406 1407 clocks = <&k3_clks 174 1>; 1408 clock-names = "fck"; 1409 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1410 }; 1411 1412 mcasp1: mcasp@2b10000 { 1413 compatible = "ti,am33xx-mcasp-audio"; 1414 reg = <0x0 0x02b10000 0x0 0x2000>, 1415 <0x0 0x02b18000 0x0 0x1000>; 1416 reg-names = "mpu","dat"; 1417 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1419 interrupt-names = "tx", "rx"; 1420 1421 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1422 dma-names = "tx", "rx"; 1423 1424 clocks = <&k3_clks 175 1>; 1425 clock-names = "fck"; 1426 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1427 }; 1428 1429 mcasp2: mcasp@2b20000 { 1430 compatible = "ti,am33xx-mcasp-audio"; 1431 reg = <0x0 0x02b20000 0x0 0x2000>, 1432 <0x0 0x02b28000 0x0 0x1000>; 1433 reg-names = "mpu","dat"; 1434 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1436 interrupt-names = "tx", "rx"; 1437 1438 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1439 dma-names = "tx", "rx"; 1440 1441 clocks = <&k3_clks 176 1>; 1442 clock-names = "fck"; 1443 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1444 }; 1445 1446 mcasp3: mcasp@2b30000 { 1447 compatible = "ti,am33xx-mcasp-audio"; 1448 reg = <0x0 0x02b30000 0x0 0x2000>, 1449 <0x0 0x02b38000 0x0 0x1000>; 1450 reg-names = "mpu","dat"; 1451 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1453 interrupt-names = "tx", "rx"; 1454 1455 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1456 dma-names = "tx", "rx"; 1457 1458 clocks = <&k3_clks 177 1>; 1459 clock-names = "fck"; 1460 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1461 }; 1462 1463 mcasp4: mcasp@2b40000 { 1464 compatible = "ti,am33xx-mcasp-audio"; 1465 reg = <0x0 0x02b40000 0x0 0x2000>, 1466 <0x0 0x02b48000 0x0 0x1000>; 1467 reg-names = "mpu","dat"; 1468 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1470 interrupt-names = "tx", "rx"; 1471 1472 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1473 dma-names = "tx", "rx"; 1474 1475 clocks = <&k3_clks 178 1>; 1476 clock-names = "fck"; 1477 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1478 }; 1479 1480 mcasp5: mcasp@2b50000 { 1481 compatible = "ti,am33xx-mcasp-audio"; 1482 reg = <0x0 0x02b50000 0x0 0x2000>, 1483 <0x0 0x02b58000 0x0 0x1000>; 1484 reg-names = "mpu","dat"; 1485 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1487 interrupt-names = "tx", "rx"; 1488 1489 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1490 dma-names = "tx", "rx"; 1491 1492 clocks = <&k3_clks 179 1>; 1493 clock-names = "fck"; 1494 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1495 }; 1496 1497 mcasp6: mcasp@2b60000 { 1498 compatible = "ti,am33xx-mcasp-audio"; 1499 reg = <0x0 0x02b60000 0x0 0x2000>, 1500 <0x0 0x02b68000 0x0 0x1000>; 1501 reg-names = "mpu","dat"; 1502 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1504 interrupt-names = "tx", "rx"; 1505 1506 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1507 dma-names = "tx", "rx"; 1508 1509 clocks = <&k3_clks 180 1>; 1510 clock-names = "fck"; 1511 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1512 }; 1513 1514 mcasp7: mcasp@2b70000 { 1515 compatible = "ti,am33xx-mcasp-audio"; 1516 reg = <0x0 0x02b70000 0x0 0x2000>, 1517 <0x0 0x02b78000 0x0 0x1000>; 1518 reg-names = "mpu","dat"; 1519 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-names = "tx", "rx"; 1522 1523 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1524 dma-names = "tx", "rx"; 1525 1526 clocks = <&k3_clks 181 1>; 1527 clock-names = "fck"; 1528 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1529 }; 1530 1531 mcasp8: mcasp@2b80000 { 1532 compatible = "ti,am33xx-mcasp-audio"; 1533 reg = <0x0 0x02b80000 0x0 0x2000>, 1534 <0x0 0x02b88000 0x0 0x1000>; 1535 reg-names = "mpu","dat"; 1536 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupt-names = "tx", "rx"; 1539 1540 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1541 dma-names = "tx", "rx"; 1542 1543 clocks = <&k3_clks 182 1>; 1544 clock-names = "fck"; 1545 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1546 }; 1547 1548 mcasp9: mcasp@2b90000 { 1549 compatible = "ti,am33xx-mcasp-audio"; 1550 reg = <0x0 0x02b90000 0x0 0x2000>, 1551 <0x0 0x02b98000 0x0 0x1000>; 1552 reg-names = "mpu","dat"; 1553 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "tx", "rx"; 1556 1557 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1558 dma-names = "tx", "rx"; 1559 1560 clocks = <&k3_clks 183 1>; 1561 clock-names = "fck"; 1562 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1563 }; 1564 1565 mcasp10: mcasp@2ba0000 { 1566 compatible = "ti,am33xx-mcasp-audio"; 1567 reg = <0x0 0x02ba0000 0x0 0x2000>, 1568 <0x0 0x02ba8000 0x0 0x1000>; 1569 reg-names = "mpu","dat"; 1570 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1572 interrupt-names = "tx", "rx"; 1573 1574 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1575 dma-names = "tx", "rx"; 1576 1577 clocks = <&k3_clks 184 1>; 1578 clock-names = "fck"; 1579 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1580 }; 1581 1582 mcasp11: mcasp@2bb0000 { 1583 compatible = "ti,am33xx-mcasp-audio"; 1584 reg = <0x0 0x02bb0000 0x0 0x2000>, 1585 <0x0 0x02bb8000 0x0 0x1000>; 1586 reg-names = "mpu","dat"; 1587 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1589 interrupt-names = "tx", "rx"; 1590 1591 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1592 dma-names = "tx", "rx"; 1593 1594 clocks = <&k3_clks 185 1>; 1595 clock-names = "fck"; 1596 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1597 }; 1598 1599 watchdog0: watchdog@2200000 { 1600 compatible = "ti,j7-rti-wdt"; 1601 reg = <0x0 0x2200000 0x0 0x100>; 1602 clocks = <&k3_clks 252 1>; 1603 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1604 assigned-clocks = <&k3_clks 252 1>; 1605 assigned-clock-parents = <&k3_clks 252 5>; 1606 }; 1607 1608 watchdog1: watchdog@2210000 { 1609 compatible = "ti,j7-rti-wdt"; 1610 reg = <0x0 0x2210000 0x0 0x100>; 1611 clocks = <&k3_clks 253 1>; 1612 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1613 assigned-clocks = <&k3_clks 253 1>; 1614 assigned-clock-parents = <&k3_clks 253 5>; 1615 }; 1616 1617 main_r5fss0: r5fss@5c00000 { 1618 compatible = "ti,j721e-r5fss"; 1619 ti,cluster-mode = <1>; 1620 #address-cells = <1>; 1621 #size-cells = <1>; 1622 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1623 <0x5d00000 0x00 0x5d00000 0x20000>; 1624 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1625 1626 main_r5fss0_core0: r5f@5c00000 { 1627 compatible = "ti,j721e-r5f"; 1628 reg = <0x5c00000 0x00008000>, 1629 <0x5c10000 0x00008000>; 1630 reg-names = "atcm", "btcm"; 1631 ti,sci = <&dmsc>; 1632 ti,sci-dev-id = <245>; 1633 ti,sci-proc-ids = <0x06 0xff>; 1634 resets = <&k3_reset 245 1>; 1635 firmware-name = "j7-main-r5f0_0-fw"; 1636 ti,atcm-enable = <1>; 1637 ti,btcm-enable = <1>; 1638 ti,loczrama = <1>; 1639 }; 1640 1641 main_r5fss0_core1: r5f@5d00000 { 1642 compatible = "ti,j721e-r5f"; 1643 reg = <0x5d00000 0x00008000>, 1644 <0x5d10000 0x00008000>; 1645 reg-names = "atcm", "btcm"; 1646 ti,sci = <&dmsc>; 1647 ti,sci-dev-id = <246>; 1648 ti,sci-proc-ids = <0x07 0xff>; 1649 resets = <&k3_reset 246 1>; 1650 firmware-name = "j7-main-r5f0_1-fw"; 1651 ti,atcm-enable = <1>; 1652 ti,btcm-enable = <1>; 1653 ti,loczrama = <1>; 1654 }; 1655 }; 1656 1657 main_r5fss1: r5fss@5e00000 { 1658 compatible = "ti,j721e-r5fss"; 1659 ti,cluster-mode = <1>; 1660 #address-cells = <1>; 1661 #size-cells = <1>; 1662 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1663 <0x5f00000 0x00 0x5f00000 0x20000>; 1664 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1665 1666 main_r5fss1_core0: r5f@5e00000 { 1667 compatible = "ti,j721e-r5f"; 1668 reg = <0x5e00000 0x00008000>, 1669 <0x5e10000 0x00008000>; 1670 reg-names = "atcm", "btcm"; 1671 ti,sci = <&dmsc>; 1672 ti,sci-dev-id = <247>; 1673 ti,sci-proc-ids = <0x08 0xff>; 1674 resets = <&k3_reset 247 1>; 1675 firmware-name = "j7-main-r5f1_0-fw"; 1676 ti,atcm-enable = <1>; 1677 ti,btcm-enable = <1>; 1678 ti,loczrama = <1>; 1679 }; 1680 1681 main_r5fss1_core1: r5f@5f00000 { 1682 compatible = "ti,j721e-r5f"; 1683 reg = <0x5f00000 0x00008000>, 1684 <0x5f10000 0x00008000>; 1685 reg-names = "atcm", "btcm"; 1686 ti,sci = <&dmsc>; 1687 ti,sci-dev-id = <248>; 1688 ti,sci-proc-ids = <0x09 0xff>; 1689 resets = <&k3_reset 248 1>; 1690 firmware-name = "j7-main-r5f1_1-fw"; 1691 ti,atcm-enable = <1>; 1692 ti,btcm-enable = <1>; 1693 ti,loczrama = <1>; 1694 }; 1695 }; 1696 1697 c66_0: dsp@4d80800000 { 1698 compatible = "ti,j721e-c66-dsp"; 1699 reg = <0x4d 0x80800000 0x00 0x00048000>, 1700 <0x4d 0x80e00000 0x00 0x00008000>, 1701 <0x4d 0x80f00000 0x00 0x00008000>; 1702 reg-names = "l2sram", "l1pram", "l1dram"; 1703 ti,sci = <&dmsc>; 1704 ti,sci-dev-id = <142>; 1705 ti,sci-proc-ids = <0x03 0xff>; 1706 resets = <&k3_reset 142 1>; 1707 firmware-name = "j7-c66_0-fw"; 1708 }; 1709 1710 c66_1: dsp@4d81800000 { 1711 compatible = "ti,j721e-c66-dsp"; 1712 reg = <0x4d 0x81800000 0x00 0x00048000>, 1713 <0x4d 0x81e00000 0x00 0x00008000>, 1714 <0x4d 0x81f00000 0x00 0x00008000>; 1715 reg-names = "l2sram", "l1pram", "l1dram"; 1716 ti,sci = <&dmsc>; 1717 ti,sci-dev-id = <143>; 1718 ti,sci-proc-ids = <0x04 0xff>; 1719 resets = <&k3_reset 143 1>; 1720 firmware-name = "j7-c66_1-fw"; 1721 }; 1722 1723 c71_0: dsp@64800000 { 1724 compatible = "ti,j721e-c71-dsp"; 1725 reg = <0x00 0x64800000 0x00 0x00080000>, 1726 <0x00 0x64e00000 0x00 0x0000c000>; 1727 reg-names = "l2sram", "l1dram"; 1728 ti,sci = <&dmsc>; 1729 ti,sci-dev-id = <15>; 1730 ti,sci-proc-ids = <0x30 0xff>; 1731 resets = <&k3_reset 15 1>; 1732 firmware-name = "j7-c71_0-fw"; 1733 }; 1734 1735 icssg0: icssg@b000000 { 1736 compatible = "ti,j721e-icssg"; 1737 reg = <0x00 0xb000000 0x00 0x80000>; 1738 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1739 #address-cells = <1>; 1740 #size-cells = <1>; 1741 ranges = <0x0 0x00 0x0b000000 0x100000>; 1742 1743 icssg0_mem: memories@0 { 1744 reg = <0x0 0x2000>, 1745 <0x2000 0x2000>, 1746 <0x10000 0x10000>; 1747 reg-names = "dram0", "dram1", 1748 "shrdram2"; 1749 }; 1750 1751 icssg0_cfg: cfg@26000 { 1752 compatible = "ti,pruss-cfg", "syscon"; 1753 reg = <0x26000 0x200>; 1754 #address-cells = <1>; 1755 #size-cells = <1>; 1756 ranges = <0x0 0x26000 0x2000>; 1757 1758 clocks { 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 1762 icssg0_coreclk_mux: coreclk-mux@3c { 1763 reg = <0x3c>; 1764 #clock-cells = <0>; 1765 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1766 <&k3_clks 119 1>; /* icssg0_iclk */ 1767 assigned-clocks = <&icssg0_coreclk_mux>; 1768 assigned-clock-parents = <&k3_clks 119 1>; 1769 }; 1770 1771 icssg0_iepclk_mux: iepclk-mux@30 { 1772 reg = <0x30>; 1773 #clock-cells = <0>; 1774 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1775 <&icssg0_coreclk_mux>; /* core_clk */ 1776 assigned-clocks = <&icssg0_iepclk_mux>; 1777 assigned-clock-parents = <&icssg0_coreclk_mux>; 1778 }; 1779 }; 1780 }; 1781 1782 icssg0_mii_rt: mii-rt@32000 { 1783 compatible = "ti,pruss-mii", "syscon"; 1784 reg = <0x32000 0x100>; 1785 }; 1786 1787 icssg0_mii_g_rt: mii-g-rt@33000 { 1788 compatible = "ti,pruss-mii-g", "syscon"; 1789 reg = <0x33000 0x1000>; 1790 }; 1791 1792 icssg0_intc: interrupt-controller@20000 { 1793 compatible = "ti,icssg-intc"; 1794 reg = <0x20000 0x2000>; 1795 interrupt-controller; 1796 #interrupt-cells = <3>; 1797 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1805 interrupt-names = "host_intr0", "host_intr1", 1806 "host_intr2", "host_intr3", 1807 "host_intr4", "host_intr5", 1808 "host_intr6", "host_intr7"; 1809 }; 1810 1811 pru0_0: pru@34000 { 1812 compatible = "ti,j721e-pru"; 1813 reg = <0x34000 0x3000>, 1814 <0x22000 0x100>, 1815 <0x22400 0x100>; 1816 reg-names = "iram", "control", "debug"; 1817 firmware-name = "j7-pru0_0-fw"; 1818 }; 1819 1820 rtu0_0: rtu@4000 { 1821 compatible = "ti,j721e-rtu"; 1822 reg = <0x4000 0x2000>, 1823 <0x23000 0x100>, 1824 <0x23400 0x100>; 1825 reg-names = "iram", "control", "debug"; 1826 firmware-name = "j7-rtu0_0-fw"; 1827 }; 1828 1829 tx_pru0_0: txpru@a000 { 1830 compatible = "ti,j721e-tx-pru"; 1831 reg = <0xa000 0x1800>, 1832 <0x25000 0x100>, 1833 <0x25400 0x100>; 1834 reg-names = "iram", "control", "debug"; 1835 firmware-name = "j7-txpru0_0-fw"; 1836 }; 1837 1838 pru0_1: pru@38000 { 1839 compatible = "ti,j721e-pru"; 1840 reg = <0x38000 0x3000>, 1841 <0x24000 0x100>, 1842 <0x24400 0x100>; 1843 reg-names = "iram", "control", "debug"; 1844 firmware-name = "j7-pru0_1-fw"; 1845 }; 1846 1847 rtu0_1: rtu@6000 { 1848 compatible = "ti,j721e-rtu"; 1849 reg = <0x6000 0x2000>, 1850 <0x23800 0x100>, 1851 <0x23c00 0x100>; 1852 reg-names = "iram", "control", "debug"; 1853 firmware-name = "j7-rtu0_1-fw"; 1854 }; 1855 1856 tx_pru0_1: txpru@c000 { 1857 compatible = "ti,j721e-tx-pru"; 1858 reg = <0xc000 0x1800>, 1859 <0x25800 0x100>, 1860 <0x25c00 0x100>; 1861 reg-names = "iram", "control", "debug"; 1862 firmware-name = "j7-txpru0_1-fw"; 1863 }; 1864 1865 icssg0_mdio: mdio@32400 { 1866 compatible = "ti,davinci_mdio"; 1867 reg = <0x32400 0x100>; 1868 clocks = <&k3_clks 119 1>; 1869 clock-names = "fck"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 bus_freq = <1000000>; 1873 }; 1874 }; 1875 1876 icssg1: icssg@b100000 { 1877 compatible = "ti,j721e-icssg"; 1878 reg = <0x00 0xb100000 0x00 0x80000>; 1879 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 1880 #address-cells = <1>; 1881 #size-cells = <1>; 1882 ranges = <0x0 0x00 0x0b100000 0x100000>; 1883 1884 icssg1_mem: memories@b100000 { 1885 reg = <0x0 0x2000>, 1886 <0x2000 0x2000>, 1887 <0x10000 0x10000>; 1888 reg-names = "dram0", "dram1", 1889 "shrdram2"; 1890 }; 1891 1892 icssg1_cfg: cfg@26000 { 1893 compatible = "ti,pruss-cfg", "syscon"; 1894 reg = <0x26000 0x200>; 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 ranges = <0x0 0x26000 0x2000>; 1898 1899 clocks { 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 1903 icssg1_coreclk_mux: coreclk-mux@3c { 1904 reg = <0x3c>; 1905 #clock-cells = <0>; 1906 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 1907 <&k3_clks 120 4>; /* icssg1_iclk */ 1908 assigned-clocks = <&icssg1_coreclk_mux>; 1909 assigned-clock-parents = <&k3_clks 120 4>; 1910 }; 1911 1912 icssg1_iepclk_mux: iepclk-mux@30 { 1913 reg = <0x30>; 1914 #clock-cells = <0>; 1915 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 1916 <&icssg1_coreclk_mux>; /* core_clk */ 1917 assigned-clocks = <&icssg1_iepclk_mux>; 1918 assigned-clock-parents = <&icssg1_coreclk_mux>; 1919 }; 1920 }; 1921 }; 1922 1923 icssg1_mii_rt: mii-rt@32000 { 1924 compatible = "ti,pruss-mii", "syscon"; 1925 reg = <0x32000 0x100>; 1926 }; 1927 1928 icssg1_mii_g_rt: mii-g-rt@33000 { 1929 compatible = "ti,pruss-mii-g", "syscon"; 1930 reg = <0x33000 0x1000>; 1931 }; 1932 1933 icssg1_intc: interrupt-controller@20000 { 1934 compatible = "ti,icssg-intc"; 1935 reg = <0x20000 0x2000>; 1936 interrupt-controller; 1937 #interrupt-cells = <3>; 1938 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1946 interrupt-names = "host_intr0", "host_intr1", 1947 "host_intr2", "host_intr3", 1948 "host_intr4", "host_intr5", 1949 "host_intr6", "host_intr7"; 1950 }; 1951 1952 pru1_0: pru@34000 { 1953 compatible = "ti,j721e-pru"; 1954 reg = <0x34000 0x4000>, 1955 <0x22000 0x100>, 1956 <0x22400 0x100>; 1957 reg-names = "iram", "control", "debug"; 1958 firmware-name = "j7-pru1_0-fw"; 1959 }; 1960 1961 rtu1_0: rtu@4000 { 1962 compatible = "ti,j721e-rtu"; 1963 reg = <0x4000 0x2000>, 1964 <0x23000 0x100>, 1965 <0x23400 0x100>; 1966 reg-names = "iram", "control", "debug"; 1967 firmware-name = "j7-rtu1_0-fw"; 1968 }; 1969 1970 tx_pru1_0: txpru@a000 { 1971 compatible = "ti,j721e-tx-pru"; 1972 reg = <0xa000 0x1800>, 1973 <0x25000 0x100>, 1974 <0x25400 0x100>; 1975 reg-names = "iram", "control", "debug"; 1976 firmware-name = "j7-txpru1_0-fw"; 1977 }; 1978 1979 pru1_1: pru@38000 { 1980 compatible = "ti,j721e-pru"; 1981 reg = <0x38000 0x4000>, 1982 <0x24000 0x100>, 1983 <0x24400 0x100>; 1984 reg-names = "iram", "control", "debug"; 1985 firmware-name = "j7-pru1_1-fw"; 1986 }; 1987 1988 rtu1_1: rtu@6000 { 1989 compatible = "ti,j721e-rtu"; 1990 reg = <0x6000 0x2000>, 1991 <0x23800 0x100>, 1992 <0x23c00 0x100>; 1993 reg-names = "iram", "control", "debug"; 1994 firmware-name = "j7-rtu1_1-fw"; 1995 }; 1996 1997 tx_pru1_1: txpru@c000 { 1998 compatible = "ti,j721e-tx-pru"; 1999 reg = <0xc000 0x1800>, 2000 <0x25800 0x100>, 2001 <0x25c00 0x100>; 2002 reg-names = "iram", "control", "debug"; 2003 firmware-name = "j7-txpru1_1-fw"; 2004 }; 2005 2006 icssg1_mdio: mdio@32400 { 2007 compatible = "ti,davinci_mdio"; 2008 reg = <0x32400 0x100>; 2009 clocks = <&k3_clks 120 4>; 2010 clock-names = "fck"; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 bus_freq = <1000000>; 2014 }; 2015 }; 2016 2017 main_mcan0: can@2701000 { 2018 compatible = "bosch,m_can"; 2019 reg = <0x00 0x02701000 0x00 0x200>, 2020 <0x00 0x02708000 0x00 0x8000>; 2021 reg-names = "m_can", "message_ram"; 2022 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2023 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2024 clock-names = "hclk", "cclk"; 2025 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2027 interrupt-names = "int0", "int1"; 2028 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2029 }; 2030 2031 main_mcan1: can@2711000 { 2032 compatible = "bosch,m_can"; 2033 reg = <0x00 0x02711000 0x00 0x200>, 2034 <0x00 0x02718000 0x00 0x8000>; 2035 reg-names = "m_can", "message_ram"; 2036 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2037 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2038 clock-names = "hclk", "cclk"; 2039 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2041 interrupt-names = "int0", "int1"; 2042 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2043 }; 2044 2045 main_mcan2: can@2721000 { 2046 compatible = "bosch,m_can"; 2047 reg = <0x00 0x02721000 0x00 0x200>, 2048 <0x00 0x02728000 0x00 0x8000>; 2049 reg-names = "m_can", "message_ram"; 2050 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2051 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2052 clock-names = "hclk", "cclk"; 2053 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2055 interrupt-names = "int0", "int1"; 2056 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2057 }; 2058 2059 main_mcan3: can@2731000 { 2060 compatible = "bosch,m_can"; 2061 reg = <0x00 0x02731000 0x00 0x200>, 2062 <0x00 0x02738000 0x00 0x8000>; 2063 reg-names = "m_can", "message_ram"; 2064 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2065 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2066 clock-names = "hclk", "cclk"; 2067 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2069 interrupt-names = "int0", "int1"; 2070 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2071 }; 2072 2073 main_mcan4: can@2741000 { 2074 compatible = "bosch,m_can"; 2075 reg = <0x00 0x02741000 0x00 0x200>, 2076 <0x00 0x02748000 0x00 0x8000>; 2077 reg-names = "m_can", "message_ram"; 2078 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2079 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2080 clock-names = "hclk", "cclk"; 2081 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2083 interrupt-names = "int0", "int1"; 2084 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2085 }; 2086 2087 main_mcan5: can@2751000 { 2088 compatible = "bosch,m_can"; 2089 reg = <0x00 0x02751000 0x00 0x200>, 2090 <0x00 0x02758000 0x00 0x8000>; 2091 reg-names = "m_can", "message_ram"; 2092 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2093 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2094 clock-names = "hclk", "cclk"; 2095 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "int0", "int1"; 2098 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2099 }; 2100 2101 main_mcan6: can@2761000 { 2102 compatible = "bosch,m_can"; 2103 reg = <0x00 0x02761000 0x00 0x200>, 2104 <0x00 0x02768000 0x00 0x8000>; 2105 reg-names = "m_can", "message_ram"; 2106 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2107 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2108 clock-names = "hclk", "cclk"; 2109 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2111 interrupt-names = "int0", "int1"; 2112 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2113 }; 2114 2115 main_mcan7: can@2771000 { 2116 compatible = "bosch,m_can"; 2117 reg = <0x00 0x02771000 0x00 0x200>, 2118 <0x00 0x02778000 0x00 0x8000>; 2119 reg-names = "m_can", "message_ram"; 2120 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2121 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2122 clock-names = "hclk", "cclk"; 2123 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2125 interrupt-names = "int0", "int1"; 2126 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2127 }; 2128 2129 main_mcan8: can@2781000 { 2130 compatible = "bosch,m_can"; 2131 reg = <0x00 0x02781000 0x00 0x200>, 2132 <0x00 0x02788000 0x00 0x8000>; 2133 reg-names = "m_can", "message_ram"; 2134 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2135 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2136 clock-names = "hclk", "cclk"; 2137 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2139 interrupt-names = "int0", "int1"; 2140 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2141 }; 2142 2143 main_mcan9: can@2791000 { 2144 compatible = "bosch,m_can"; 2145 reg = <0x00 0x02791000 0x00 0x200>, 2146 <0x00 0x02798000 0x00 0x8000>; 2147 reg-names = "m_can", "message_ram"; 2148 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2149 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2150 clock-names = "hclk", "cclk"; 2151 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2153 interrupt-names = "int0", "int1"; 2154 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2155 }; 2156 2157 main_mcan10: can@27a1000 { 2158 compatible = "bosch,m_can"; 2159 reg = <0x00 0x027a1000 0x00 0x200>, 2160 <0x00 0x027a8000 0x00 0x8000>; 2161 reg-names = "m_can", "message_ram"; 2162 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2163 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2164 clock-names = "hclk", "cclk"; 2165 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2167 interrupt-names = "int0", "int1"; 2168 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2169 }; 2170 2171 main_mcan11: can@27b1000 { 2172 compatible = "bosch,m_can"; 2173 reg = <0x00 0x027b1000 0x00 0x200>, 2174 <0x00 0x027b8000 0x00 0x8000>; 2175 reg-names = "m_can", "message_ram"; 2176 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2177 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2178 clock-names = "hclk", "cclk"; 2179 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2181 interrupt-names = "int0", "int1"; 2182 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2183 }; 2184 2185 main_mcan12: can@27c1000 { 2186 compatible = "bosch,m_can"; 2187 reg = <0x00 0x027c1000 0x00 0x200>, 2188 <0x00 0x027c8000 0x00 0x8000>; 2189 reg-names = "m_can", "message_ram"; 2190 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2191 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2192 clock-names = "hclk", "cclk"; 2193 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2195 interrupt-names = "int0", "int1"; 2196 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2197 }; 2198 2199 main_mcan13: can@27d1000 { 2200 compatible = "bosch,m_can"; 2201 reg = <0x00 0x027d1000 0x00 0x200>, 2202 <0x00 0x027d8000 0x00 0x8000>; 2203 reg-names = "m_can", "message_ram"; 2204 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2205 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2206 clock-names = "hclk", "cclk"; 2207 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2209 interrupt-names = "int0", "int1"; 2210 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2211 }; 2212}; 2213