1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 cbb-noc@2300000 { 92 compatible = "nvidia,tegra194-cbb-noc"; 93 reg = <0x02300000 0x1000>; 94 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96 nvidia,axi2apb = <&axi2apb>; 97 nvidia,apbmisc = <&apbmisc>; 98 status = "okay"; 99 }; 100 101 axi2apb: axi2apb@2390000 { 102 compatible = "nvidia,tegra194-axi2apb"; 103 reg = <0x2390000 0x1000>, 104 <0x23a0000 0x1000>, 105 <0x23b0000 0x1000>, 106 <0x23c0000 0x1000>, 107 <0x23d0000 0x1000>, 108 <0x23e0000 0x1000>; 109 status = "okay"; 110 }; 111 112 ethernet@2490000 { 113 compatible = "nvidia,tegra194-eqos", 114 "nvidia,tegra186-eqos", 115 "snps,dwc-qos-ethernet-4.10"; 116 reg = <0x02490000 0x10000>; 117 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119 <&bpmp TEGRA194_CLK_EQOS_AXI>, 120 <&bpmp TEGRA194_CLK_EQOS_RX>, 121 <&bpmp TEGRA194_CLK_EQOS_TX>, 122 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124 resets = <&bpmp TEGRA194_RESET_EQOS>; 125 reset-names = "eqos"; 126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128 interconnect-names = "dma-mem", "write"; 129 iommus = <&smmu TEGRA194_SID_EQOS>; 130 status = "disabled"; 131 132 snps,write-requests = <1>; 133 snps,read-requests = <3>; 134 snps,burst-map = <0x7>; 135 snps,txpbl = <16>; 136 snps,rxpbl = <8>; 137 }; 138 139 gpcdma: dma-controller@2600000 { 140 compatible = "nvidia,tegra194-gpcdma", 141 "nvidia,tegra186-gpcdma"; 142 reg = <0x2600000 0x210000>; 143 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144 reset-names = "gpcdma"; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178 dma-coherent; 179 status = "okay"; 180 }; 181 182 aconnect@2900000 { 183 compatible = "nvidia,tegra194-aconnect", 184 "nvidia,tegra210-aconnect"; 185 clocks = <&bpmp TEGRA194_CLK_APE>, 186 <&bpmp TEGRA194_CLK_APB2APE>; 187 clock-names = "ape", "apb2ape"; 188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x02900000 0x02900000 0x200000>; 192 status = "disabled"; 193 194 adma: dma-controller@2930000 { 195 compatible = "nvidia,tegra194-adma", 196 "nvidia,tegra186-adma"; 197 reg = <0x02930000 0x20000>; 198 interrupt-parent = <&agic>; 199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 231 #dma-cells = <1>; 232 clocks = <&bpmp TEGRA194_CLK_AHUB>; 233 clock-names = "d_audio"; 234 status = "disabled"; 235 }; 236 237 agic: interrupt-controller@2a40000 { 238 compatible = "nvidia,tegra194-agic", 239 "nvidia,tegra210-agic"; 240 #interrupt-cells = <3>; 241 interrupt-controller; 242 reg = <0x02a41000 0x1000>, 243 <0x02a42000 0x2000>; 244 interrupts = <GIC_SPI 145 245 (GIC_CPU_MASK_SIMPLE(4) | 246 IRQ_TYPE_LEVEL_HIGH)>; 247 clocks = <&bpmp TEGRA194_CLK_APE>; 248 clock-names = "clk"; 249 status = "disabled"; 250 }; 251 252 tegra_ahub: ahub@2900800 { 253 compatible = "nvidia,tegra194-ahub", 254 "nvidia,tegra186-ahub"; 255 reg = <0x02900800 0x800>; 256 clocks = <&bpmp TEGRA194_CLK_AHUB>; 257 clock-names = "ahub"; 258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x02900800 0x02900800 0x11800>; 263 status = "disabled"; 264 265 tegra_admaif: admaif@290f000 { 266 compatible = "nvidia,tegra194-admaif", 267 "nvidia,tegra186-admaif"; 268 reg = <0x0290f000 0x1000>; 269 dmas = <&adma 1>, <&adma 1>, 270 <&adma 2>, <&adma 2>, 271 <&adma 3>, <&adma 3>, 272 <&adma 4>, <&adma 4>, 273 <&adma 5>, <&adma 5>, 274 <&adma 6>, <&adma 6>, 275 <&adma 7>, <&adma 7>, 276 <&adma 8>, <&adma 8>, 277 <&adma 9>, <&adma 9>, 278 <&adma 10>, <&adma 10>, 279 <&adma 11>, <&adma 11>, 280 <&adma 12>, <&adma 12>, 281 <&adma 13>, <&adma 13>, 282 <&adma 14>, <&adma 14>, 283 <&adma 15>, <&adma 15>, 284 <&adma 16>, <&adma 16>, 285 <&adma 17>, <&adma 17>, 286 <&adma 18>, <&adma 18>, 287 <&adma 19>, <&adma 19>, 288 <&adma 20>, <&adma 20>; 289 dma-names = "rx1", "tx1", 290 "rx2", "tx2", 291 "rx3", "tx3", 292 "rx4", "tx4", 293 "rx5", "tx5", 294 "rx6", "tx6", 295 "rx7", "tx7", 296 "rx8", "tx8", 297 "rx9", "tx9", 298 "rx10", "tx10", 299 "rx11", "tx11", 300 "rx12", "tx12", 301 "rx13", "tx13", 302 "rx14", "tx14", 303 "rx15", "tx15", 304 "rx16", "tx16", 305 "rx17", "tx17", 306 "rx18", "tx18", 307 "rx19", "tx19", 308 "rx20", "tx20"; 309 status = "disabled"; 310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312 interconnect-names = "dma-mem", "write"; 313 iommus = <&smmu TEGRA194_SID_APE>; 314 }; 315 316 tegra_i2s1: i2s@2901000 { 317 compatible = "nvidia,tegra194-i2s", 318 "nvidia,tegra210-i2s"; 319 reg = <0x2901000 0x100>; 320 clocks = <&bpmp TEGRA194_CLK_I2S1>, 321 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322 clock-names = "i2s", "sync_input"; 323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325 assigned-clock-rates = <1536000>; 326 sound-name-prefix = "I2S1"; 327 status = "disabled"; 328 }; 329 330 tegra_i2s2: i2s@2901100 { 331 compatible = "nvidia,tegra194-i2s", 332 "nvidia,tegra210-i2s"; 333 reg = <0x2901100 0x100>; 334 clocks = <&bpmp TEGRA194_CLK_I2S2>, 335 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336 clock-names = "i2s", "sync_input"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <1536000>; 340 sound-name-prefix = "I2S2"; 341 status = "disabled"; 342 }; 343 344 tegra_i2s3: i2s@2901200 { 345 compatible = "nvidia,tegra194-i2s", 346 "nvidia,tegra210-i2s"; 347 reg = <0x2901200 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_I2S3>, 349 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350 clock-names = "i2s", "sync_input"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <1536000>; 354 sound-name-prefix = "I2S3"; 355 status = "disabled"; 356 }; 357 358 tegra_i2s4: i2s@2901300 { 359 compatible = "nvidia,tegra194-i2s", 360 "nvidia,tegra210-i2s"; 361 reg = <0x2901300 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_I2S4>, 363 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364 clock-names = "i2s", "sync_input"; 365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367 assigned-clock-rates = <1536000>; 368 sound-name-prefix = "I2S4"; 369 status = "disabled"; 370 }; 371 372 tegra_i2s5: i2s@2901400 { 373 compatible = "nvidia,tegra194-i2s", 374 "nvidia,tegra210-i2s"; 375 reg = <0x2901400 0x100>; 376 clocks = <&bpmp TEGRA194_CLK_I2S5>, 377 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378 clock-names = "i2s", "sync_input"; 379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381 assigned-clock-rates = <1536000>; 382 sound-name-prefix = "I2S5"; 383 status = "disabled"; 384 }; 385 386 tegra_i2s6: i2s@2901500 { 387 compatible = "nvidia,tegra194-i2s", 388 "nvidia,tegra210-i2s"; 389 reg = <0x2901500 0x100>; 390 clocks = <&bpmp TEGRA194_CLK_I2S6>, 391 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392 clock-names = "i2s", "sync_input"; 393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395 assigned-clock-rates = <1536000>; 396 sound-name-prefix = "I2S6"; 397 status = "disabled"; 398 }; 399 400 tegra_dmic1: dmic@2904000 { 401 compatible = "nvidia,tegra194-dmic", 402 "nvidia,tegra210-dmic"; 403 reg = <0x2904000 0x100>; 404 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405 clock-names = "dmic"; 406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408 assigned-clock-rates = <3072000>; 409 sound-name-prefix = "DMIC1"; 410 status = "disabled"; 411 }; 412 413 tegra_dmic2: dmic@2904100 { 414 compatible = "nvidia,tegra194-dmic", 415 "nvidia,tegra210-dmic"; 416 reg = <0x2904100 0x100>; 417 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418 clock-names = "dmic"; 419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421 assigned-clock-rates = <3072000>; 422 sound-name-prefix = "DMIC2"; 423 status = "disabled"; 424 }; 425 426 tegra_dmic3: dmic@2904200 { 427 compatible = "nvidia,tegra194-dmic", 428 "nvidia,tegra210-dmic"; 429 reg = <0x2904200 0x100>; 430 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431 clock-names = "dmic"; 432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434 assigned-clock-rates = <3072000>; 435 sound-name-prefix = "DMIC3"; 436 status = "disabled"; 437 }; 438 439 tegra_dmic4: dmic@2904300 { 440 compatible = "nvidia,tegra194-dmic", 441 "nvidia,tegra210-dmic"; 442 reg = <0x2904300 0x100>; 443 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444 clock-names = "dmic"; 445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447 assigned-clock-rates = <3072000>; 448 sound-name-prefix = "DMIC4"; 449 status = "disabled"; 450 }; 451 452 tegra_dspk1: dspk@2905000 { 453 compatible = "nvidia,tegra194-dspk", 454 "nvidia,tegra186-dspk"; 455 reg = <0x2905000 0x100>; 456 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457 clock-names = "dspk"; 458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460 assigned-clock-rates = <12288000>; 461 sound-name-prefix = "DSPK1"; 462 status = "disabled"; 463 }; 464 465 tegra_dspk2: dspk@2905100 { 466 compatible = "nvidia,tegra194-dspk", 467 "nvidia,tegra186-dspk"; 468 reg = <0x2905100 0x100>; 469 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470 clock-names = "dspk"; 471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473 assigned-clock-rates = <12288000>; 474 sound-name-prefix = "DSPK2"; 475 status = "disabled"; 476 }; 477 478 tegra_sfc1: sfc@2902000 { 479 compatible = "nvidia,tegra194-sfc", 480 "nvidia,tegra210-sfc"; 481 reg = <0x2902000 0x200>; 482 sound-name-prefix = "SFC1"; 483 status = "disabled"; 484 }; 485 486 tegra_sfc2: sfc@2902200 { 487 compatible = "nvidia,tegra194-sfc", 488 "nvidia,tegra210-sfc"; 489 reg = <0x2902200 0x200>; 490 sound-name-prefix = "SFC2"; 491 status = "disabled"; 492 }; 493 494 tegra_sfc3: sfc@2902400 { 495 compatible = "nvidia,tegra194-sfc", 496 "nvidia,tegra210-sfc"; 497 reg = <0x2902400 0x200>; 498 sound-name-prefix = "SFC3"; 499 status = "disabled"; 500 }; 501 502 tegra_sfc4: sfc@2902600 { 503 compatible = "nvidia,tegra194-sfc", 504 "nvidia,tegra210-sfc"; 505 reg = <0x2902600 0x200>; 506 sound-name-prefix = "SFC4"; 507 status = "disabled"; 508 }; 509 510 tegra_mvc1: mvc@290a000 { 511 compatible = "nvidia,tegra194-mvc", 512 "nvidia,tegra210-mvc"; 513 reg = <0x290a000 0x200>; 514 sound-name-prefix = "MVC1"; 515 status = "disabled"; 516 }; 517 518 tegra_mvc2: mvc@290a200 { 519 compatible = "nvidia,tegra194-mvc", 520 "nvidia,tegra210-mvc"; 521 reg = <0x290a200 0x200>; 522 sound-name-prefix = "MVC2"; 523 status = "disabled"; 524 }; 525 526 tegra_amx1: amx@2903000 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903000 0x100>; 529 sound-name-prefix = "AMX1"; 530 status = "disabled"; 531 }; 532 533 tegra_amx2: amx@2903100 { 534 compatible = "nvidia,tegra194-amx"; 535 reg = <0x2903100 0x100>; 536 sound-name-prefix = "AMX2"; 537 status = "disabled"; 538 }; 539 540 tegra_amx3: amx@2903200 { 541 compatible = "nvidia,tegra194-amx"; 542 reg = <0x2903200 0x100>; 543 sound-name-prefix = "AMX3"; 544 status = "disabled"; 545 }; 546 547 tegra_amx4: amx@2903300 { 548 compatible = "nvidia,tegra194-amx"; 549 reg = <0x2903300 0x100>; 550 sound-name-prefix = "AMX4"; 551 status = "disabled"; 552 }; 553 554 tegra_adx1: adx@2903800 { 555 compatible = "nvidia,tegra194-adx", 556 "nvidia,tegra210-adx"; 557 reg = <0x2903800 0x100>; 558 sound-name-prefix = "ADX1"; 559 status = "disabled"; 560 }; 561 562 tegra_adx2: adx@2903900 { 563 compatible = "nvidia,tegra194-adx", 564 "nvidia,tegra210-adx"; 565 reg = <0x2903900 0x100>; 566 sound-name-prefix = "ADX2"; 567 status = "disabled"; 568 }; 569 570 tegra_adx3: adx@2903a00 { 571 compatible = "nvidia,tegra194-adx", 572 "nvidia,tegra210-adx"; 573 reg = <0x2903a00 0x100>; 574 sound-name-prefix = "ADX3"; 575 status = "disabled"; 576 }; 577 578 tegra_adx4: adx@2903b00 { 579 compatible = "nvidia,tegra194-adx", 580 "nvidia,tegra210-adx"; 581 reg = <0x2903b00 0x100>; 582 sound-name-prefix = "ADX4"; 583 status = "disabled"; 584 }; 585 586 tegra_ope1: processing-engine@2908000 { 587 compatible = "nvidia,tegra194-ope", 588 "nvidia,tegra210-ope"; 589 reg = <0x2908000 0x100>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 sound-name-prefix = "OPE1"; 594 status = "disabled"; 595 596 equalizer@2908100 { 597 compatible = "nvidia,tegra194-peq", 598 "nvidia,tegra210-peq"; 599 reg = <0x2908100 0x100>; 600 }; 601 602 dynamic-range-compressor@2908200 { 603 compatible = "nvidia,tegra194-mbdrc", 604 "nvidia,tegra210-mbdrc"; 605 reg = <0x2908200 0x200>; 606 }; 607 }; 608 609 tegra_amixer: amixer@290bb00 { 610 compatible = "nvidia,tegra194-amixer", 611 "nvidia,tegra210-amixer"; 612 reg = <0x290bb00 0x800>; 613 sound-name-prefix = "MIXER1"; 614 status = "disabled"; 615 }; 616 617 tegra_asrc: asrc@2910000 { 618 compatible = "nvidia,tegra194-asrc", 619 "nvidia,tegra186-asrc"; 620 reg = <0x2910000 0x2000>; 621 sound-name-prefix = "ASRC1"; 622 status = "disabled"; 623 }; 624 }; 625 }; 626 627 pinmux: pinmux@2430000 { 628 compatible = "nvidia,tegra194-pinmux"; 629 reg = <0x2430000 0x17000>, 630 <0xc300000 0x4000>; 631 632 status = "okay"; 633 634 pex_rst_c5_out_state: pex_rst_c5_out { 635 pex_rst { 636 nvidia,pins = "pex_l5_rst_n_pgg1"; 637 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640 nvidia,tristate = <TEGRA_PIN_DISABLE>; 641 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642 }; 643 }; 644 645 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646 clkreq { 647 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 650 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651 nvidia,tristate = <TEGRA_PIN_DISABLE>; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 }; 654 }; 655 }; 656 657 mc: memory-controller@2c00000 { 658 compatible = "nvidia,tegra194-mc"; 659 reg = <0x02c00000 0x10000>, /* MC-SID */ 660 <0x02c10000 0x10000>, /* MC Broadcast*/ 661 <0x02c20000 0x10000>, /* MC0 */ 662 <0x02c30000 0x10000>, /* MC1 */ 663 <0x02c40000 0x10000>, /* MC2 */ 664 <0x02c50000 0x10000>, /* MC3 */ 665 <0x02b80000 0x10000>, /* MC4 */ 666 <0x02b90000 0x10000>, /* MC5 */ 667 <0x02ba0000 0x10000>, /* MC6 */ 668 <0x02bb0000 0x10000>, /* MC7 */ 669 <0x01700000 0x10000>, /* MC8 */ 670 <0x01710000 0x10000>, /* MC9 */ 671 <0x01720000 0x10000>, /* MC10 */ 672 <0x01730000 0x10000>, /* MC11 */ 673 <0x01740000 0x10000>, /* MC12 */ 674 <0x01750000 0x10000>, /* MC13 */ 675 <0x01760000 0x10000>, /* MC14 */ 676 <0x01770000 0x10000>; /* MC15 */ 677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679 "ch11", "ch12", "ch13", "ch14", "ch15"; 680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681 #interconnect-cells = <1>; 682 status = "disabled"; 683 684 #address-cells = <2>; 685 #size-cells = <2>; 686 687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690 691 /* 692 * Bit 39 of addresses passing through the memory 693 * controller selects the XBAR format used when memory 694 * is accessed. This is used to transparently access 695 * memory in the XBAR format used by the discrete GPU 696 * (bit 39 set) or Tegra (bit 39 clear). 697 * 698 * As a consequence, the operating system must ensure 699 * that bit 39 is never used implicitly, for example 700 * via an I/O virtual address mapping of an IOMMU. If 701 * devices require access to the XBAR switch, their 702 * drivers must set this bit explicitly. 703 * 704 * Limit the DMA range for memory clients to [38:0]. 705 */ 706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707 708 emc: external-memory-controller@2c60000 { 709 compatible = "nvidia,tegra194-emc"; 710 reg = <0x0 0x02c60000 0x0 0x90000>, 711 <0x0 0x01780000 0x0 0x80000>; 712 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA194_CLK_EMC>; 714 clock-names = "emc"; 715 716 #interconnect-cells = <0>; 717 718 nvidia,bpmp = <&bpmp>; 719 }; 720 }; 721 722 timer@3010000 { 723 compatible = "nvidia,tegra186-timer"; 724 reg = <0x03010000 0x000e0000>; 725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 735 status = "okay"; 736 }; 737 738 uarta: serial@3100000 { 739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 740 reg = <0x03100000 0x40>; 741 reg-shift = <2>; 742 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&bpmp TEGRA194_CLK_UARTA>; 744 clock-names = "serial"; 745 resets = <&bpmp TEGRA194_RESET_UARTA>; 746 reset-names = "serial"; 747 status = "disabled"; 748 }; 749 750 uartb: serial@3110000 { 751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 752 reg = <0x03110000 0x40>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&bpmp TEGRA194_CLK_UARTB>; 756 clock-names = "serial"; 757 resets = <&bpmp TEGRA194_RESET_UARTB>; 758 reset-names = "serial"; 759 status = "disabled"; 760 }; 761 762 uartd: serial@3130000 { 763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 764 reg = <0x03130000 0x40>; 765 reg-shift = <2>; 766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA194_CLK_UARTD>; 768 clock-names = "serial"; 769 resets = <&bpmp TEGRA194_RESET_UARTD>; 770 reset-names = "serial"; 771 status = "disabled"; 772 }; 773 774 uarte: serial@3140000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x03140000 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTE>; 780 clock-names = "serial"; 781 resets = <&bpmp TEGRA194_RESET_UARTE>; 782 reset-names = "serial"; 783 status = "disabled"; 784 }; 785 786 uartf: serial@3150000 { 787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 788 reg = <0x03150000 0x40>; 789 reg-shift = <2>; 790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_UARTF>; 792 clock-names = "serial"; 793 resets = <&bpmp TEGRA194_RESET_UARTF>; 794 reset-names = "serial"; 795 status = "disabled"; 796 }; 797 798 gen1_i2c: i2c@3160000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x03160000 0x10000>; 801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C1>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C1>; 807 reset-names = "i2c"; 808 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 809 dma-coherent; 810 dmas = <&gpcdma 21>, <&gpcdma 21>; 811 dma-names = "rx", "tx"; 812 status = "disabled"; 813 }; 814 815 uarth: serial@3170000 { 816 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 817 reg = <0x03170000 0x40>; 818 reg-shift = <2>; 819 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&bpmp TEGRA194_CLK_UARTH>; 821 clock-names = "serial"; 822 resets = <&bpmp TEGRA194_RESET_UARTH>; 823 reset-names = "serial"; 824 status = "disabled"; 825 }; 826 827 cam_i2c: i2c@3180000 { 828 compatible = "nvidia,tegra194-i2c"; 829 reg = <0x03180000 0x10000>; 830 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 clocks = <&bpmp TEGRA194_CLK_I2C3>; 834 clock-names = "div-clk"; 835 resets = <&bpmp TEGRA194_RESET_I2C3>; 836 reset-names = "i2c"; 837 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 838 dma-coherent; 839 dmas = <&gpcdma 23>, <&gpcdma 23>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 /* shares pads with dpaux1 */ 845 dp_aux_ch1_i2c: i2c@3190000 { 846 compatible = "nvidia,tegra194-i2c"; 847 reg = <0x03190000 0x10000>; 848 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 clocks = <&bpmp TEGRA194_CLK_I2C4>; 852 clock-names = "div-clk"; 853 resets = <&bpmp TEGRA194_RESET_I2C4>; 854 reset-names = "i2c"; 855 pinctrl-0 = <&state_dpaux1_i2c>; 856 pinctrl-1 = <&state_dpaux1_off>; 857 pinctrl-names = "default", "idle"; 858 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 859 dma-coherent; 860 dmas = <&gpcdma 26>, <&gpcdma 26>; 861 dma-names = "rx", "tx"; 862 status = "disabled"; 863 }; 864 865 /* shares pads with dpaux0 */ 866 dp_aux_ch0_i2c: i2c@31b0000 { 867 compatible = "nvidia,tegra194-i2c"; 868 reg = <0x031b0000 0x10000>; 869 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 clocks = <&bpmp TEGRA194_CLK_I2C6>; 873 clock-names = "div-clk"; 874 resets = <&bpmp TEGRA194_RESET_I2C6>; 875 reset-names = "i2c"; 876 pinctrl-0 = <&state_dpaux0_i2c>; 877 pinctrl-1 = <&state_dpaux0_off>; 878 pinctrl-names = "default", "idle"; 879 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 880 dma-coherent; 881 dmas = <&gpcdma 30>, <&gpcdma 30>; 882 dma-names = "rx", "tx"; 883 status = "disabled"; 884 }; 885 886 /* shares pads with dpaux2 */ 887 dp_aux_ch2_i2c: i2c@31c0000 { 888 compatible = "nvidia,tegra194-i2c"; 889 reg = <0x031c0000 0x10000>; 890 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 clocks = <&bpmp TEGRA194_CLK_I2C7>; 894 clock-names = "div-clk"; 895 resets = <&bpmp TEGRA194_RESET_I2C7>; 896 reset-names = "i2c"; 897 pinctrl-0 = <&state_dpaux2_i2c>; 898 pinctrl-1 = <&state_dpaux2_off>; 899 pinctrl-names = "default", "idle"; 900 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 901 dma-coherent; 902 dmas = <&gpcdma 27>, <&gpcdma 27>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 /* shares pads with dpaux3 */ 908 dp_aux_ch3_i2c: i2c@31e0000 { 909 compatible = "nvidia,tegra194-i2c"; 910 reg = <0x031e0000 0x10000>; 911 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&bpmp TEGRA194_CLK_I2C9>; 915 clock-names = "div-clk"; 916 resets = <&bpmp TEGRA194_RESET_I2C9>; 917 reset-names = "i2c"; 918 pinctrl-0 = <&state_dpaux3_i2c>; 919 pinctrl-1 = <&state_dpaux3_off>; 920 pinctrl-names = "default", "idle"; 921 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 922 dma-coherent; 923 dmas = <&gpcdma 31>, <&gpcdma 31>; 924 dma-names = "rx", "tx"; 925 status = "disabled"; 926 }; 927 928 spi@3270000 { 929 compatible = "nvidia,tegra194-qspi"; 930 reg = <0x3270000 0x1000>; 931 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 935 <&bpmp TEGRA194_CLK_QSPI0_PM>; 936 clock-names = "qspi", "qspi_out"; 937 resets = <&bpmp TEGRA194_RESET_QSPI0>; 938 reset-names = "qspi"; 939 status = "disabled"; 940 }; 941 942 spi@3300000 { 943 compatible = "nvidia,tegra194-qspi"; 944 reg = <0x3300000 0x1000>; 945 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 949 <&bpmp TEGRA194_CLK_QSPI1_PM>; 950 clock-names = "qspi", "qspi_out"; 951 resets = <&bpmp TEGRA194_RESET_QSPI1>; 952 reset-names = "qspi"; 953 status = "disabled"; 954 }; 955 956 pwm1: pwm@3280000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x3280000 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM1>; 961 clock-names = "pwm"; 962 resets = <&bpmp TEGRA194_RESET_PWM1>; 963 reset-names = "pwm"; 964 status = "disabled"; 965 #pwm-cells = <2>; 966 }; 967 968 pwm2: pwm@3290000 { 969 compatible = "nvidia,tegra194-pwm", 970 "nvidia,tegra186-pwm"; 971 reg = <0x3290000 0x10000>; 972 clocks = <&bpmp TEGRA194_CLK_PWM2>; 973 clock-names = "pwm"; 974 resets = <&bpmp TEGRA194_RESET_PWM2>; 975 reset-names = "pwm"; 976 status = "disabled"; 977 #pwm-cells = <2>; 978 }; 979 980 pwm3: pwm@32a0000 { 981 compatible = "nvidia,tegra194-pwm", 982 "nvidia,tegra186-pwm"; 983 reg = <0x32a0000 0x10000>; 984 clocks = <&bpmp TEGRA194_CLK_PWM3>; 985 clock-names = "pwm"; 986 resets = <&bpmp TEGRA194_RESET_PWM3>; 987 reset-names = "pwm"; 988 status = "disabled"; 989 #pwm-cells = <2>; 990 }; 991 992 pwm5: pwm@32c0000 { 993 compatible = "nvidia,tegra194-pwm", 994 "nvidia,tegra186-pwm"; 995 reg = <0x32c0000 0x10000>; 996 clocks = <&bpmp TEGRA194_CLK_PWM5>; 997 clock-names = "pwm"; 998 resets = <&bpmp TEGRA194_RESET_PWM5>; 999 reset-names = "pwm"; 1000 status = "disabled"; 1001 #pwm-cells = <2>; 1002 }; 1003 1004 pwm6: pwm@32d0000 { 1005 compatible = "nvidia,tegra194-pwm", 1006 "nvidia,tegra186-pwm"; 1007 reg = <0x32d0000 0x10000>; 1008 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1009 clock-names = "pwm"; 1010 resets = <&bpmp TEGRA194_RESET_PWM6>; 1011 reset-names = "pwm"; 1012 status = "disabled"; 1013 #pwm-cells = <2>; 1014 }; 1015 1016 pwm7: pwm@32e0000 { 1017 compatible = "nvidia,tegra194-pwm", 1018 "nvidia,tegra186-pwm"; 1019 reg = <0x32e0000 0x10000>; 1020 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1021 clock-names = "pwm"; 1022 resets = <&bpmp TEGRA194_RESET_PWM7>; 1023 reset-names = "pwm"; 1024 status = "disabled"; 1025 #pwm-cells = <2>; 1026 }; 1027 1028 pwm8: pwm@32f0000 { 1029 compatible = "nvidia,tegra194-pwm", 1030 "nvidia,tegra186-pwm"; 1031 reg = <0x32f0000 0x10000>; 1032 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1033 clock-names = "pwm"; 1034 resets = <&bpmp TEGRA194_RESET_PWM8>; 1035 reset-names = "pwm"; 1036 status = "disabled"; 1037 #pwm-cells = <2>; 1038 }; 1039 1040 sdmmc1: mmc@3400000 { 1041 compatible = "nvidia,tegra194-sdhci"; 1042 reg = <0x03400000 0x10000>; 1043 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1045 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1046 clock-names = "sdhci", "tmclk"; 1047 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1048 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1049 assigned-clock-parents = 1050 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1051 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1052 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1053 reset-names = "sdhci"; 1054 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1055 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1056 interconnect-names = "dma-mem", "write"; 1057 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1058 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1059 pinctrl-0 = <&sdmmc1_3v3>; 1060 pinctrl-1 = <&sdmmc1_1v8>; 1061 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1062 <0x07>; 1063 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1064 <0x07>; 1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1066 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1067 <0x07>; 1068 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1069 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1070 nvidia,default-tap = <0x9>; 1071 nvidia,default-trim = <0x5>; 1072 sd-uhs-sdr25; 1073 sd-uhs-sdr50; 1074 sd-uhs-ddr50; 1075 sd-uhs-sdr104; 1076 status = "disabled"; 1077 }; 1078 1079 sdmmc3: mmc@3440000 { 1080 compatible = "nvidia,tegra194-sdhci"; 1081 reg = <0x03440000 0x10000>; 1082 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1084 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1085 clock-names = "sdhci", "tmclk"; 1086 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1087 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1088 assigned-clock-parents = 1089 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1090 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1091 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1092 reset-names = "sdhci"; 1093 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1094 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1095 interconnect-names = "dma-mem", "write"; 1096 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1097 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1098 pinctrl-0 = <&sdmmc3_3v3>; 1099 pinctrl-1 = <&sdmmc3_1v8>; 1100 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1101 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1102 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1103 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1104 <0x07>; 1105 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1106 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1107 <0x07>; 1108 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1109 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1110 nvidia,default-tap = <0x9>; 1111 nvidia,default-trim = <0x5>; 1112 sd-uhs-sdr25; 1113 sd-uhs-sdr50; 1114 sd-uhs-ddr50; 1115 sd-uhs-sdr104; 1116 status = "disabled"; 1117 }; 1118 1119 sdmmc4: mmc@3460000 { 1120 compatible = "nvidia,tegra194-sdhci"; 1121 reg = <0x03460000 0x10000>; 1122 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1124 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1125 clock-names = "sdhci", "tmclk"; 1126 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1127 <&bpmp TEGRA194_CLK_PLLC4>; 1128 assigned-clock-parents = 1129 <&bpmp TEGRA194_CLK_PLLC4>; 1130 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1131 reset-names = "sdhci"; 1132 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1133 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1134 interconnect-names = "dma-mem", "write"; 1135 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1136 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1137 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1138 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1139 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1140 <0x0a>; 1141 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1142 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1143 <0x0a>; 1144 nvidia,default-tap = <0x8>; 1145 nvidia,default-trim = <0x14>; 1146 nvidia,dqs-trim = <40>; 1147 cap-mmc-highspeed; 1148 mmc-ddr-1_8v; 1149 mmc-hs200-1_8v; 1150 mmc-hs400-1_8v; 1151 mmc-hs400-enhanced-strobe; 1152 supports-cqe; 1153 status = "disabled"; 1154 }; 1155 1156 hda@3510000 { 1157 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1158 reg = <0x3510000 0x10000>; 1159 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&bpmp TEGRA194_CLK_HDA>, 1161 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1162 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1163 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1164 resets = <&bpmp TEGRA194_RESET_HDA>, 1165 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1166 reset-names = "hda", "hda2hdmi"; 1167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1168 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1169 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1170 interconnect-names = "dma-mem", "write"; 1171 iommus = <&smmu TEGRA194_SID_HDA>; 1172 status = "disabled"; 1173 }; 1174 1175 xusb_padctl: padctl@3520000 { 1176 compatible = "nvidia,tegra194-xusb-padctl"; 1177 reg = <0x03520000 0x1000>, 1178 <0x03540000 0x1000>; 1179 reg-names = "padctl", "ao"; 1180 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1181 1182 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1183 reset-names = "padctl"; 1184 1185 status = "disabled"; 1186 1187 pads { 1188 usb2 { 1189 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1190 clock-names = "trk"; 1191 1192 lanes { 1193 usb2-0 { 1194 nvidia,function = "xusb"; 1195 status = "disabled"; 1196 #phy-cells = <0>; 1197 }; 1198 1199 usb2-1 { 1200 nvidia,function = "xusb"; 1201 status = "disabled"; 1202 #phy-cells = <0>; 1203 }; 1204 1205 usb2-2 { 1206 nvidia,function = "xusb"; 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 1211 usb2-3 { 1212 nvidia,function = "xusb"; 1213 status = "disabled"; 1214 #phy-cells = <0>; 1215 }; 1216 }; 1217 }; 1218 1219 usb3 { 1220 lanes { 1221 usb3-0 { 1222 nvidia,function = "xusb"; 1223 status = "disabled"; 1224 #phy-cells = <0>; 1225 }; 1226 1227 usb3-1 { 1228 nvidia,function = "xusb"; 1229 status = "disabled"; 1230 #phy-cells = <0>; 1231 }; 1232 1233 usb3-2 { 1234 nvidia,function = "xusb"; 1235 status = "disabled"; 1236 #phy-cells = <0>; 1237 }; 1238 1239 usb3-3 { 1240 nvidia,function = "xusb"; 1241 status = "disabled"; 1242 #phy-cells = <0>; 1243 }; 1244 }; 1245 }; 1246 }; 1247 1248 ports { 1249 usb2-0 { 1250 status = "disabled"; 1251 }; 1252 1253 usb2-1 { 1254 status = "disabled"; 1255 }; 1256 1257 usb2-2 { 1258 status = "disabled"; 1259 }; 1260 1261 usb2-3 { 1262 status = "disabled"; 1263 }; 1264 1265 usb3-0 { 1266 status = "disabled"; 1267 }; 1268 1269 usb3-1 { 1270 status = "disabled"; 1271 }; 1272 1273 usb3-2 { 1274 status = "disabled"; 1275 }; 1276 1277 usb3-3 { 1278 status = "disabled"; 1279 }; 1280 }; 1281 }; 1282 1283 usb@3550000 { 1284 compatible = "nvidia,tegra194-xudc"; 1285 reg = <0x03550000 0x8000>, 1286 <0x03558000 0x1000>; 1287 reg-names = "base", "fpci"; 1288 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1290 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1291 <&bpmp TEGRA194_CLK_XUSB_SS>, 1292 <&bpmp TEGRA194_CLK_XUSB_FS>; 1293 clock-names = "dev", "ss", "ss_src", "fs_src"; 1294 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1295 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1296 interconnect-names = "dma-mem", "write"; 1297 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1298 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1299 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1300 power-domain-names = "dev", "ss"; 1301 nvidia,xusb-padctl = <&xusb_padctl>; 1302 status = "disabled"; 1303 }; 1304 1305 usb@3610000 { 1306 compatible = "nvidia,tegra194-xusb"; 1307 reg = <0x03610000 0x40000>, 1308 <0x03600000 0x10000>; 1309 reg-names = "hcd", "fpci"; 1310 1311 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1313 1314 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1315 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1316 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1317 <&bpmp TEGRA194_CLK_XUSB_SS>, 1318 <&bpmp TEGRA194_CLK_CLK_M>, 1319 <&bpmp TEGRA194_CLK_XUSB_FS>, 1320 <&bpmp TEGRA194_CLK_UTMIPLL>, 1321 <&bpmp TEGRA194_CLK_CLK_M>, 1322 <&bpmp TEGRA194_CLK_PLLE>; 1323 clock-names = "xusb_host", "xusb_falcon_src", 1324 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1325 "xusb_fs_src", "pll_u_480m", "clk_m", 1326 "pll_e"; 1327 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1328 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1329 interconnect-names = "dma-mem", "write"; 1330 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1331 1332 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1333 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1334 power-domain-names = "xusb_host", "xusb_ss"; 1335 1336 nvidia,xusb-padctl = <&xusb_padctl>; 1337 status = "disabled"; 1338 }; 1339 1340 fuse@3820000 { 1341 compatible = "nvidia,tegra194-efuse"; 1342 reg = <0x03820000 0x10000>; 1343 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1344 clock-names = "fuse"; 1345 }; 1346 1347 gic: interrupt-controller@3881000 { 1348 compatible = "arm,gic-400"; 1349 #interrupt-cells = <3>; 1350 interrupt-controller; 1351 reg = <0x03881000 0x1000>, 1352 <0x03882000 0x2000>, 1353 <0x03884000 0x2000>, 1354 <0x03886000 0x2000>; 1355 interrupts = <GIC_PPI 9 1356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1357 interrupt-parent = <&gic>; 1358 }; 1359 1360 cec@3960000 { 1361 compatible = "nvidia,tegra194-cec"; 1362 reg = <0x03960000 0x10000>; 1363 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&bpmp TEGRA194_CLK_CEC>; 1365 clock-names = "cec"; 1366 status = "disabled"; 1367 }; 1368 1369 hsp_top0: hsp@3c00000 { 1370 compatible = "nvidia,tegra194-hsp"; 1371 reg = <0x03c00000 0xa0000>; 1372 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1381 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1382 "shared3", "shared4", "shared5", "shared6", 1383 "shared7"; 1384 #mbox-cells = <2>; 1385 }; 1386 1387 p2u_hsio_0: phy@3e10000 { 1388 compatible = "nvidia,tegra194-p2u"; 1389 reg = <0x03e10000 0x10000>; 1390 reg-names = "ctl"; 1391 1392 #phy-cells = <0>; 1393 }; 1394 1395 p2u_hsio_1: phy@3e20000 { 1396 compatible = "nvidia,tegra194-p2u"; 1397 reg = <0x03e20000 0x10000>; 1398 reg-names = "ctl"; 1399 1400 #phy-cells = <0>; 1401 }; 1402 1403 p2u_hsio_2: phy@3e30000 { 1404 compatible = "nvidia,tegra194-p2u"; 1405 reg = <0x03e30000 0x10000>; 1406 reg-names = "ctl"; 1407 1408 #phy-cells = <0>; 1409 }; 1410 1411 p2u_hsio_3: phy@3e40000 { 1412 compatible = "nvidia,tegra194-p2u"; 1413 reg = <0x03e40000 0x10000>; 1414 reg-names = "ctl"; 1415 1416 #phy-cells = <0>; 1417 }; 1418 1419 p2u_hsio_4: phy@3e50000 { 1420 compatible = "nvidia,tegra194-p2u"; 1421 reg = <0x03e50000 0x10000>; 1422 reg-names = "ctl"; 1423 1424 #phy-cells = <0>; 1425 }; 1426 1427 p2u_hsio_5: phy@3e60000 { 1428 compatible = "nvidia,tegra194-p2u"; 1429 reg = <0x03e60000 0x10000>; 1430 reg-names = "ctl"; 1431 1432 #phy-cells = <0>; 1433 }; 1434 1435 p2u_hsio_6: phy@3e70000 { 1436 compatible = "nvidia,tegra194-p2u"; 1437 reg = <0x03e70000 0x10000>; 1438 reg-names = "ctl"; 1439 1440 #phy-cells = <0>; 1441 }; 1442 1443 p2u_hsio_7: phy@3e80000 { 1444 compatible = "nvidia,tegra194-p2u"; 1445 reg = <0x03e80000 0x10000>; 1446 reg-names = "ctl"; 1447 1448 #phy-cells = <0>; 1449 }; 1450 1451 p2u_hsio_8: phy@3e90000 { 1452 compatible = "nvidia,tegra194-p2u"; 1453 reg = <0x03e90000 0x10000>; 1454 reg-names = "ctl"; 1455 1456 #phy-cells = <0>; 1457 }; 1458 1459 p2u_hsio_9: phy@3ea0000 { 1460 compatible = "nvidia,tegra194-p2u"; 1461 reg = <0x03ea0000 0x10000>; 1462 reg-names = "ctl"; 1463 1464 #phy-cells = <0>; 1465 }; 1466 1467 p2u_nvhs_0: phy@3eb0000 { 1468 compatible = "nvidia,tegra194-p2u"; 1469 reg = <0x03eb0000 0x10000>; 1470 reg-names = "ctl"; 1471 1472 #phy-cells = <0>; 1473 }; 1474 1475 p2u_nvhs_1: phy@3ec0000 { 1476 compatible = "nvidia,tegra194-p2u"; 1477 reg = <0x03ec0000 0x10000>; 1478 reg-names = "ctl"; 1479 1480 #phy-cells = <0>; 1481 }; 1482 1483 p2u_nvhs_2: phy@3ed0000 { 1484 compatible = "nvidia,tegra194-p2u"; 1485 reg = <0x03ed0000 0x10000>; 1486 reg-names = "ctl"; 1487 1488 #phy-cells = <0>; 1489 }; 1490 1491 p2u_nvhs_3: phy@3ee0000 { 1492 compatible = "nvidia,tegra194-p2u"; 1493 reg = <0x03ee0000 0x10000>; 1494 reg-names = "ctl"; 1495 1496 #phy-cells = <0>; 1497 }; 1498 1499 p2u_nvhs_4: phy@3ef0000 { 1500 compatible = "nvidia,tegra194-p2u"; 1501 reg = <0x03ef0000 0x10000>; 1502 reg-names = "ctl"; 1503 1504 #phy-cells = <0>; 1505 }; 1506 1507 p2u_nvhs_5: phy@3f00000 { 1508 compatible = "nvidia,tegra194-p2u"; 1509 reg = <0x03f00000 0x10000>; 1510 reg-names = "ctl"; 1511 1512 #phy-cells = <0>; 1513 }; 1514 1515 p2u_nvhs_6: phy@3f10000 { 1516 compatible = "nvidia,tegra194-p2u"; 1517 reg = <0x03f10000 0x10000>; 1518 reg-names = "ctl"; 1519 1520 #phy-cells = <0>; 1521 }; 1522 1523 p2u_nvhs_7: phy@3f20000 { 1524 compatible = "nvidia,tegra194-p2u"; 1525 reg = <0x03f20000 0x10000>; 1526 reg-names = "ctl"; 1527 1528 #phy-cells = <0>; 1529 }; 1530 1531 p2u_hsio_10: phy@3f30000 { 1532 compatible = "nvidia,tegra194-p2u"; 1533 reg = <0x03f30000 0x10000>; 1534 reg-names = "ctl"; 1535 1536 #phy-cells = <0>; 1537 }; 1538 1539 p2u_hsio_11: phy@3f40000 { 1540 compatible = "nvidia,tegra194-p2u"; 1541 reg = <0x03f40000 0x10000>; 1542 reg-names = "ctl"; 1543 1544 #phy-cells = <0>; 1545 }; 1546 1547 sce-noc@b600000 { 1548 compatible = "nvidia,tegra194-sce-noc"; 1549 reg = <0xb600000 0x1000>; 1550 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1552 nvidia,axi2apb = <&axi2apb>; 1553 nvidia,apbmisc = <&apbmisc>; 1554 status = "okay"; 1555 }; 1556 1557 rce-noc@be00000 { 1558 compatible = "nvidia,tegra194-rce-noc"; 1559 reg = <0xbe00000 0x1000>; 1560 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1562 nvidia,axi2apb = <&axi2apb>; 1563 nvidia,apbmisc = <&apbmisc>; 1564 status = "okay"; 1565 }; 1566 1567 hsp_aon: hsp@c150000 { 1568 compatible = "nvidia,tegra194-hsp"; 1569 reg = <0x0c150000 0x90000>; 1570 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1574 /* 1575 * Shared interrupt 0 is routed only to AON/SPE, so 1576 * we only have 4 shared interrupts for the CCPLEX. 1577 */ 1578 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1579 #mbox-cells = <2>; 1580 }; 1581 1582 gen2_i2c: i2c@c240000 { 1583 compatible = "nvidia,tegra194-i2c"; 1584 reg = <0x0c240000 0x10000>; 1585 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1589 clock-names = "div-clk"; 1590 resets = <&bpmp TEGRA194_RESET_I2C2>; 1591 reset-names = "i2c"; 1592 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1593 dma-coherent; 1594 dmas = <&gpcdma 22>, <&gpcdma 22>; 1595 dma-names = "rx", "tx"; 1596 status = "disabled"; 1597 }; 1598 1599 gen8_i2c: i2c@c250000 { 1600 compatible = "nvidia,tegra194-i2c"; 1601 reg = <0x0c250000 0x10000>; 1602 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1606 clock-names = "div-clk"; 1607 resets = <&bpmp TEGRA194_RESET_I2C8>; 1608 reset-names = "i2c"; 1609 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1610 dma-coherent; 1611 dmas = <&gpcdma 0>, <&gpcdma 0>; 1612 dma-names = "rx", "tx"; 1613 status = "disabled"; 1614 }; 1615 1616 uartc: serial@c280000 { 1617 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1618 reg = <0x0c280000 0x40>; 1619 reg-shift = <2>; 1620 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1622 clock-names = "serial"; 1623 resets = <&bpmp TEGRA194_RESET_UARTC>; 1624 reset-names = "serial"; 1625 status = "disabled"; 1626 }; 1627 1628 uartg: serial@c290000 { 1629 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1630 reg = <0x0c290000 0x40>; 1631 reg-shift = <2>; 1632 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1634 clock-names = "serial"; 1635 resets = <&bpmp TEGRA194_RESET_UARTG>; 1636 reset-names = "serial"; 1637 status = "disabled"; 1638 }; 1639 1640 rtc: rtc@c2a0000 { 1641 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1642 reg = <0x0c2a0000 0x10000>; 1643 interrupt-parent = <&pmc>; 1644 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1646 clock-names = "rtc"; 1647 status = "disabled"; 1648 }; 1649 1650 gpio_aon: gpio@c2f0000 { 1651 compatible = "nvidia,tegra194-gpio-aon"; 1652 reg-names = "security", "gpio"; 1653 reg = <0xc2f0000 0x1000>, 1654 <0xc2f1000 0x1000>; 1655 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1659 gpio-controller; 1660 #gpio-cells = <2>; 1661 interrupt-controller; 1662 #interrupt-cells = <2>; 1663 }; 1664 1665 pwm4: pwm@c340000 { 1666 compatible = "nvidia,tegra194-pwm", 1667 "nvidia,tegra186-pwm"; 1668 reg = <0xc340000 0x10000>; 1669 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1670 clock-names = "pwm"; 1671 resets = <&bpmp TEGRA194_RESET_PWM4>; 1672 reset-names = "pwm"; 1673 status = "disabled"; 1674 #pwm-cells = <2>; 1675 }; 1676 1677 pmc: pmc@c360000 { 1678 compatible = "nvidia,tegra194-pmc"; 1679 reg = <0x0c360000 0x10000>, 1680 <0x0c370000 0x10000>, 1681 <0x0c380000 0x10000>, 1682 <0x0c390000 0x10000>, 1683 <0x0c3a0000 0x10000>; 1684 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1685 1686 #interrupt-cells = <2>; 1687 interrupt-controller; 1688 sdmmc1_3v3: sdmmc1-3v3 { 1689 pins = "sdmmc1-hv"; 1690 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1691 }; 1692 1693 sdmmc1_1v8: sdmmc1-1v8 { 1694 pins = "sdmmc1-hv"; 1695 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1696 }; 1697 sdmmc3_3v3: sdmmc3-3v3 { 1698 pins = "sdmmc3-hv"; 1699 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1700 }; 1701 1702 sdmmc3_1v8: sdmmc3-1v8 { 1703 pins = "sdmmc3-hv"; 1704 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1705 }; 1706 1707 }; 1708 1709 aon-noc@c600000 { 1710 compatible = "nvidia,tegra194-aon-noc"; 1711 reg = <0xc600000 0x1000>; 1712 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1714 nvidia,apbmisc = <&apbmisc>; 1715 status = "okay"; 1716 }; 1717 1718 bpmp-noc@d600000 { 1719 compatible = "nvidia,tegra194-bpmp-noc"; 1720 reg = <0xd600000 0x1000>; 1721 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1723 nvidia,axi2apb = <&axi2apb>; 1724 nvidia,apbmisc = <&apbmisc>; 1725 status = "okay"; 1726 }; 1727 1728 iommu@10000000 { 1729 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1730 reg = <0x10000000 0x800000>; 1731 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1796 stream-match-mask = <0x7f80>; 1797 #global-interrupts = <1>; 1798 #iommu-cells = <1>; 1799 1800 nvidia,memory-controller = <&mc>; 1801 status = "disabled"; 1802 }; 1803 1804 smmu: iommu@12000000 { 1805 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1806 reg = <0x12000000 0x800000>, 1807 <0x11000000 0x800000>; 1808 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1874 stream-match-mask = <0x7f80>; 1875 #global-interrupts = <2>; 1876 #iommu-cells = <1>; 1877 1878 nvidia,memory-controller = <&mc>; 1879 status = "okay"; 1880 }; 1881 1882 host1x@13e00000 { 1883 compatible = "nvidia,tegra194-host1x"; 1884 reg = <0x13e00000 0x10000>, 1885 <0x13e10000 0x10000>; 1886 reg-names = "hypervisor", "vm"; 1887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-names = "syncpt", "host1x"; 1890 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1891 clock-names = "host1x"; 1892 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1893 reset-names = "host1x"; 1894 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 1898 ranges = <0x15000000 0x15000000 0x01000000>; 1899 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1900 interconnect-names = "dma-mem"; 1901 iommus = <&smmu TEGRA194_SID_HOST1X>; 1902 1903 /* Context isolation domains */ 1904 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1905 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1906 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1907 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1908 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1909 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1910 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1911 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1912 1913 nvdec@15140000 { 1914 compatible = "nvidia,tegra194-nvdec"; 1915 reg = <0x15140000 0x00040000>; 1916 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1917 clock-names = "nvdec"; 1918 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1919 reset-names = "nvdec"; 1920 1921 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1922 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1923 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1924 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1925 interconnect-names = "dma-mem", "read-1", "write"; 1926 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1927 dma-coherent; 1928 1929 nvidia,host1x-class = <0xf5>; 1930 }; 1931 1932 display-hub@15200000 { 1933 compatible = "nvidia,tegra194-display"; 1934 reg = <0x15200000 0x00040000>; 1935 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1936 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1937 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1938 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1939 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1940 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1941 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1942 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1943 "wgrp3", "wgrp4", "wgrp5"; 1944 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1945 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1946 clock-names = "disp", "hub"; 1947 status = "disabled"; 1948 1949 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1950 1951 #address-cells = <1>; 1952 #size-cells = <1>; 1953 1954 ranges = <0x15200000 0x15200000 0x40000>; 1955 1956 display@15200000 { 1957 compatible = "nvidia,tegra194-dc"; 1958 reg = <0x15200000 0x10000>; 1959 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1960 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1961 clock-names = "dc"; 1962 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1963 reset-names = "dc"; 1964 1965 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1966 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1967 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1968 interconnect-names = "dma-mem", "read-1"; 1969 1970 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1971 nvidia,head = <0>; 1972 }; 1973 1974 display@15210000 { 1975 compatible = "nvidia,tegra194-dc"; 1976 reg = <0x15210000 0x10000>; 1977 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1979 clock-names = "dc"; 1980 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1981 reset-names = "dc"; 1982 1983 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1984 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1985 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1986 interconnect-names = "dma-mem", "read-1"; 1987 1988 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1989 nvidia,head = <1>; 1990 }; 1991 1992 display@15220000 { 1993 compatible = "nvidia,tegra194-dc"; 1994 reg = <0x15220000 0x10000>; 1995 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1996 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1997 clock-names = "dc"; 1998 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1999 reset-names = "dc"; 2000 2001 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2002 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2003 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2004 interconnect-names = "dma-mem", "read-1"; 2005 2006 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2007 nvidia,head = <2>; 2008 }; 2009 2010 display@15230000 { 2011 compatible = "nvidia,tegra194-dc"; 2012 reg = <0x15230000 0x10000>; 2013 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2014 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2015 clock-names = "dc"; 2016 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2017 reset-names = "dc"; 2018 2019 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2020 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2021 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2022 interconnect-names = "dma-mem", "read-1"; 2023 2024 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2025 nvidia,head = <3>; 2026 }; 2027 }; 2028 2029 vic@15340000 { 2030 compatible = "nvidia,tegra194-vic"; 2031 reg = <0x15340000 0x00040000>; 2032 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2033 clocks = <&bpmp TEGRA194_CLK_VIC>; 2034 clock-names = "vic"; 2035 resets = <&bpmp TEGRA194_RESET_VIC>; 2036 reset-names = "vic"; 2037 2038 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2039 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2040 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2041 interconnect-names = "dma-mem", "write"; 2042 iommus = <&smmu TEGRA194_SID_VIC>; 2043 dma-coherent; 2044 }; 2045 2046 nvjpg@15380000 { 2047 compatible = "nvidia,tegra194-nvjpg"; 2048 reg = <0x15380000 0x40000>; 2049 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2050 clock-names = "nvjpg"; 2051 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2052 reset-names = "nvjpg"; 2053 2054 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2055 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2056 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2057 interconnect-names = "dma-mem", "write"; 2058 iommus = <&smmu TEGRA194_SID_NVJPG>; 2059 dma-coherent; 2060 }; 2061 2062 nvdec@15480000 { 2063 compatible = "nvidia,tegra194-nvdec"; 2064 reg = <0x15480000 0x00040000>; 2065 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2066 clock-names = "nvdec"; 2067 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2068 reset-names = "nvdec"; 2069 2070 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2071 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2072 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2073 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2074 interconnect-names = "dma-mem", "read-1", "write"; 2075 iommus = <&smmu TEGRA194_SID_NVDEC>; 2076 dma-coherent; 2077 2078 nvidia,host1x-class = <0xf0>; 2079 }; 2080 2081 nvenc@154c0000 { 2082 compatible = "nvidia,tegra194-nvenc"; 2083 reg = <0x154c0000 0x40000>; 2084 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2085 clock-names = "nvenc"; 2086 resets = <&bpmp TEGRA194_RESET_NVENC>; 2087 reset-names = "nvenc"; 2088 2089 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2090 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2091 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2092 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2093 interconnect-names = "dma-mem", "read-1", "write"; 2094 iommus = <&smmu TEGRA194_SID_NVENC>; 2095 dma-coherent; 2096 2097 nvidia,host1x-class = <0x21>; 2098 }; 2099 2100 dpaux0: dpaux@155c0000 { 2101 compatible = "nvidia,tegra194-dpaux"; 2102 reg = <0x155c0000 0x10000>; 2103 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2104 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2105 <&bpmp TEGRA194_CLK_PLLDP>; 2106 clock-names = "dpaux", "parent"; 2107 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2108 reset-names = "dpaux"; 2109 status = "disabled"; 2110 2111 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2112 2113 state_dpaux0_aux: pinmux-aux { 2114 groups = "dpaux-io"; 2115 function = "aux"; 2116 }; 2117 2118 state_dpaux0_i2c: pinmux-i2c { 2119 groups = "dpaux-io"; 2120 function = "i2c"; 2121 }; 2122 2123 state_dpaux0_off: pinmux-off { 2124 groups = "dpaux-io"; 2125 function = "off"; 2126 }; 2127 2128 i2c-bus { 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 }; 2132 }; 2133 2134 dpaux1: dpaux@155d0000 { 2135 compatible = "nvidia,tegra194-dpaux"; 2136 reg = <0x155d0000 0x10000>; 2137 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2138 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2139 <&bpmp TEGRA194_CLK_PLLDP>; 2140 clock-names = "dpaux", "parent"; 2141 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2142 reset-names = "dpaux"; 2143 status = "disabled"; 2144 2145 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2146 2147 state_dpaux1_aux: pinmux-aux { 2148 groups = "dpaux-io"; 2149 function = "aux"; 2150 }; 2151 2152 state_dpaux1_i2c: pinmux-i2c { 2153 groups = "dpaux-io"; 2154 function = "i2c"; 2155 }; 2156 2157 state_dpaux1_off: pinmux-off { 2158 groups = "dpaux-io"; 2159 function = "off"; 2160 }; 2161 2162 i2c-bus { 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 }; 2166 }; 2167 2168 dpaux2: dpaux@155e0000 { 2169 compatible = "nvidia,tegra194-dpaux"; 2170 reg = <0x155e0000 0x10000>; 2171 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2173 <&bpmp TEGRA194_CLK_PLLDP>; 2174 clock-names = "dpaux", "parent"; 2175 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2176 reset-names = "dpaux"; 2177 status = "disabled"; 2178 2179 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2180 2181 state_dpaux2_aux: pinmux-aux { 2182 groups = "dpaux-io"; 2183 function = "aux"; 2184 }; 2185 2186 state_dpaux2_i2c: pinmux-i2c { 2187 groups = "dpaux-io"; 2188 function = "i2c"; 2189 }; 2190 2191 state_dpaux2_off: pinmux-off { 2192 groups = "dpaux-io"; 2193 function = "off"; 2194 }; 2195 2196 i2c-bus { 2197 #address-cells = <1>; 2198 #size-cells = <0>; 2199 }; 2200 }; 2201 2202 dpaux3: dpaux@155f0000 { 2203 compatible = "nvidia,tegra194-dpaux"; 2204 reg = <0x155f0000 0x10000>; 2205 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2207 <&bpmp TEGRA194_CLK_PLLDP>; 2208 clock-names = "dpaux", "parent"; 2209 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2210 reset-names = "dpaux"; 2211 status = "disabled"; 2212 2213 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2214 2215 state_dpaux3_aux: pinmux-aux { 2216 groups = "dpaux-io"; 2217 function = "aux"; 2218 }; 2219 2220 state_dpaux3_i2c: pinmux-i2c { 2221 groups = "dpaux-io"; 2222 function = "i2c"; 2223 }; 2224 2225 state_dpaux3_off: pinmux-off { 2226 groups = "dpaux-io"; 2227 function = "off"; 2228 }; 2229 2230 i2c-bus { 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 }; 2234 }; 2235 2236 nvenc@15a80000 { 2237 compatible = "nvidia,tegra194-nvenc"; 2238 reg = <0x15a80000 0x00040000>; 2239 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2240 clock-names = "nvenc"; 2241 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2242 reset-names = "nvenc"; 2243 2244 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2245 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2246 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2247 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2248 interconnect-names = "dma-mem", "read-1", "write"; 2249 iommus = <&smmu TEGRA194_SID_NVENC1>; 2250 dma-coherent; 2251 2252 nvidia,host1x-class = <0x22>; 2253 }; 2254 2255 sor0: sor@15b00000 { 2256 compatible = "nvidia,tegra194-sor"; 2257 reg = <0x15b00000 0x40000>; 2258 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2259 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2260 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2261 <&bpmp TEGRA194_CLK_PLLD>, 2262 <&bpmp TEGRA194_CLK_PLLDP>, 2263 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2264 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2265 clock-names = "sor", "out", "parent", "dp", "safe", 2266 "pad"; 2267 resets = <&bpmp TEGRA194_RESET_SOR0>; 2268 reset-names = "sor"; 2269 pinctrl-0 = <&state_dpaux0_aux>; 2270 pinctrl-1 = <&state_dpaux0_i2c>; 2271 pinctrl-2 = <&state_dpaux0_off>; 2272 pinctrl-names = "aux", "i2c", "off"; 2273 status = "disabled"; 2274 2275 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2276 nvidia,interface = <0>; 2277 }; 2278 2279 sor1: sor@15b40000 { 2280 compatible = "nvidia,tegra194-sor"; 2281 reg = <0x15b40000 0x40000>; 2282 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2283 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2284 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2285 <&bpmp TEGRA194_CLK_PLLD2>, 2286 <&bpmp TEGRA194_CLK_PLLDP>, 2287 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2288 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2289 clock-names = "sor", "out", "parent", "dp", "safe", 2290 "pad"; 2291 resets = <&bpmp TEGRA194_RESET_SOR1>; 2292 reset-names = "sor"; 2293 pinctrl-0 = <&state_dpaux1_aux>; 2294 pinctrl-1 = <&state_dpaux1_i2c>; 2295 pinctrl-2 = <&state_dpaux1_off>; 2296 pinctrl-names = "aux", "i2c", "off"; 2297 status = "disabled"; 2298 2299 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2300 nvidia,interface = <1>; 2301 }; 2302 2303 sor2: sor@15b80000 { 2304 compatible = "nvidia,tegra194-sor"; 2305 reg = <0x15b80000 0x40000>; 2306 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2308 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2309 <&bpmp TEGRA194_CLK_PLLD3>, 2310 <&bpmp TEGRA194_CLK_PLLDP>, 2311 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2312 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2313 clock-names = "sor", "out", "parent", "dp", "safe", 2314 "pad"; 2315 resets = <&bpmp TEGRA194_RESET_SOR2>; 2316 reset-names = "sor"; 2317 pinctrl-0 = <&state_dpaux2_aux>; 2318 pinctrl-1 = <&state_dpaux2_i2c>; 2319 pinctrl-2 = <&state_dpaux2_off>; 2320 pinctrl-names = "aux", "i2c", "off"; 2321 status = "disabled"; 2322 2323 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2324 nvidia,interface = <2>; 2325 }; 2326 2327 sor3: sor@15bc0000 { 2328 compatible = "nvidia,tegra194-sor"; 2329 reg = <0x15bc0000 0x40000>; 2330 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2332 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2333 <&bpmp TEGRA194_CLK_PLLD4>, 2334 <&bpmp TEGRA194_CLK_PLLDP>, 2335 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2336 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2337 clock-names = "sor", "out", "parent", "dp", "safe", 2338 "pad"; 2339 resets = <&bpmp TEGRA194_RESET_SOR3>; 2340 reset-names = "sor"; 2341 pinctrl-0 = <&state_dpaux3_aux>; 2342 pinctrl-1 = <&state_dpaux3_i2c>; 2343 pinctrl-2 = <&state_dpaux3_off>; 2344 pinctrl-names = "aux", "i2c", "off"; 2345 status = "disabled"; 2346 2347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2348 nvidia,interface = <3>; 2349 }; 2350 }; 2351 2352 gpu@17000000 { 2353 compatible = "nvidia,gv11b"; 2354 reg = <0x17000000 0x1000000>, 2355 <0x18000000 0x1000000>; 2356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2358 interrupt-names = "stall", "nonstall"; 2359 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2360 <&bpmp TEGRA194_CLK_GPU_PWR>, 2361 <&bpmp TEGRA194_CLK_FUSE>; 2362 clock-names = "gpu", "pwr", "fuse"; 2363 resets = <&bpmp TEGRA194_RESET_GPU>; 2364 reset-names = "gpu"; 2365 dma-coherent; 2366 2367 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2368 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2369 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2370 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2371 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2372 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2373 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2374 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2375 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2376 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2377 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2378 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2379 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2380 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2381 "read-1", "read-1-hp", "write-1", 2382 "read-2", "read-2-hp", "write-2", 2383 "read-3", "read-3-hp", "write-3"; 2384 }; 2385 }; 2386 2387 pcie@14100000 { 2388 compatible = "nvidia,tegra194-pcie"; 2389 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2390 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2391 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2392 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2393 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2394 reg-names = "appl", "config", "atu_dma", "dbi"; 2395 2396 status = "disabled"; 2397 2398 #address-cells = <3>; 2399 #size-cells = <2>; 2400 device_type = "pci"; 2401 num-lanes = <1>; 2402 linux,pci-domain = <1>; 2403 2404 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2405 clock-names = "core"; 2406 2407 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2408 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2409 reset-names = "apb", "core"; 2410 2411 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2412 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2413 interrupt-names = "intr", "msi"; 2414 2415 #interrupt-cells = <1>; 2416 interrupt-map-mask = <0 0 0 0>; 2417 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2418 2419 nvidia,bpmp = <&bpmp 1>; 2420 2421 nvidia,aspm-cmrt-us = <60>; 2422 nvidia,aspm-pwr-on-t-us = <20>; 2423 nvidia,aspm-l0s-entrance-latency-us = <3>; 2424 2425 bus-range = <0x0 0xff>; 2426 2427 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2428 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2429 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2430 2431 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2432 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2433 interconnect-names = "dma-mem", "write"; 2434 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2435 iommu-map-mask = <0x0>; 2436 dma-coherent; 2437 }; 2438 2439 pcie@14120000 { 2440 compatible = "nvidia,tegra194-pcie"; 2441 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2442 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2443 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2444 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2445 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2446 reg-names = "appl", "config", "atu_dma", "dbi"; 2447 2448 status = "disabled"; 2449 2450 #address-cells = <3>; 2451 #size-cells = <2>; 2452 device_type = "pci"; 2453 num-lanes = <1>; 2454 linux,pci-domain = <2>; 2455 2456 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2457 clock-names = "core"; 2458 2459 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2460 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2461 reset-names = "apb", "core"; 2462 2463 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2464 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2465 interrupt-names = "intr", "msi"; 2466 2467 #interrupt-cells = <1>; 2468 interrupt-map-mask = <0 0 0 0>; 2469 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2470 2471 nvidia,bpmp = <&bpmp 2>; 2472 2473 nvidia,aspm-cmrt-us = <60>; 2474 nvidia,aspm-pwr-on-t-us = <20>; 2475 nvidia,aspm-l0s-entrance-latency-us = <3>; 2476 2477 bus-range = <0x0 0xff>; 2478 2479 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2480 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2481 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2482 2483 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2484 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2485 interconnect-names = "dma-mem", "write"; 2486 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2487 iommu-map-mask = <0x0>; 2488 dma-coherent; 2489 }; 2490 2491 pcie@14140000 { 2492 compatible = "nvidia,tegra194-pcie"; 2493 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2494 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2495 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2496 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2497 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2498 reg-names = "appl", "config", "atu_dma", "dbi"; 2499 2500 status = "disabled"; 2501 2502 #address-cells = <3>; 2503 #size-cells = <2>; 2504 device_type = "pci"; 2505 num-lanes = <1>; 2506 linux,pci-domain = <3>; 2507 2508 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2509 clock-names = "core"; 2510 2511 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2512 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2513 reset-names = "apb", "core"; 2514 2515 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2516 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2517 interrupt-names = "intr", "msi"; 2518 2519 #interrupt-cells = <1>; 2520 interrupt-map-mask = <0 0 0 0>; 2521 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2522 2523 nvidia,bpmp = <&bpmp 3>; 2524 2525 nvidia,aspm-cmrt-us = <60>; 2526 nvidia,aspm-pwr-on-t-us = <20>; 2527 nvidia,aspm-l0s-entrance-latency-us = <3>; 2528 2529 bus-range = <0x0 0xff>; 2530 2531 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2532 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2533 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2534 2535 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2536 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2537 interconnect-names = "dma-mem", "write"; 2538 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2539 iommu-map-mask = <0x0>; 2540 dma-coherent; 2541 }; 2542 2543 pcie@14160000 { 2544 compatible = "nvidia,tegra194-pcie"; 2545 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2546 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2547 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2548 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2549 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2550 reg-names = "appl", "config", "atu_dma", "dbi"; 2551 2552 status = "disabled"; 2553 2554 #address-cells = <3>; 2555 #size-cells = <2>; 2556 device_type = "pci"; 2557 num-lanes = <4>; 2558 linux,pci-domain = <4>; 2559 2560 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2561 clock-names = "core"; 2562 2563 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2564 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2565 reset-names = "apb", "core"; 2566 2567 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2568 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2569 interrupt-names = "intr", "msi"; 2570 2571 #interrupt-cells = <1>; 2572 interrupt-map-mask = <0 0 0 0>; 2573 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2574 2575 nvidia,bpmp = <&bpmp 4>; 2576 2577 nvidia,aspm-cmrt-us = <60>; 2578 nvidia,aspm-pwr-on-t-us = <20>; 2579 nvidia,aspm-l0s-entrance-latency-us = <3>; 2580 2581 bus-range = <0x0 0xff>; 2582 2583 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2584 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2585 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2586 2587 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2588 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2589 interconnect-names = "dma-mem", "write"; 2590 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2591 iommu-map-mask = <0x0>; 2592 dma-coherent; 2593 }; 2594 2595 pcie@14180000 { 2596 compatible = "nvidia,tegra194-pcie"; 2597 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2598 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2599 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2600 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2601 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2602 reg-names = "appl", "config", "atu_dma", "dbi"; 2603 2604 status = "disabled"; 2605 2606 #address-cells = <3>; 2607 #size-cells = <2>; 2608 device_type = "pci"; 2609 num-lanes = <8>; 2610 linux,pci-domain = <0>; 2611 2612 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2613 clock-names = "core"; 2614 2615 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2616 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2617 reset-names = "apb", "core"; 2618 2619 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2620 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2621 interrupt-names = "intr", "msi"; 2622 2623 #interrupt-cells = <1>; 2624 interrupt-map-mask = <0 0 0 0>; 2625 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2626 2627 nvidia,bpmp = <&bpmp 0>; 2628 2629 nvidia,aspm-cmrt-us = <60>; 2630 nvidia,aspm-pwr-on-t-us = <20>; 2631 nvidia,aspm-l0s-entrance-latency-us = <3>; 2632 2633 bus-range = <0x0 0xff>; 2634 2635 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2636 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2637 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2638 2639 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2640 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2641 interconnect-names = "dma-mem", "write"; 2642 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2643 iommu-map-mask = <0x0>; 2644 dma-coherent; 2645 }; 2646 2647 pcie@141a0000 { 2648 compatible = "nvidia,tegra194-pcie"; 2649 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2650 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2651 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2652 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2653 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2654 reg-names = "appl", "config", "atu_dma", "dbi"; 2655 2656 status = "disabled"; 2657 2658 #address-cells = <3>; 2659 #size-cells = <2>; 2660 device_type = "pci"; 2661 num-lanes = <8>; 2662 linux,pci-domain = <5>; 2663 2664 pinctrl-names = "default"; 2665 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2666 2667 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2668 clock-names = "core"; 2669 2670 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2671 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2672 reset-names = "apb", "core"; 2673 2674 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2675 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2676 interrupt-names = "intr", "msi"; 2677 2678 nvidia,bpmp = <&bpmp 5>; 2679 2680 #interrupt-cells = <1>; 2681 interrupt-map-mask = <0 0 0 0>; 2682 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2683 2684 nvidia,aspm-cmrt-us = <60>; 2685 nvidia,aspm-pwr-on-t-us = <20>; 2686 nvidia,aspm-l0s-entrance-latency-us = <3>; 2687 2688 bus-range = <0x0 0xff>; 2689 2690 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2691 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2692 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2693 2694 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2695 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2696 interconnect-names = "dma-mem", "write"; 2697 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2698 iommu-map-mask = <0x0>; 2699 dma-coherent; 2700 }; 2701 2702 pcie-ep@14160000 { 2703 compatible = "nvidia,tegra194-pcie-ep"; 2704 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2705 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2706 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2707 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2708 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2709 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2710 2711 status = "disabled"; 2712 2713 num-lanes = <4>; 2714 num-ib-windows = <2>; 2715 num-ob-windows = <8>; 2716 2717 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2718 clock-names = "core"; 2719 2720 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2721 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2722 reset-names = "apb", "core"; 2723 2724 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2725 interrupt-names = "intr"; 2726 2727 nvidia,bpmp = <&bpmp 4>; 2728 2729 nvidia,aspm-cmrt-us = <60>; 2730 nvidia,aspm-pwr-on-t-us = <20>; 2731 nvidia,aspm-l0s-entrance-latency-us = <3>; 2732 2733 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2734 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2735 interconnect-names = "dma-mem", "write"; 2736 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2737 iommu-map-mask = <0x0>; 2738 dma-coherent; 2739 }; 2740 2741 pcie-ep@14180000 { 2742 compatible = "nvidia,tegra194-pcie-ep"; 2743 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2744 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2745 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2746 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2747 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2748 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2749 2750 status = "disabled"; 2751 2752 num-lanes = <8>; 2753 num-ib-windows = <2>; 2754 num-ob-windows = <8>; 2755 2756 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2757 clock-names = "core"; 2758 2759 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2760 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2761 reset-names = "apb", "core"; 2762 2763 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2764 interrupt-names = "intr"; 2765 2766 nvidia,bpmp = <&bpmp 0>; 2767 2768 nvidia,aspm-cmrt-us = <60>; 2769 nvidia,aspm-pwr-on-t-us = <20>; 2770 nvidia,aspm-l0s-entrance-latency-us = <3>; 2771 2772 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2773 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2774 interconnect-names = "dma-mem", "write"; 2775 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2776 iommu-map-mask = <0x0>; 2777 dma-coherent; 2778 }; 2779 2780 pcie-ep@141a0000 { 2781 compatible = "nvidia,tegra194-pcie-ep"; 2782 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2783 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2784 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2785 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2786 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2787 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2788 2789 status = "disabled"; 2790 2791 num-lanes = <8>; 2792 num-ib-windows = <2>; 2793 num-ob-windows = <8>; 2794 2795 pinctrl-names = "default"; 2796 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2797 2798 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2799 clock-names = "core"; 2800 2801 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2802 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2803 reset-names = "apb", "core"; 2804 2805 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2806 interrupt-names = "intr"; 2807 2808 nvidia,bpmp = <&bpmp 5>; 2809 2810 nvidia,aspm-cmrt-us = <60>; 2811 nvidia,aspm-pwr-on-t-us = <20>; 2812 nvidia,aspm-l0s-entrance-latency-us = <3>; 2813 2814 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2815 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2816 interconnect-names = "dma-mem", "write"; 2817 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2818 iommu-map-mask = <0x0>; 2819 dma-coherent; 2820 }; 2821 2822 sram@40000000 { 2823 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2824 reg = <0x0 0x40000000 0x0 0x50000>; 2825 #address-cells = <1>; 2826 #size-cells = <1>; 2827 ranges = <0x0 0x0 0x40000000 0x50000>; 2828 no-memory-wc; 2829 2830 cpu_bpmp_tx: sram@4e000 { 2831 reg = <0x4e000 0x1000>; 2832 label = "cpu-bpmp-tx"; 2833 pool; 2834 }; 2835 2836 cpu_bpmp_rx: sram@4f000 { 2837 reg = <0x4f000 0x1000>; 2838 label = "cpu-bpmp-rx"; 2839 pool; 2840 }; 2841 }; 2842 2843 bpmp: bpmp { 2844 compatible = "nvidia,tegra186-bpmp"; 2845 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2846 TEGRA_HSP_DB_MASTER_BPMP>; 2847 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2848 #clock-cells = <1>; 2849 #reset-cells = <1>; 2850 #power-domain-cells = <1>; 2851 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2852 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2853 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2854 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2855 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2856 iommus = <&smmu TEGRA194_SID_BPMP>; 2857 2858 bpmp_i2c: i2c { 2859 compatible = "nvidia,tegra186-bpmp-i2c"; 2860 nvidia,bpmp-bus-id = <5>; 2861 #address-cells = <1>; 2862 #size-cells = <0>; 2863 }; 2864 2865 bpmp_thermal: thermal { 2866 compatible = "nvidia,tegra186-bpmp-thermal"; 2867 #thermal-sensor-cells = <1>; 2868 }; 2869 }; 2870 2871 cpus { 2872 compatible = "nvidia,tegra194-ccplex"; 2873 nvidia,bpmp = <&bpmp>; 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 2877 cpu0_0: cpu@0 { 2878 compatible = "nvidia,tegra194-carmel"; 2879 device_type = "cpu"; 2880 reg = <0x000>; 2881 enable-method = "psci"; 2882 i-cache-size = <131072>; 2883 i-cache-line-size = <64>; 2884 i-cache-sets = <512>; 2885 d-cache-size = <65536>; 2886 d-cache-line-size = <64>; 2887 d-cache-sets = <256>; 2888 next-level-cache = <&l2c_0>; 2889 }; 2890 2891 cpu0_1: cpu@1 { 2892 compatible = "nvidia,tegra194-carmel"; 2893 device_type = "cpu"; 2894 reg = <0x001>; 2895 enable-method = "psci"; 2896 i-cache-size = <131072>; 2897 i-cache-line-size = <64>; 2898 i-cache-sets = <512>; 2899 d-cache-size = <65536>; 2900 d-cache-line-size = <64>; 2901 d-cache-sets = <256>; 2902 next-level-cache = <&l2c_0>; 2903 }; 2904 2905 cpu1_0: cpu@100 { 2906 compatible = "nvidia,tegra194-carmel"; 2907 device_type = "cpu"; 2908 reg = <0x100>; 2909 enable-method = "psci"; 2910 i-cache-size = <131072>; 2911 i-cache-line-size = <64>; 2912 i-cache-sets = <512>; 2913 d-cache-size = <65536>; 2914 d-cache-line-size = <64>; 2915 d-cache-sets = <256>; 2916 next-level-cache = <&l2c_1>; 2917 }; 2918 2919 cpu1_1: cpu@101 { 2920 compatible = "nvidia,tegra194-carmel"; 2921 device_type = "cpu"; 2922 reg = <0x101>; 2923 enable-method = "psci"; 2924 i-cache-size = <131072>; 2925 i-cache-line-size = <64>; 2926 i-cache-sets = <512>; 2927 d-cache-size = <65536>; 2928 d-cache-line-size = <64>; 2929 d-cache-sets = <256>; 2930 next-level-cache = <&l2c_1>; 2931 }; 2932 2933 cpu2_0: cpu@200 { 2934 compatible = "nvidia,tegra194-carmel"; 2935 device_type = "cpu"; 2936 reg = <0x200>; 2937 enable-method = "psci"; 2938 i-cache-size = <131072>; 2939 i-cache-line-size = <64>; 2940 i-cache-sets = <512>; 2941 d-cache-size = <65536>; 2942 d-cache-line-size = <64>; 2943 d-cache-sets = <256>; 2944 next-level-cache = <&l2c_2>; 2945 }; 2946 2947 cpu2_1: cpu@201 { 2948 compatible = "nvidia,tegra194-carmel"; 2949 device_type = "cpu"; 2950 reg = <0x201>; 2951 enable-method = "psci"; 2952 i-cache-size = <131072>; 2953 i-cache-line-size = <64>; 2954 i-cache-sets = <512>; 2955 d-cache-size = <65536>; 2956 d-cache-line-size = <64>; 2957 d-cache-sets = <256>; 2958 next-level-cache = <&l2c_2>; 2959 }; 2960 2961 cpu3_0: cpu@300 { 2962 compatible = "nvidia,tegra194-carmel"; 2963 device_type = "cpu"; 2964 reg = <0x300>; 2965 enable-method = "psci"; 2966 i-cache-size = <131072>; 2967 i-cache-line-size = <64>; 2968 i-cache-sets = <512>; 2969 d-cache-size = <65536>; 2970 d-cache-line-size = <64>; 2971 d-cache-sets = <256>; 2972 next-level-cache = <&l2c_3>; 2973 }; 2974 2975 cpu3_1: cpu@301 { 2976 compatible = "nvidia,tegra194-carmel"; 2977 device_type = "cpu"; 2978 reg = <0x301>; 2979 enable-method = "psci"; 2980 i-cache-size = <131072>; 2981 i-cache-line-size = <64>; 2982 i-cache-sets = <512>; 2983 d-cache-size = <65536>; 2984 d-cache-line-size = <64>; 2985 d-cache-sets = <256>; 2986 next-level-cache = <&l2c_3>; 2987 }; 2988 2989 cpu-map { 2990 cluster0 { 2991 core0 { 2992 cpu = <&cpu0_0>; 2993 }; 2994 2995 core1 { 2996 cpu = <&cpu0_1>; 2997 }; 2998 }; 2999 3000 cluster1 { 3001 core0 { 3002 cpu = <&cpu1_0>; 3003 }; 3004 3005 core1 { 3006 cpu = <&cpu1_1>; 3007 }; 3008 }; 3009 3010 cluster2 { 3011 core0 { 3012 cpu = <&cpu2_0>; 3013 }; 3014 3015 core1 { 3016 cpu = <&cpu2_1>; 3017 }; 3018 }; 3019 3020 cluster3 { 3021 core0 { 3022 cpu = <&cpu3_0>; 3023 }; 3024 3025 core1 { 3026 cpu = <&cpu3_1>; 3027 }; 3028 }; 3029 }; 3030 3031 l2c_0: l2-cache0 { 3032 cache-size = <2097152>; 3033 cache-line-size = <64>; 3034 cache-sets = <2048>; 3035 next-level-cache = <&l3c>; 3036 }; 3037 3038 l2c_1: l2-cache1 { 3039 cache-size = <2097152>; 3040 cache-line-size = <64>; 3041 cache-sets = <2048>; 3042 next-level-cache = <&l3c>; 3043 }; 3044 3045 l2c_2: l2-cache2 { 3046 cache-size = <2097152>; 3047 cache-line-size = <64>; 3048 cache-sets = <2048>; 3049 next-level-cache = <&l3c>; 3050 }; 3051 3052 l2c_3: l2-cache3 { 3053 cache-size = <2097152>; 3054 cache-line-size = <64>; 3055 cache-sets = <2048>; 3056 next-level-cache = <&l3c>; 3057 }; 3058 3059 l3c: l3-cache { 3060 cache-size = <4194304>; 3061 cache-line-size = <64>; 3062 cache-sets = <4096>; 3063 }; 3064 }; 3065 3066 pmu { 3067 compatible = "nvidia,carmel-pmu"; 3068 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3076 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3077 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3078 }; 3079 3080 psci { 3081 compatible = "arm,psci-1.0"; 3082 status = "okay"; 3083 method = "smc"; 3084 }; 3085 3086 sound { 3087 status = "disabled"; 3088 3089 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3090 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3091 clock-names = "pll_a", "plla_out0"; 3092 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3093 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3094 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3095 assigned-clock-parents = <0>, 3096 <&bpmp TEGRA194_CLK_PLLA>, 3097 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3098 /* 3099 * PLLA supports dynamic ramp. Below initial rate is chosen 3100 * for this to work and oscillate between base rates required 3101 * for 8x and 11.025x sample rate streams. 3102 */ 3103 assigned-clock-rates = <258000000>; 3104 }; 3105 3106 tcu: serial { 3107 compatible = "nvidia,tegra194-tcu"; 3108 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3109 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3110 mbox-names = "rx", "tx"; 3111 }; 3112 3113 thermal-zones { 3114 cpu-thermal { 3115 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3116 status = "disabled"; 3117 }; 3118 3119 gpu-thermal { 3120 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3121 status = "disabled"; 3122 }; 3123 3124 aux-thermal { 3125 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3126 status = "disabled"; 3127 }; 3128 3129 pllx-thermal { 3130 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3131 status = "disabled"; 3132 }; 3133 3134 ao-thermal { 3135 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3136 status = "disabled"; 3137 }; 3138 3139 tj-thermal { 3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3141 status = "disabled"; 3142 }; 3143 }; 3144 3145 timer { 3146 compatible = "arm,armv8-timer"; 3147 interrupts = <GIC_PPI 13 3148 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3149 <GIC_PPI 14 3150 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3151 <GIC_PPI 11 3152 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3153 <GIC_PPI 10 3154 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3155 interrupt-parent = <&gic>; 3156 always-on; 3157 }; 3158}; 3159