1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 /* system wide LDO 3.3V power rail */ 35 pp3300_z5: regulator-pp3300-ldo-z5 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pp3300_ldo_z5"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&ppvar_sys>; 43 }; 44 45 /* separately switched 3.3V power rail */ 46 pp3300_s3: regulator-pp3300-s3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "pp3300_s3"; 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&pp3300_z2>; 55 }; 56 57 /* system wide 3.3V power rail */ 58 pp3300_z2: regulator-pp3300-z2 { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_z2"; 61 /* EN pin tied to pp4200_z2, which is controlled by EC */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 /* system wide 4.2V power rail */ 70 pp4200_z2: regulator-pp4200-z2 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp4200_z2"; 73 /* controlled by EC */ 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <4200000>; 77 regulator-max-microvolt = <4200000>; 78 vin-supply = <&ppvar_sys>; 79 }; 80 81 /* system wide switching 5.0V power rail */ 82 pp5000_s5: regulator-pp5000-s5 { 83 compatible = "regulator-fixed"; 84 regulator-name = "pp5000_s5"; 85 /* controlled by EC */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 /* system wide semi-regulated power rail from battery or USB */ 94 ppvar_sys: regulator-ppvar-sys { 95 compatible = "regulator-fixed"; 96 regulator-name = "ppvar_sys"; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 usb_vbus: regulator-5v0-usb-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "usb-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reserved_memory: reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 scp_mem: memory@50000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x50000000 0 0x2900000>; 118 no-map; 119 }; 120 }; 121}; 122 123&i2c0 { 124 status = "okay"; 125 126 clock-frequency = <400000>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&i2c0_pins>; 129}; 130 131&i2c1 { 132 status = "okay"; 133 134 clock-frequency = <400000>; 135 i2c-scl-internal-delay-ns = <12500>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&i2c1_pins>; 138 139 trackpad@15 { 140 compatible = "elan,ekth3000"; 141 reg = <0x15>; 142 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&trackpad_pins>; 145 vcc-supply = <&pp3300_s3>; 146 wakeup-source; 147 }; 148}; 149 150&i2c2 { 151 status = "okay"; 152 153 clock-frequency = <400000>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&i2c2_pins>; 156}; 157 158&i2c3 { 159 status = "okay"; 160 161 clock-frequency = <400000>; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&i2c3_pins>; 164 165 tpm@50 { 166 compatible = "google,cr50"; 167 reg = <0x50>; 168 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&cr50_int>; 171 }; 172}; 173 174&i2c4 { 175 status = "okay"; 176 177 clock-frequency = <400000>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&i2c4_pins>; 180 181 ts_10: touchscreen@10 { 182 compatible = "hid-over-i2c"; 183 reg = <0x10>; 184 hid-descr-addr = <0x0001>; 185 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&touchscreen_pins>; 188 post-power-on-delay-ms = <10>; 189 vdd-supply = <&pp3300_s3>; 190 status = "disabled"; 191 }; 192}; 193 194&i2c5 { 195 status = "okay"; 196 197 clock-frequency = <400000>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&i2c5_pins>; 200}; 201 202&i2c7 { 203 status = "okay"; 204 205 clock-frequency = <400000>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&i2c7_pins>; 208 209 pmic@34 { 210 #interrupt-cells = <1>; 211 compatible = "mediatek,mt6360"; 212 reg = <0x34>; 213 interrupt-controller; 214 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 215 interrupt-names = "IRQB"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&subpmic_default>; 218 wakeup-source; 219 }; 220}; 221 222&mmc0 { 223 status = "okay"; 224 225 bus-width = <8>; 226 cap-mmc-highspeed; 227 cap-mmc-hw-reset; 228 hs400-ds-delay = <0x14c11>; 229 max-frequency = <200000000>; 230 mmc-hs200-1_8v; 231 mmc-hs400-1_8v; 232 no-sdio; 233 no-sd; 234 non-removable; 235 pinctrl-names = "default", "state_uhs"; 236 pinctrl-0 = <&mmc0_pins_default>; 237 pinctrl-1 = <&mmc0_pins_uhs>; 238 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 239 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 240}; 241 242&mmc1 { 243 status = "okay"; 244 245 bus-width = <4>; 246 cap-sd-highspeed; 247 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 248 max-frequency = <200000000>; 249 no-mmc; 250 no-sdio; 251 pinctrl-names = "default", "state_uhs"; 252 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 253 pinctrl-1 = <&mmc1_pins_default>; 254 sd-uhs-sdr50; 255 sd-uhs-sdr104; 256 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 257 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 258}; 259 260/* for CPU-L */ 261&mt6359_vcore_buck_reg { 262 regulator-always-on; 263}; 264 265/* for CORE */ 266&mt6359_vgpu11_buck_reg { 267 regulator-always-on; 268}; 269 270&mt6359_vgpu11_sshub_buck_reg { 271 regulator-always-on; 272 regulator-min-microvolt = <550000>; 273 regulator-max-microvolt = <550000>; 274}; 275 276/* for CORE SRAM */ 277&mt6359_vpu_buck_reg { 278 regulator-always-on; 279}; 280 281&mt6359_vrf12_ldo_reg { 282 regulator-always-on; 283}; 284 285/* for GPU SRAM */ 286&mt6359_vsram_others_ldo_reg { 287 regulator-always-on; 288 regulator-min-microvolt = <750000>; 289 regulator-max-microvolt = <750000>; 290}; 291 292&mt6359_vufs_ldo_reg { 293 regulator-always-on; 294}; 295 296&nor_flash { 297 status = "okay"; 298 299 pinctrl-names = "default"; 300 pinctrl-0 = <&nor_pins_default>; 301 302 flash@0 { 303 compatible = "jedec,spi-nor"; 304 reg = <0>; 305 spi-max-frequency = <52000000>; 306 spi-rx-bus-width = <2>; 307 spi-tx-bus-width = <2>; 308 }; 309}; 310 311&pio { 312 mediatek,rsel-resistance-in-si-unit; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pio_default>; 315 316 /* 144 lines */ 317 gpio-line-names = 318 "I2S_SPKR_MCLK", 319 "I2S_SPKR_DATAIN", 320 "I2S_SPKR_LRCK", 321 "I2S_SPKR_BCLK", 322 "EC_AP_INT_ODL", 323 /* 324 * AP_FLASH_WP_L is crossystem ABI. Schematics 325 * call it AP_FLASH_WP_ODL. 326 */ 327 "AP_FLASH_WP_L", 328 "TCHPAD_INT_ODL", 329 "EDP_HPD_1V8", 330 "AP_I2C_CAM_SDA", 331 "AP_I2C_CAM_SCL", 332 "AP_I2C_TCHPAD_SDA_1V8", 333 "AP_I2C_TCHPAD_SCL_1V8", 334 "AP_I2C_AUD_SDA", 335 "AP_I2C_AUD_SCL", 336 "AP_I2C_TPM_SDA_1V8", 337 "AP_I2C_TPM_SCL_1V8", 338 "AP_I2C_TCHSCR_SDA_1V8", 339 "AP_I2C_TCHSCR_SCL_1V8", 340 "EC_AP_HPD_OD", 341 "", 342 "PCIE_NVME_RST_L", 343 "PCIE_NVME_CLKREQ_ODL", 344 "PCIE_RST_1V8_L", 345 "PCIE_CLKREQ_1V8_ODL", 346 "PCIE_WAKE_1V8_ODL", 347 "CLK_24M_CAM0", 348 "CAM1_SEN_EN", 349 "AP_I2C_PWR_SCL_1V8", 350 "AP_I2C_PWR_SDA_1V8", 351 "AP_I2C_MISC_SCL", 352 "AP_I2C_MISC_SDA", 353 "EN_PP5000_HDMI_X", 354 "AP_HDMITX_HTPLG", 355 "", 356 "AP_HDMITX_SCL_1V8", 357 "AP_HDMITX_SDA_1V8", 358 "AP_RTC_CLK32K", 359 "AP_EC_WATCHDOG_L", 360 "SRCLKENA0", 361 "SRCLKENA1", 362 "PWRAP_SPI0_CS_L", 363 "PWRAP_SPI0_CK", 364 "PWRAP_SPI0_MOSI", 365 "PWRAP_SPI0_MISO", 366 "SPMI_SCL", 367 "SPMI_SDA", 368 "", 369 "", 370 "", 371 "I2S_HP_DATAIN", 372 "I2S_HP_MCLK", 373 "I2S_HP_BCK", 374 "I2S_HP_LRCK", 375 "I2S_HP_DATAOUT", 376 "SD_CD_ODL", 377 "EN_PP3300_DISP_X", 378 "TCHSCR_RST_1V8_L", 379 "TCHSCR_REPORT_DISABLE", 380 "EN_PP3300_WLAN_X", 381 "BT_KILL_1V8_L", 382 "I2S_SPKR_DATAOUT", 383 "WIFI_KILL_1V8_L", 384 "BEEP_ON", 385 "SCP_I2C_SENSOR_SCL_1V8", 386 "SCP_I2C_SENSOR_SDA_1V8", 387 "", 388 "", 389 "", 390 "", 391 "AUD_CLK_MOSI", 392 "AUD_SYNC_MOSI", 393 "AUD_DAT_MOSI0", 394 "AUD_DAT_MOSI1", 395 "AUD_DAT_MISO0", 396 "AUD_DAT_MISO1", 397 "AUD_DAT_MISO2", 398 "SCP_VREQ_VAO", 399 "AP_SPI_GSC_TPM_CLK", 400 "AP_SPI_GSC_TPM_MOSI", 401 "AP_SPI_GSC_TPM_CS_L", 402 "AP_SPI_GSC_TPM_MISO", 403 "EN_PP1000_CAM_X", 404 "AP_EDP_BKLTEN", 405 "", 406 "USB3_HUB_RST_L", 407 "", 408 "WLAN_ALERT_ODL", 409 "EC_IN_RW_ODL", 410 "GSC_AP_INT_ODL", 411 "HP_INT_ODL", 412 "CAM0_RST_L", 413 "CAM1_RST_L", 414 "TCHSCR_INT_1V8_L", 415 "CAM1_DET_L", 416 "RST_ALC1011_L", 417 "", 418 "", 419 "BL_PWM_1V8", 420 "UART_AP_TX_DBG_RX", 421 "UART_DBG_TX_AP_RX", 422 "EN_SPKR", 423 "AP_EC_WARM_RST_REQ", 424 "UART_SCP_TX_DBGCON_RX", 425 "UART_DBGCON_TX_SCP_RX", 426 "", 427 "", 428 "KPCOL0", 429 "", 430 "MT6315_GPU_INT", 431 "MT6315_PROC_BC_INT", 432 "SD_CMD", 433 "SD_CLK", 434 "SD_DAT0", 435 "SD_DAT1", 436 "SD_DAT2", 437 "SD_DAT3", 438 "EMMC_DAT7", 439 "EMMC_DAT6", 440 "EMMC_DAT5", 441 "EMMC_DAT4", 442 "EMMC_RSTB", 443 "EMMC_CMD", 444 "EMMC_CLK", 445 "EMMC_DAT3", 446 "EMMC_DAT2", 447 "EMMC_DAT1", 448 "EMMC_DAT0", 449 "EMMC_DSL", 450 "", 451 "", 452 "MT6360_INT_ODL", 453 "SCP_JTAG0_TRSTN", 454 "AP_SPI_EC_CS_L", 455 "AP_SPI_EC_CLK", 456 "AP_SPI_EC_MOSI", 457 "AP_SPI_EC_MISO", 458 "SCP_JTAG0_TMS", 459 "SCP_JTAG0_TCK", 460 "SCP_JTAG0_TDO", 461 "SCP_JTAG0_TDI", 462 "AP_SPI_FLASH_CS_L", 463 "AP_SPI_FLASH_CLK", 464 "AP_SPI_FLASH_MOSI", 465 "AP_SPI_FLASH_MISO"; 466 467 cr50_int: cr50-irq-default-pins { 468 pins-gsc-ap-int-odl { 469 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 470 input-enable; 471 }; 472 }; 473 474 cros_ec_int: cros-ec-irq-default-pins { 475 pins-ec-ap-int-odl { 476 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 477 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 478 input-enable; 479 }; 480 }; 481 482 i2c0_pins: i2c0-default-pins { 483 pins-bus { 484 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 485 <PINMUX_GPIO9__FUNC_SCL0>; 486 bias-disable; 487 drive-strength-microamp = <1000>; 488 }; 489 }; 490 491 i2c1_pins: i2c1-default-pins { 492 pins-bus { 493 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 494 <PINMUX_GPIO11__FUNC_SCL1>; 495 bias-pull-up = <1000>; 496 drive-strength-microamp = <1000>; 497 }; 498 }; 499 500 i2c2_pins: i2c2-default-pins { 501 pins-bus { 502 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 503 <PINMUX_GPIO13__FUNC_SCL2>; 504 bias-disable; 505 drive-strength-microamp = <1000>; 506 }; 507 }; 508 509 i2c3_pins: i2c3-default-pins { 510 pins-bus { 511 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 512 <PINMUX_GPIO15__FUNC_SCL3>; 513 bias-pull-up = <1000>; 514 drive-strength-microamp = <1000>; 515 }; 516 }; 517 518 i2c4_pins: i2c4-default-pins { 519 pins-bus { 520 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 521 <PINMUX_GPIO17__FUNC_SCL4>; 522 bias-pull-up = <1000>; 523 drive-strength = <4>; 524 }; 525 }; 526 527 i2c5_pins: i2c5-default-pins { 528 pins-bus { 529 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 530 <PINMUX_GPIO30__FUNC_SDA5>; 531 bias-disable; 532 drive-strength-microamp = <1000>; 533 }; 534 }; 535 536 i2c7_pins: i2c7-default-pins { 537 pins-bus { 538 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 539 <PINMUX_GPIO28__FUNC_SDA7>; 540 bias-disable; 541 }; 542 }; 543 544 mmc0_pins_default: mmc0-default-pins { 545 pins-cmd-dat { 546 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 547 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 548 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 549 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 550 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 551 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 552 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 553 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 554 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 555 input-enable; 556 drive-strength = <6>; 557 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 558 }; 559 560 pins-clk { 561 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 562 drive-strength = <6>; 563 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 564 }; 565 566 pins-rst { 567 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 568 drive-strength = <6>; 569 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 570 }; 571 }; 572 573 mmc0_pins_uhs: mmc0-uhs-pins { 574 pins-cmd-dat { 575 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 576 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 577 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 578 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 579 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 580 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 581 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 582 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 583 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 584 input-enable; 585 drive-strength = <8>; 586 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 587 }; 588 589 pins-clk { 590 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 591 drive-strength = <8>; 592 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 593 }; 594 595 pins-ds { 596 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 597 drive-strength = <8>; 598 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 599 }; 600 601 pins-rst { 602 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 603 drive-strength = <8>; 604 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 605 }; 606 }; 607 608 mmc1_pins_detect: mmc1-detect-pins { 609 pins-insert { 610 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 611 bias-pull-up; 612 }; 613 }; 614 615 mmc1_pins_default: mmc1-default-pins { 616 pins-cmd-dat { 617 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 618 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 619 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 620 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 621 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 622 input-enable; 623 drive-strength = <8>; 624 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 625 }; 626 627 pins-clk { 628 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 629 drive-strength = <8>; 630 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 631 }; 632 }; 633 634 nor_pins_default: nor-default-pins { 635 pins-ck-io { 636 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 637 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 638 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 639 drive-strength = <6>; 640 bias-pull-down; 641 }; 642 643 pins-cs { 644 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 645 drive-strength = <6>; 646 bias-pull-up; 647 }; 648 }; 649 650 pio_default: pio-default-pins { 651 pins-wifi-enable { 652 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 653 output-high; 654 drive-strength = <14>; 655 }; 656 657 pins-low-power-pd { 658 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 659 <PINMUX_GPIO26__FUNC_GPIO26>, 660 <PINMUX_GPIO46__FUNC_GPIO46>, 661 <PINMUX_GPIO47__FUNC_GPIO47>, 662 <PINMUX_GPIO48__FUNC_GPIO48>, 663 <PINMUX_GPIO65__FUNC_GPIO65>, 664 <PINMUX_GPIO66__FUNC_GPIO66>, 665 <PINMUX_GPIO67__FUNC_GPIO67>, 666 <PINMUX_GPIO68__FUNC_GPIO68>, 667 <PINMUX_GPIO128__FUNC_GPIO128>, 668 <PINMUX_GPIO129__FUNC_GPIO129>; 669 input-enable; 670 bias-pull-down; 671 }; 672 673 pins-low-power-pupd { 674 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 675 <PINMUX_GPIO78__FUNC_GPIO78>, 676 <PINMUX_GPIO79__FUNC_GPIO79>, 677 <PINMUX_GPIO80__FUNC_GPIO80>, 678 <PINMUX_GPIO83__FUNC_GPIO83>, 679 <PINMUX_GPIO85__FUNC_GPIO85>, 680 <PINMUX_GPIO90__FUNC_GPIO90>, 681 <PINMUX_GPIO91__FUNC_GPIO91>, 682 <PINMUX_GPIO93__FUNC_GPIO93>, 683 <PINMUX_GPIO94__FUNC_GPIO94>, 684 <PINMUX_GPIO95__FUNC_GPIO95>, 685 <PINMUX_GPIO96__FUNC_GPIO96>, 686 <PINMUX_GPIO104__FUNC_GPIO104>, 687 <PINMUX_GPIO105__FUNC_GPIO105>, 688 <PINMUX_GPIO107__FUNC_GPIO107>; 689 input-enable; 690 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 691 }; 692 }; 693 694 scp_pins: scp-default-pins { 695 pins-vreq { 696 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 697 bias-disable; 698 input-enable; 699 }; 700 }; 701 702 spi0_pins: spi0-default-pins { 703 pins-cs-mosi-clk { 704 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 705 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 706 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 707 bias-disable; 708 }; 709 710 pins-miso { 711 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 712 bias-pull-down; 713 }; 714 }; 715 716 subpmic_default: subpmic-default-pins { 717 subpmic_pin_irq: pins-subpmic-int-n { 718 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 719 input-enable; 720 bias-pull-up; 721 }; 722 }; 723 724 trackpad_pins: trackpad-default-pins { 725 pins-int-n { 726 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 727 input-enable; 728 bias-pull-up; 729 }; 730 }; 731 732 touchscreen_pins: touchscreen-default-pins { 733 pins-int-n { 734 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 735 input-enable; 736 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 737 }; 738 pins-rst { 739 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 740 output-high; 741 }; 742 pins-report-sw { 743 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 744 output-low; 745 }; 746 }; 747}; 748 749&pmic { 750 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 751}; 752 753&scp { 754 status = "okay"; 755 756 firmware-name = "mediatek/mt8195/scp.img"; 757 memory-region = <&scp_mem>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&scp_pins>; 760 761 cros-ec-rpmsg { 762 compatible = "google,cros-ec-rpmsg"; 763 mediatek,rpmsg-name = "cros-ec-rpmsg"; 764 }; 765}; 766 767&spi0 { 768 status = "okay"; 769 770 pinctrl-names = "default"; 771 pinctrl-0 = <&spi0_pins>; 772 mediatek,pad-select = <0>; 773 774 cros_ec: ec@0 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 compatible = "google,cros-ec-spi"; 779 reg = <0>; 780 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&cros_ec_int>; 783 spi-max-frequency = <3000000>; 784 785 keyboard-backlight { 786 compatible = "google,cros-kbd-led-backlight"; 787 }; 788 789 i2c_tunnel: i2c-tunnel { 790 compatible = "google,cros-ec-i2c-tunnel"; 791 google,remote-bus = <0>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 }; 795 796 mt_pmic_vmc_ldo_reg: regulator@0 { 797 compatible = "google,cros-ec-regulator"; 798 reg = <0>; 799 regulator-name = "mt_pmic_vmc_ldo"; 800 regulator-min-microvolt = <1200000>; 801 regulator-max-microvolt = <3600000>; 802 }; 803 804 mt_pmic_vmch_ldo_reg: regulator@1 { 805 compatible = "google,cros-ec-regulator"; 806 reg = <1>; 807 regulator-name = "mt_pmic_vmch_ldo"; 808 regulator-min-microvolt = <2700000>; 809 regulator-max-microvolt = <3600000>; 810 }; 811 812 typec { 813 compatible = "google,cros-ec-typec"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 817 usb_c0: connector@0 { 818 compatible = "usb-c-connector"; 819 reg = <0>; 820 power-role = "dual"; 821 data-role = "host"; 822 try-power-role = "source"; 823 }; 824 825 usb_c1: connector@1 { 826 compatible = "usb-c-connector"; 827 reg = <1>; 828 power-role = "dual"; 829 data-role = "host"; 830 try-power-role = "source"; 831 }; 832 }; 833 }; 834}; 835 836&spmi { 837 #address-cells = <2>; 838 #size-cells = <0>; 839 840 mt6315@6 { 841 compatible = "mediatek,mt6315-regulator"; 842 reg = <0x6 SPMI_USID>; 843 844 regulators { 845 mt6315_6_vbuck1: vbuck1 { 846 regulator-compatible = "vbuck1"; 847 regulator-name = "Vbcpu"; 848 regulator-min-microvolt = <300000>; 849 regulator-max-microvolt = <1193750>; 850 regulator-enable-ramp-delay = <256>; 851 regulator-ramp-delay = <6250>; 852 regulator-allowed-modes = <0 1 2>; 853 regulator-always-on; 854 }; 855 }; 856 }; 857 858 mt6315@7 { 859 compatible = "mediatek,mt6315-regulator"; 860 reg = <0x7 SPMI_USID>; 861 862 regulators { 863 mt6315_7_vbuck1: vbuck1 { 864 regulator-compatible = "vbuck1"; 865 regulator-name = "Vgpu"; 866 regulator-min-microvolt = <625000>; 867 regulator-max-microvolt = <1193750>; 868 regulator-enable-ramp-delay = <256>; 869 regulator-ramp-delay = <6250>; 870 regulator-allowed-modes = <0 1 2>; 871 regulator-always-on; 872 }; 873 }; 874 }; 875}; 876 877&u3phy0 { 878 status = "okay"; 879}; 880 881&u3phy1 { 882 status = "okay"; 883}; 884 885&u3phy2 { 886 status = "okay"; 887}; 888 889&u3phy3 { 890 status = "okay"; 891}; 892 893&uart0 { 894 status = "okay"; 895}; 896 897&xhci0 { 898 status = "okay"; 899 900 vusb33-supply = <&mt6359_vusb_ldo_reg>; 901 vbus-supply = <&usb_vbus>; 902}; 903 904&xhci1 { 905 status = "okay"; 906 907 vusb33-supply = <&mt6359_vusb_ldo_reg>; 908 vbus-supply = <&usb_vbus>; 909}; 910 911&xhci2 { 912 status = "okay"; 913 914 vusb33-supply = <&mt6359_vusb_ldo_reg>; 915 vbus-supply = <&usb_vbus>; 916}; 917 918&xhci3 { 919 status = "okay"; 920 921 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 922 usb2-lpm-disable; 923 vusb33-supply = <&mt6359_vusb_ldo_reg>; 924 vbus-supply = <&usb_vbus>; 925}; 926 927#include <arm/cros-ec-keyboard.dtsi> 928#include <arm/cros-ec-sbs.dtsi> 929 930&keyboard_controller { 931 function-row-physmap = < 932 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 933 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 934 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 935 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 936 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 937 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 938 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 939 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 940 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 941 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 942 >; 943 944 linux,keymap = < 945 MATRIX_KEY(0x00, 0x02, KEY_BACK) 946 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 947 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 948 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 949 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 950 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 951 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 952 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 953 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 954 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 955 956 CROS_STD_MAIN_KEYMAP 957 >; 958}; 959