1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7904 i.MX8MM board"; 17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 memory@40000000 { 24 device_type = "memory"; 25 reg = <0x0 0x40000000 0 0x80000000>; 26 }; 27 28 gpio-keys { 29 compatible = "gpio-keys"; 30 31 key-0 { 32 label = "user_pb"; 33 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 34 linux,code = <BTN_0>; 35 }; 36 37 key-1 { 38 label = "user_pb1x"; 39 linux,code = <BTN_1>; 40 interrupt-parent = <&gsc>; 41 interrupts = <0>; 42 }; 43 44 key-2 { 45 label = "key_erased"; 46 linux,code = <BTN_2>; 47 interrupt-parent = <&gsc>; 48 interrupts = <1>; 49 }; 50 51 key-3 { 52 label = "eeprom_wp"; 53 linux,code = <BTN_3>; 54 interrupt-parent = <&gsc>; 55 interrupts = <2>; 56 }; 57 58 key-4 { 59 label = "switch_hold"; 60 linux,code = <BTN_5>; 61 interrupt-parent = <&gsc>; 62 interrupts = <7>; 63 }; 64 }; 65 66 led-controller { 67 compatible = "gpio-leds"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_gpio_leds>; 70 71 led-0 { 72 function = LED_FUNCTION_STATUS; 73 color = <LED_COLOR_ID_GREEN>; 74 label = "led01_grn"; 75 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>; 76 default-state = "off"; 77 }; 78 79 led-1 { 80 function = LED_FUNCTION_STATUS; 81 color = <LED_COLOR_ID_YELLOW>; 82 label = "led01_yel"; 83 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>; 84 default-state = "off"; 85 }; 86 87 led-2 { 88 function = LED_FUNCTION_STATUS; 89 color = <LED_COLOR_ID_GREEN>; 90 label = "led02_grn"; 91 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>; 92 default-state = "off"; 93 }; 94 95 led-3 { 96 function = LED_FUNCTION_STATUS; 97 color = <LED_COLOR_ID_YELLOW>; 98 label = "led02_yel"; 99 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>; 100 default-state = "off"; 101 }; 102 103 led-4 { 104 function = LED_FUNCTION_STATUS; 105 color = <LED_COLOR_ID_GREEN>; 106 label = "led03_grn"; 107 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>; 108 default-state = "off"; 109 }; 110 111 led-5 { 112 function = LED_FUNCTION_STATUS; 113 color = <LED_COLOR_ID_YELLOW>; 114 label = "led03_yel"; 115 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>; 116 default-state = "off"; 117 }; 118 119 led-6 { 120 function = LED_FUNCTION_STATUS; 121 color = <LED_COLOR_ID_GREEN>; 122 label = "led04_grn"; 123 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>; 124 default-state = "off"; 125 }; 126 127 led-7 { 128 function = LED_FUNCTION_STATUS; 129 color = <LED_COLOR_ID_YELLOW>; 130 label = "led04_yel"; 131 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>; 132 default-state = "off"; 133 }; 134 135 led-8 { 136 function = LED_FUNCTION_STATUS; 137 color = <LED_COLOR_ID_GREEN>; 138 label = "led05_grn"; 139 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>; 140 default-state = "off"; 141 }; 142 143 led-9 { 144 function = LED_FUNCTION_STATUS; 145 color = <LED_COLOR_ID_YELLOW>; 146 label = "led05_yel"; 147 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>; 148 default-state = "off"; 149 }; 150 151 led-10 { 152 function = LED_FUNCTION_STATUS; 153 color = <LED_COLOR_ID_GREEN>; 154 label = "led06_grn"; 155 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 156 default-state = "off"; 157 }; 158 159 led-11 { 160 function = LED_FUNCTION_STATUS; 161 color = <LED_COLOR_ID_RED>; 162 label = "led06_red"; 163 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 164 default-state = "off"; 165 }; 166 167 led-12 { 168 function = LED_FUNCTION_STATUS; 169 color = <LED_COLOR_ID_GREEN>; 170 label = "led07_grn"; 171 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 172 default-state = "off"; 173 }; 174 175 led-13 { 176 function = LED_FUNCTION_STATUS; 177 color = <LED_COLOR_ID_RED>; 178 label = "led07_red"; 179 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 180 default-state = "off"; 181 }; 182 183 led-14 { 184 function = LED_FUNCTION_STATUS; 185 color = <LED_COLOR_ID_GREEN>; 186 label = "led08_grn"; 187 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>; 188 default-state = "off"; 189 }; 190 191 led-15 { 192 function = LED_FUNCTION_STATUS; 193 color = <LED_COLOR_ID_YELLOW>; 194 label = "led08_yel"; 195 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>; 196 default-state = "off"; 197 }; 198 199 led-16 { 200 function = LED_FUNCTION_STATUS; 201 color = <LED_COLOR_ID_GREEN>; 202 label = "led09_grn"; 203 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>; 204 default-state = "off"; 205 }; 206 207 led-17 { 208 function = LED_FUNCTION_STATUS; 209 color = <LED_COLOR_ID_YELLOW>; 210 label = "led09_yel"; 211 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>; 212 default-state = "off"; 213 }; 214 215 led-18 { 216 function = LED_FUNCTION_STATUS; 217 color = <LED_COLOR_ID_GREEN>; 218 label = "led10_grn"; 219 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>; 220 default-state = "off"; 221 }; 222 223 led-19 { 224 function = LED_FUNCTION_STATUS; 225 color = <LED_COLOR_ID_YELLOW>; 226 label = "led10_yel"; 227 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>; 228 default-state = "off"; 229 }; 230 }; 231 232 pcie0_refclk: pcie0-refclk { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 clock-frequency = <100000000>; 236 }; 237 238 reg_3p3v: regulator-3p3v { 239 compatible = "regulator-fixed"; 240 regulator-name = "3P3V"; 241 regulator-min-microvolt = <3300000>; 242 regulator-max-microvolt = <3300000>; 243 regulator-always-on; 244 }; 245}; 246 247&A53_0 { 248 cpu-supply = <&buck2>; 249}; 250 251&A53_1 { 252 cpu-supply = <&buck2>; 253}; 254 255&A53_2 { 256 cpu-supply = <&buck2>; 257}; 258 259&A53_3 { 260 cpu-supply = <&buck2>; 261}; 262 263&ddrc { 264 operating-points-v2 = <&ddrc_opp_table>; 265 266 ddrc_opp_table: opp-table { 267 compatible = "operating-points-v2"; 268 269 opp-25M { 270 opp-hz = /bits/ 64 <25000000>; 271 }; 272 273 opp-100M { 274 opp-hz = /bits/ 64 <100000000>; 275 }; 276 277 opp-750M { 278 opp-hz = /bits/ 64 <750000000>; 279 }; 280 }; 281}; 282 283&fec1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_fec1>; 286 phy-mode = "rgmii-id"; 287 phy-handle = <ðphy0>; 288 local-mac-address = [00 00 00 00 00 00]; 289 status = "okay"; 290 291 mdio { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 ethphy0: ethernet-phy@0 { 296 compatible = "ethernet-phy-ieee802.3-c22"; 297 reg = <0>; 298 }; 299 }; 300}; 301 302&gpio1 { 303 gpio-line-names = "", "", "", "", "", "", "", "", 304 "", "", "", "", "rs232_en#", "", "", "", 305 "", "", "", "", "", "", "", "", 306 "", "", "", "", "", "", "", ""; 307}; 308 309&gpio5 { 310 gpio-line-names = "", "", "", "", "", "", "", "", 311 "", "", "", "", "pci_wdis#", "", "", "", 312 "", "", "", "", "", "", "", "", 313 "", "", "", "", "", "", "", ""; 314}; 315 316&i2c1 { 317 clock-frequency = <100000>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_i2c1>; 320 status = "okay"; 321 322 gsc: gsc@20 { 323 compatible = "gw,gsc"; 324 reg = <0x20>; 325 pinctrl-0 = <&pinctrl_gsc>; 326 interrupt-parent = <&gpio4>; 327 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 328 interrupt-controller; 329 #interrupt-cells = <1>; 330 331 adc { 332 compatible = "gw,gsc-adc"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 channel@6 { 337 gw,mode = <0>; 338 reg = <0x06>; 339 label = "temp"; 340 }; 341 342 channel@82 { 343 gw,mode = <2>; 344 reg = <0x82>; 345 label = "vin"; 346 gw,voltage-divider-ohms = <22100 1000>; 347 gw,voltage-offset-microvolt = <700000>; 348 }; 349 350 channel@84 { 351 gw,mode = <2>; 352 reg = <0x84>; 353 label = "vdd_5p0"; 354 gw,voltage-divider-ohms = <10000 10000>; 355 }; 356 357 channel@86 { 358 gw,mode = <2>; 359 reg = <0x86>; 360 label = "vdd_3p3"; 361 gw,voltage-divider-ohms = <10000 10000>; 362 }; 363 364 channel@88 { 365 gw,mode = <2>; 366 reg = <0x88>; 367 label = "vdd_0p9"; 368 }; 369 370 channel@8c { 371 gw,mode = <2>; 372 reg = <0x8c>; 373 label = "vdd_soc"; 374 }; 375 376 channel@8e { 377 gw,mode = <2>; 378 reg = <0x8e>; 379 label = "vdd_arm"; 380 }; 381 382 channel@90 { 383 gw,mode = <2>; 384 reg = <0x90>; 385 label = "vdd_1p8"; 386 }; 387 388 channel@92 { 389 gw,mode = <2>; 390 reg = <0x92>; 391 label = "vdd_dram"; 392 }; 393 394 channel@a2 { 395 gw,mode = <2>; 396 reg = <0xa2>; 397 label = "vdd_gsc"; 398 gw,voltage-divider-ohms = <10000 10000>; 399 }; 400 }; 401 }; 402 403 gpio: gpio@23 { 404 compatible = "nxp,pca9555"; 405 reg = <0x23>; 406 gpio-controller; 407 #gpio-cells = <2>; 408 interrupt-parent = <&gsc>; 409 interrupts = <4>; 410 }; 411 412 eeprom@50 { 413 compatible = "atmel,24c02"; 414 reg = <0x50>; 415 pagesize = <16>; 416 }; 417 418 eeprom@51 { 419 compatible = "atmel,24c02"; 420 reg = <0x51>; 421 pagesize = <16>; 422 }; 423 424 eeprom@52 { 425 compatible = "atmel,24c02"; 426 reg = <0x52>; 427 pagesize = <16>; 428 }; 429 430 eeprom@53 { 431 compatible = "atmel,24c02"; 432 reg = <0x53>; 433 pagesize = <16>; 434 }; 435 436 rtc@68 { 437 compatible = "dallas,ds1672"; 438 reg = <0x68>; 439 }; 440}; 441 442&i2c2 { 443 clock-frequency = <400000>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_i2c2>; 446 status = "okay"; 447 448 pmic@4b { 449 compatible = "rohm,bd71847"; 450 reg = <0x4b>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_pmic>; 453 interrupt-parent = <&gpio3>; 454 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 455 rohm,reset-snvs-powered; 456 #clock-cells = <0>; 457 clocks = <&osc_32k 0>; 458 clock-output-names = "clk-32k-out"; 459 460 regulators { 461 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 462 BUCK1 { 463 regulator-name = "buck1"; 464 regulator-min-microvolt = <700000>; 465 regulator-max-microvolt = <1300000>; 466 regulator-boot-on; 467 regulator-always-on; 468 regulator-ramp-delay = <1250>; 469 }; 470 471 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 472 buck2: BUCK2 { 473 regulator-name = "buck2"; 474 regulator-min-microvolt = <700000>; 475 regulator-max-microvolt = <1300000>; 476 regulator-boot-on; 477 regulator-always-on; 478 regulator-ramp-delay = <1250>; 479 rohm,dvs-run-voltage = <1000000>; 480 rohm,dvs-idle-voltage = <900000>; 481 }; 482 483 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 484 BUCK3 { 485 regulator-name = "buck3"; 486 regulator-min-microvolt = <700000>; 487 regulator-max-microvolt = <1350000>; 488 regulator-boot-on; 489 regulator-always-on; 490 }; 491 492 /* vdd_3p3 */ 493 BUCK4 { 494 regulator-name = "buck4"; 495 regulator-min-microvolt = <3000000>; 496 regulator-max-microvolt = <3300000>; 497 regulator-boot-on; 498 regulator-always-on; 499 }; 500 501 /* vdd_1p8 */ 502 BUCK5 { 503 regulator-name = "buck5"; 504 regulator-min-microvolt = <1605000>; 505 regulator-max-microvolt = <1995000>; 506 regulator-boot-on; 507 regulator-always-on; 508 }; 509 510 /* vdd_dram */ 511 BUCK6 { 512 regulator-name = "buck6"; 513 regulator-min-microvolt = <800000>; 514 regulator-max-microvolt = <1400000>; 515 regulator-boot-on; 516 regulator-always-on; 517 }; 518 519 /* nvcc_snvs_1p8 */ 520 LDO1 { 521 regulator-name = "ldo1"; 522 regulator-min-microvolt = <1600000>; 523 regulator-max-microvolt = <1900000>; 524 regulator-boot-on; 525 regulator-always-on; 526 }; 527 528 /* vdd_snvs_0p8 */ 529 LDO2 { 530 regulator-name = "ldo2"; 531 regulator-min-microvolt = <800000>; 532 regulator-max-microvolt = <900000>; 533 regulator-boot-on; 534 regulator-always-on; 535 }; 536 537 /* vdda_1p8 */ 538 LDO3 { 539 regulator-name = "ldo3"; 540 regulator-min-microvolt = <1800000>; 541 regulator-max-microvolt = <3300000>; 542 regulator-boot-on; 543 regulator-always-on; 544 }; 545 546 LDO4 { 547 regulator-name = "ldo4"; 548 regulator-min-microvolt = <900000>; 549 regulator-max-microvolt = <1800000>; 550 regulator-boot-on; 551 regulator-always-on; 552 }; 553 554 LDO6 { 555 regulator-name = "ldo6"; 556 regulator-min-microvolt = <900000>; 557 regulator-max-microvolt = <1800000>; 558 regulator-boot-on; 559 regulator-always-on; 560 }; 561 }; 562 }; 563}; 564 565&i2c3 { 566 clock-frequency = <400000>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_i2c3>; 569 status = "okay"; 570 571 accelerometer@19 { 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_accel>; 574 compatible = "st,lis2de12"; 575 reg = <0x19>; 576 st,drdy-int-pin = <1>; 577 interrupt-parent = <&gpio1>; 578 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 579 interrupt-names = "INT1"; 580 }; 581}; 582 583&i2c4 { 584 clock-frequency = <400000>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_i2c4>; 587 status = "okay"; 588 589 gpioled: gpio@27 { 590 compatible = "nxp,pca9555"; 591 reg = <0x27>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 }; 595}; 596 597&pcie_phy { 598 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 599 fsl,clkreq-unsupported; 600 clocks = <&pcie0_refclk>; 601 clock-names = "ref"; 602 status = "okay"; 603}; 604 605&pcie0 { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_pcie0>; 608 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; 609 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 610 <&pcie0_refclk>; 611 clock-names = "pcie", "pcie_aux", "pcie_bus"; 612 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 613 <&clk IMX8MM_CLK_PCIE1_CTRL>; 614 assigned-clock-rates = <10000000>, <250000000>; 615 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 616 <&clk IMX8MM_SYS_PLL2_250M>; 617 status = "okay"; 618}; 619 620&pgc_mipi { 621 status = "disabled"; 622}; 623 624/* off-board RS232 */ 625&uart1 { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_uart1>; 628 status = "okay"; 629}; 630 631/* console */ 632&uart2 { 633 pinctrl-names = "default"; 634 pinctrl-0 = <&pinctrl_uart2>; 635 status = "okay"; 636}; 637 638/* off-board RS232 */ 639&uart3 { 640 pinctrl-names = "default"; 641 pinctrl-0 = <&pinctrl_uart3>; 642 status = "okay"; 643}; 644 645&usbotg1 { 646 dr_mode = "host"; 647 disable-over-current; 648 status = "okay"; 649}; 650 651/* microSD */ 652&usdhc2 { 653 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 654 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 655 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 656 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 657 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 658 bus-width = <4>; 659 vmmc-supply = <®_3p3v>; 660 status = "okay"; 661}; 662 663/* eMMC */ 664&usdhc3 { 665 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 666 pinctrl-0 = <&pinctrl_usdhc3>; 667 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 668 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 669 bus-width = <8>; 670 non-removable; 671 status = "okay"; 672}; 673 674&wdog1 { 675 pinctrl-names = "default"; 676 pinctrl-0 = <&pinctrl_wdog>; 677 fsl,ext-reset-output; 678 status = "okay"; 679}; 680 681&iomuxc { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_hog>; 684 685 pinctrl_hog: hoggrp { 686 fsl,pins = < 687 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ 688 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ 689 >; 690 }; 691 692 pinctrl_accel: accelgrp { 693 fsl,pins = < 694 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 695 >; 696 }; 697 698 pinctrl_fec1: fec1grp { 699 fsl,pins = < 700 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 701 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 702 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 703 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 704 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 705 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 706 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 707 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 708 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 709 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 710 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 711 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 712 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 713 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 714 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ 715 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ 716 >; 717 }; 718 719 pinctrl_gpio_leds: gpioledsgrp { 720 fsl,pins = < 721 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019 722 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019 723 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019 724 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019 725 >; 726 }; 727 728 pinctrl_gsc: gscgrp { 729 fsl,pins = < 730 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 731 >; 732 }; 733 734 pinctrl_i2c1: i2c1grp { 735 fsl,pins = < 736 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 737 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 738 >; 739 }; 740 741 pinctrl_i2c2: i2c2grp { 742 fsl,pins = < 743 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 744 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 745 >; 746 }; 747 748 pinctrl_i2c3: i2c3grp { 749 fsl,pins = < 750 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 751 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 752 >; 753 }; 754 755 pinctrl_i2c4: i2c4grp { 756 fsl,pins = < 757 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 758 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 759 >; 760 }; 761 762 pinctrl_pcie0: pciegrp { 763 fsl,pins = < 764 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 765 >; 766 }; 767 768 pinctrl_pmic: pmicgrp { 769 fsl,pins = < 770 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 771 >; 772 }; 773 774 pinctrl_uart1: uart1grp { 775 fsl,pins = < 776 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 777 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 778 >; 779 }; 780 781 pinctrl_uart2: uart2grp { 782 fsl,pins = < 783 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 784 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 785 >; 786 }; 787 788 pinctrl_uart3: uart3grp { 789 fsl,pins = < 790 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 791 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 792 >; 793 }; 794 795 pinctrl_usdhc2: usdhc2grp { 796 fsl,pins = < 797 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 798 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 799 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 800 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 801 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 802 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 803 >; 804 }; 805 806 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 807 fsl,pins = < 808 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 809 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 810 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 811 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 812 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 813 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 814 >; 815 }; 816 817 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 818 fsl,pins = < 819 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 820 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 821 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 822 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 823 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 824 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 825 >; 826 }; 827 828 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 829 fsl,pins = < 830 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 831 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 832 >; 833 }; 834 835 pinctrl_usdhc3: usdhc3grp { 836 fsl,pins = < 837 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 838 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 839 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 840 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 841 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 842 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 843 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 844 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 845 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 846 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 847 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 848 >; 849 }; 850 851 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 852 fsl,pins = < 853 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 854 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 855 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 856 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 857 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 858 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 859 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 860 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 861 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 862 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 863 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 864 >; 865 }; 866 867 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 868 fsl,pins = < 869 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 870 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 871 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 872 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 873 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 874 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 875 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 876 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 877 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 878 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 879 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 880 >; 881 }; 882 883 pinctrl_wdog: wdoggrp { 884 fsl,pins = < 885 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 886 >; 887 }; 888}; 889