1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93};
94
95&eqos {
96	pinctrl-names = "default";
97	pinctrl-0 = <&pinctrl_eqos>;
98	phy-mode = "rgmii-id";
99	phy-handle = <&ethphy0>;
100	nvmem-cells = <&fec_mac1>;
101	nvmem-cell-names = "mac-address";
102	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
103	snps,reset-delays-us = <10 20 200000>;
104	status = "okay";
105
106	mdio {
107		compatible = "snps,dwmac-mdio";
108		#address-cells = <1>;
109		#size-cells = <0>;
110
111		ethphy0: ethernet-phy@0 {
112			compatible = "ethernet-phy-ieee802.3-c22";
113			reg = <0>;
114			eee-broken-1000t;
115			qca,disable-smarteee;
116			vddio-supply = <&vddio0>;
117
118			vddio0: vddio-regulator {
119				regulator-min-microvolt = <1800000>;
120				regulator-max-microvolt = <1800000>;
121			};
122		};
123	};
124};
125
126/*
127 * fec1 shares the some PINs with usdhc2.
128 * by default usdhc2 is enabled in this dts.
129 * Please disable usdhc2 to enable fec1
130 */
131&fec1 {
132	pinctrl-names = "default";
133	pinctrl-0 = <&pinctrl_fec1>;
134	phy-mode = "rgmii-txid";
135	phy-handle = <&ethphy1>;
136	fsl,magic-packet;
137	rx-internal-delay-ps = <2000>;
138	nvmem-cells = <&fec_mac0>;
139	nvmem-cell-names = "mac-address";
140	status = "disabled";
141
142	mdio {
143		#address-cells = <1>;
144		#size-cells = <0>;
145
146		ethphy1: ethernet-phy@1 {
147			compatible = "ethernet-phy-ieee802.3-c22";
148			reg = <1>;
149			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
150			reset-assert-us = <10000>;
151			qca,disable-smarteee;
152			vddio-supply = <&vddio1>;
153
154			vddio1: vddio-regulator {
155				regulator-min-microvolt = <1800000>;
156				regulator-max-microvolt = <1800000>;
157			};
158		};
159	};
160};
161
162&i2c2 {
163	#address-cells = <1>;
164	#size-cells = <0>;
165	clock-frequency = <100000>;
166	pinctrl-names = "default";
167	pinctrl-0 = <&pinctrl_i2c2>;
168	status = "okay";
169
170	pca6416_1: gpio@20 {
171		compatible = "ti,tca6416";
172		reg = <0x20>;
173		gpio-controller;
174		#gpio-cells = <2>;
175	};
176
177	pca6416_2: gpio@21 {
178		compatible = "ti,tca6416";
179		reg = <0x21>;
180		gpio-controller;
181		#gpio-cells = <2>;
182	};
183
184	pca9548_1: i2c-mux@70 {
185		compatible = "nxp,pca9548";
186		#address-cells = <1>;
187		#size-cells = <0>;
188		reg = <0x70>;
189
190		i2c@0 {
191			#address-cells = <1>;
192			#size-cells = <0>;
193			reg = <0x0>;
194
195			max7322: gpio@68 {
196				compatible = "maxim,max7322";
197				reg = <0x68>;
198				gpio-controller;
199				#gpio-cells = <2>;
200				status = "disabled";
201			};
202		};
203
204		i2c@4 {
205			#address-cells = <1>;
206			#size-cells = <0>;
207			reg = <0x4>;
208		};
209
210		i2c@5 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			reg = <0x5>;
214		};
215
216		i2c@6 {
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0x6>;
220		};
221	};
222};
223
224&lpuart0 {
225	pinctrl-names = "default";
226	pinctrl-0 = <&pinctrl_lpuart0>;
227	status = "okay";
228};
229
230&lsio_gpio4 {
231	status = "okay";
232};
233
234&lsio_gpio5 {
235	status = "okay";
236};
237
238&thermal_zones {
239	pmic-thermal0 {
240		polling-delay-passive = <250>;
241		polling-delay = <2000>;
242		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
243
244		trips {
245			pmic_alert0: trip0 {
246				temperature = <110000>;
247				hysteresis = <2000>;
248				type = "passive";
249			};
250
251			pmic_crit0: trip1 {
252				temperature = <125000>;
253				hysteresis = <2000>;
254				type = "critical";
255			};
256		};
257
258		cooling-maps {
259			map0 {
260				trip = <&pmic_alert0>;
261				cooling-device =
262					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
263					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
264			};
265		};
266	};
267};
268
269&usdhc1 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_usdhc1>;
272	bus-width = <8>;
273	no-sd;
274	no-sdio;
275	non-removable;
276	status = "okay";
277};
278
279&usdhc2 {
280	pinctrl-names = "default";
281	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
282	bus-width = <4>;
283	vmmc-supply = <&reg_usdhc2_vmmc>;
284	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
285	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
286	status = "okay";
287};
288
289&iomuxc {
290	pinctrl-names = "default";
291	pinctrl-0 = <&pinctrl_hog>;
292
293	pinctrl_hog: hoggrp {
294		fsl,pins = <
295			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
296			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
297			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
298			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
299		>;
300	};
301
302	pinctrl_usbotg1: usbotg1grp {
303		fsl,pins = <
304			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
305		>;
306	};
307
308	pinctrl_usbotg2: usbotg2grp {
309		fsl,pins = <
310			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
311		>;
312	};
313
314	pinctrl_eqos: eqosgrp {
315		fsl,pins = <
316			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
317			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
318			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
319			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
320			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
321			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
322			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
323			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
324			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
325			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
326			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
327			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
328			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
329			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
330		>;
331	};
332
333	pinctrl_fec1: fec1grp {
334		fsl,pins = <
335			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
336			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
337			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
338			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
339			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
340			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
341			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
342			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
343			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
344			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
345			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
346			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
347			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
348			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
349			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
350			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
351		>;
352	};
353
354	pinctrl_lpspi3: lpspi3grp {
355		fsl,pins = <
356			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
357			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
358			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
359			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
360		>;
361	};
362
363	pinctrl_i2c2: i2c2grp {
364		fsl,pins = <
365			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
366			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
367		>;
368	};
369
370	pinctrl_cm40_lpuart: cm40lpuartgrp {
371		fsl,pins = <
372			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
373			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
374		>;
375	};
376
377	pinctrl_i2c3: i2c3grp {
378		fsl,pins = <
379			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
380			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
381		>;
382	};
383
384	pinctrl_lpuart0: lpuart0grp {
385		fsl,pins = <
386			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
387			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
388		>;
389	};
390
391	pinctrl_usdhc1: usdhc1grp {
392		fsl,pins = <
393			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
394			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
395			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
396			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
397			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
398			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
399			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
400			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
401			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
402			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
403			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
404		>;
405	};
406
407	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
408		fsl,pins = <
409			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
410			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
411			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
412		>;
413	};
414
415	pinctrl_usdhc2: usdhc2grp {
416		fsl,pins = <
417			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
418			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
419			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
420			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
421			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
422			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
423			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
424		>;
425	};
426};
427