1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /************************************************************************ 3 * Include file for TRIZEPS4 SoM and ConXS eval-board 4 * Copyright (c) Jürgen Schindele 5 * 2006 6 ************************************************************************/ 7 8 /* 9 * Includes/Defines 10 */ 11 #ifndef _TRIPEPS4_H_ 12 #define _TRIPEPS4_H_ 13 14 #include "addr-map.h" 15 #include "irqs.h" /* PXA_GPIO_TO_IRQ */ 16 17 /* physical memory regions */ 18 #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ 19 #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ 20 #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ 21 #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 22 #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 23 24 /* Logic on ConXS-board CSFR register*/ 25 #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) 26 /* Logic on ConXS-board BOCR register*/ 27 #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) 28 /* Logic on ConXS-board IRCR register*/ 29 #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) 30 /* Logic on ConXS-board UPSR register*/ 31 #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) 32 /* Logic on ConXS-board DICR register*/ 33 #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) 34 35 /* virtual memory regions */ 36 #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 37 38 #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ 39 #define TRIZEPS4_CFSR_VIRT 0xF0100000 40 #define TRIZEPS4_BOCR_VIRT 0xF0200000 41 #define TRIZEPS4_DICR_VIRT 0xF0300000 42 #define TRIZEPS4_IRCR_VIRT 0xF0400000 43 #define TRIZEPS4_UPSR_VIRT 0xF0500000 44 45 /* size of flash */ 46 #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ 47 48 /* Ethernet Controller Davicom DM9000 */ 49 #define GPIO_DM9000 101 50 #define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) 51 52 /* UCB1400 audio / TS-controller */ 53 #define GPIO_UCB1400 1 54 #define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) 55 56 /* PCMCIA socket Compact Flash */ 57 #define GPIO_PCD 11 /* PCMCIA Card Detect */ 58 #define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) 59 #define GPIO_PRDY 13 /* READY / nINT */ 60 #define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) 61 62 /* MMC socket */ 63 #define GPIO_MMC_DET 12 64 #define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) 65 66 /* DOC NAND chip */ 67 #define GPIO_DOC_LOCK 94 68 #define GPIO_DOC_IRQ 93 69 #define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) 70 71 /* SPI interface */ 72 #define GPIO_SPI 53 73 #define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) 74 75 /* LEDS using tx2 / rx2 */ 76 #define GPIO_SYS_BUSY_LED 46 77 #define GPIO_HEARTBEAT_LED 47 78 79 /* Off-module PIC on ConXS board */ 80 #define GPIO_PIC 0 81 #define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) 82 83 #ifdef CONFIG_MACH_TRIZEPS_CONXS 84 /* for CONXS base board define these registers */ 85 #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 86 #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 87 88 #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 89 #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 90 91 #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 92 #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 93 94 #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) 95 #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) 96 97 #ifndef __ASSEMBLY__ CFSR_readw(void)98static inline unsigned short CFSR_readw(void) 99 { 100 /* [Compact Flash Status Register] is read only */ 101 return *((unsigned short *)CFSR_P2V(0x0C000000)); 102 } BCR_writew(unsigned short value)103static inline void BCR_writew(unsigned short value) 104 { 105 /* [Board Control Regsiter] is write only */ 106 *((unsigned short *)BCR_P2V(0x0E000000)) = value; 107 } DCR_writew(unsigned short value)108static inline void DCR_writew(unsigned short value) 109 { 110 /* [Display Control Register] is write only */ 111 *((unsigned short *)DCR_P2V(0x0E000000)) = value; 112 } IRCR_writew(unsigned short value)113static inline void IRCR_writew(unsigned short value) 114 { 115 /* [InfraRed data Control Register] is write only */ 116 *((unsigned short *)IRCR_P2V(0x0E000000)) = value; 117 } 118 #else 119 #define ConXS_CFSR CFSR_P2V(0x0C000000) 120 #define ConXS_BCR BCR_P2V(0x0E000000) 121 #define ConXS_DCR DCR_P2V(0x0F800000) 122 #define ConXS_IRCR IRCR_P2V(0x0F800000) 123 #endif 124 #else 125 /* for whatever baseboard define function registers */ CFSR_readw(void)126static inline unsigned short CFSR_readw(void) 127 { 128 return 0; 129 } BCR_writew(unsigned short value)130static inline void BCR_writew(unsigned short value) 131 { 132 ; 133 } DCR_writew(unsigned short value)134static inline void DCR_writew(unsigned short value) 135 { 136 ; 137 } IRCR_writew(unsigned short value)138static inline void IRCR_writew(unsigned short value) 139 { 140 ; 141 } 142 #endif /* CONFIG_MACH_TRIZEPS_CONXS */ 143 144 #define ConXS_CFSR_BVD_MASK 0x0003 145 #define ConXS_CFSR_BVD1 (1 << 0) 146 #define ConXS_CFSR_BVD2 (1 << 1) 147 #define ConXS_CFSR_VS_MASK 0x000C 148 #define ConXS_CFSR_VS1 (1 << 2) 149 #define ConXS_CFSR_VS2 (1 << 3) 150 #define ConXS_CFSR_VS_5V (0x3 << 2) 151 #define ConXS_CFSR_VS_3V3 0x0 152 153 #define ConXS_BCR_S0_POW_EN0 (1 << 0) 154 #define ConXS_BCR_S0_POW_EN1 (1 << 1) 155 #define ConXS_BCR_L_DISP (1 << 4) 156 #define ConXS_BCR_CF_BUF_EN (1 << 5) 157 #define ConXS_BCR_CF_RESET (1 << 7) 158 #define ConXS_BCR_S0_VCC_3V3 0x1 159 #define ConXS_BCR_S0_VCC_5V0 0x2 160 #define ConXS_BCR_S0_VPP_12V 0x4 161 #define ConXS_BCR_S0_VPP_3V3 0x8 162 163 #define ConXS_IRCR_MODE (1 << 0) 164 #define ConXS_IRCR_SD (1 << 1) 165 166 #endif /* _TRIPEPS4_H_ */ 167