1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * arch/arm/mach-orion5x/db88f5281-setup.c
4 *
5 * Marvell Orion-2 Development Board Setup
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 */
9 #include <linux/gpio.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/pci.h>
14 #include <linux/irq.h>
15 #include <linux/mtd/physmap.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/timer.h>
18 #include <linux/mv643xx_eth.h>
19 #include <linux/i2c.h>
20 #include <asm/mach-types.h>
21 #include <asm/mach/arch.h>
22 #include <asm/mach/pci.h>
23 #include <linux/platform_data/mtd-orion_nand.h>
24 #include "common.h"
25 #include "mpp.h"
26 #include "orion5x.h"
27
28 /*****************************************************************************
29 * DB-88F5281 on board devices
30 ****************************************************************************/
31
32 /*
33 * 512K NOR flash Device bus boot chip select
34 */
35
36 #define DB88F5281_NOR_BOOT_BASE 0xf4000000
37 #define DB88F5281_NOR_BOOT_SIZE SZ_512K
38
39 /*
40 * 7-Segment on Device bus chip select 0
41 */
42
43 #define DB88F5281_7SEG_BASE 0xfa000000
44 #define DB88F5281_7SEG_SIZE SZ_1K
45
46 /*
47 * 32M NOR flash on Device bus chip select 1
48 */
49
50 #define DB88F5281_NOR_BASE 0xfc000000
51 #define DB88F5281_NOR_SIZE SZ_32M
52
53 /*
54 * 32M NAND flash on Device bus chip select 2
55 */
56
57 #define DB88F5281_NAND_BASE 0xfa800000
58 #define DB88F5281_NAND_SIZE SZ_1K
59
60 /*
61 * PCI
62 */
63
64 #define DB88F5281_PCI_SLOT0_OFFS 7
65 #define DB88F5281_PCI_SLOT0_IRQ_PIN 12
66 #define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
67
68 /*****************************************************************************
69 * 512M NOR Flash on Device bus Boot CS
70 ****************************************************************************/
71
72 static struct physmap_flash_data db88f5281_boot_flash_data = {
73 .width = 1, /* 8 bit bus width */
74 };
75
76 static struct resource db88f5281_boot_flash_resource = {
77 .flags = IORESOURCE_MEM,
78 .start = DB88F5281_NOR_BOOT_BASE,
79 .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
80 };
81
82 static struct platform_device db88f5281_boot_flash = {
83 .name = "physmap-flash",
84 .id = 0,
85 .dev = {
86 .platform_data = &db88f5281_boot_flash_data,
87 },
88 .num_resources = 1,
89 .resource = &db88f5281_boot_flash_resource,
90 };
91
92 /*****************************************************************************
93 * 32M NOR Flash on Device bus CS1
94 ****************************************************************************/
95
96 static struct physmap_flash_data db88f5281_nor_flash_data = {
97 .width = 4, /* 32 bit bus width */
98 };
99
100 static struct resource db88f5281_nor_flash_resource = {
101 .flags = IORESOURCE_MEM,
102 .start = DB88F5281_NOR_BASE,
103 .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
104 };
105
106 static struct platform_device db88f5281_nor_flash = {
107 .name = "physmap-flash",
108 .id = 1,
109 .dev = {
110 .platform_data = &db88f5281_nor_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &db88f5281_nor_flash_resource,
114 };
115
116 /*****************************************************************************
117 * 32M NAND Flash on Device bus CS2
118 ****************************************************************************/
119
120 static struct mtd_partition db88f5281_nand_parts[] = {
121 {
122 .name = "kernel",
123 .offset = 0,
124 .size = SZ_2M,
125 }, {
126 .name = "root",
127 .offset = SZ_2M,
128 .size = (SZ_16M - SZ_2M),
129 }, {
130 .name = "user",
131 .offset = SZ_16M,
132 .size = SZ_8M,
133 }, {
134 .name = "recovery",
135 .offset = (SZ_16M + SZ_8M),
136 .size = SZ_8M,
137 },
138 };
139
140 static struct resource db88f5281_nand_resource = {
141 .flags = IORESOURCE_MEM,
142 .start = DB88F5281_NAND_BASE,
143 .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
144 };
145
146 static struct orion_nand_data db88f5281_nand_data = {
147 .parts = db88f5281_nand_parts,
148 .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
149 .cle = 0,
150 .ale = 1,
151 .width = 8,
152 };
153
154 static struct platform_device db88f5281_nand_flash = {
155 .name = "orion_nand",
156 .id = -1,
157 .dev = {
158 .platform_data = &db88f5281_nand_data,
159 },
160 .resource = &db88f5281_nand_resource,
161 .num_resources = 1,
162 };
163
164 /*****************************************************************************
165 * 7-Segment on Device bus CS0
166 * Dummy counter every 2 sec
167 ****************************************************************************/
168
169 static void __iomem *db88f5281_7seg;
170 static struct timer_list db88f5281_timer;
171
db88f5281_7seg_event(struct timer_list * unused)172 static void db88f5281_7seg_event(struct timer_list *unused)
173 {
174 static int count = 0;
175 writel(0, db88f5281_7seg + (count << 4));
176 count = (count + 1) & 7;
177 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
178 }
179
db88f5281_7seg_init(void)180 static int __init db88f5281_7seg_init(void)
181 {
182 if (machine_is_db88f5281()) {
183 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
184 DB88F5281_7SEG_SIZE);
185 if (!db88f5281_7seg) {
186 printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
187 return -EIO;
188 }
189 timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0);
190 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
191 }
192
193 return 0;
194 }
195
196 __initcall(db88f5281_7seg_init);
197
198 /*****************************************************************************
199 * PCI
200 ****************************************************************************/
201
db88f5281_pci_preinit(void)202 static void __init db88f5281_pci_preinit(void)
203 {
204 int pin;
205
206 /*
207 * Configure PCI GPIO IRQ pins
208 */
209 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
210 if (gpio_request(pin, "PCI Int1") == 0) {
211 if (gpio_direction_input(pin) == 0) {
212 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
213 } else {
214 printk(KERN_ERR "db88f5281_pci_preinit failed to "
215 "set_irq_type pin %d\n", pin);
216 gpio_free(pin);
217 }
218 } else {
219 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
220 }
221
222 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
223 if (gpio_request(pin, "PCI Int2") == 0) {
224 if (gpio_direction_input(pin) == 0) {
225 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
226 } else {
227 printk(KERN_ERR "db88f5281_pci_preinit failed "
228 "to set_irq_type pin %d\n", pin);
229 gpio_free(pin);
230 }
231 } else {
232 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
233 }
234 }
235
db88f5281_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)236 static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
237 u8 pin)
238 {
239 int irq;
240
241 /*
242 * Check for devices with hard-wired IRQs.
243 */
244 irq = orion5x_pci_map_irq(dev, slot, pin);
245 if (irq != -1)
246 return irq;
247
248 /*
249 * PCI IRQs are connected via GPIOs.
250 */
251 switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
252 case 0:
253 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
254 case 1:
255 case 2:
256 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
257 default:
258 return -1;
259 }
260 }
261
262 static struct hw_pci db88f5281_pci __initdata = {
263 .nr_controllers = 2,
264 .preinit = db88f5281_pci_preinit,
265 .setup = orion5x_pci_sys_setup,
266 .scan = orion5x_pci_sys_scan_bus,
267 .map_irq = db88f5281_pci_map_irq,
268 };
269
db88f5281_pci_init(void)270 static int __init db88f5281_pci_init(void)
271 {
272 if (machine_is_db88f5281())
273 pci_common_init(&db88f5281_pci);
274
275 return 0;
276 }
277
278 subsys_initcall(db88f5281_pci_init);
279
280 /*****************************************************************************
281 * Ethernet
282 ****************************************************************************/
283 static struct mv643xx_eth_platform_data db88f5281_eth_data = {
284 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
285 };
286
287 /*****************************************************************************
288 * RTC DS1339 on I2C bus
289 ****************************************************************************/
290 static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
291 I2C_BOARD_INFO("ds1339", 0x68),
292 };
293
294 /*****************************************************************************
295 * General Setup
296 ****************************************************************************/
297 static unsigned int db88f5281_mpp_modes[] __initdata = {
298 MPP0_GPIO, /* USB Over Current */
299 MPP1_GPIO, /* USB Vbat input */
300 MPP2_PCI_ARB, /* PCI_REQn[2] */
301 MPP3_PCI_ARB, /* PCI_GNTn[2] */
302 MPP4_PCI_ARB, /* PCI_REQn[3] */
303 MPP5_PCI_ARB, /* PCI_GNTn[3] */
304 MPP6_GPIO, /* JP0, CON17.2 */
305 MPP7_GPIO, /* JP1, CON17.1 */
306 MPP8_GPIO, /* JP2, CON11.2 */
307 MPP9_GPIO, /* JP3, CON11.3 */
308 MPP10_GPIO, /* RTC int */
309 MPP11_GPIO, /* Baud Rate Generator */
310 MPP12_GPIO, /* PCI int 1 */
311 MPP13_GPIO, /* PCI int 2 */
312 MPP14_NAND, /* NAND_REn[2] */
313 MPP15_NAND, /* NAND_WEn[2] */
314 MPP16_UART, /* UART1_RX */
315 MPP17_UART, /* UART1_TX */
316 MPP18_UART, /* UART1_CTSn */
317 MPP19_UART, /* UART1_RTSn */
318 0,
319 };
320
db88f5281_init(void)321 static void __init db88f5281_init(void)
322 {
323 /*
324 * Basic Orion setup. Need to be called early.
325 */
326 orion5x_init();
327
328 orion5x_mpp_conf(db88f5281_mpp_modes);
329 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
330
331 /*
332 * Configure peripherals.
333 */
334 orion5x_ehci0_init();
335 orion5x_eth_init(&db88f5281_eth_data);
336 orion5x_i2c_init();
337 orion5x_uart0_init();
338 orion5x_uart1_init();
339
340 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
341 ORION_MBUS_DEVBUS_BOOT_ATTR,
342 DB88F5281_NOR_BOOT_BASE,
343 DB88F5281_NOR_BOOT_SIZE);
344 platform_device_register(&db88f5281_boot_flash);
345
346 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
347 ORION_MBUS_DEVBUS_ATTR(0),
348 DB88F5281_7SEG_BASE,
349 DB88F5281_7SEG_SIZE);
350
351 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
352 ORION_MBUS_DEVBUS_ATTR(1),
353 DB88F5281_NOR_BASE,
354 DB88F5281_NOR_SIZE);
355 platform_device_register(&db88f5281_nor_flash);
356
357 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
358 ORION_MBUS_DEVBUS_ATTR(2),
359 DB88F5281_NAND_BASE,
360 DB88F5281_NAND_SIZE);
361 platform_device_register(&db88f5281_nand_flash);
362
363 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
364 }
365
366 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
367 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
368 .atag_offset = 0x100,
369 .nr_irqs = ORION5X_NR_IRQS,
370 .init_machine = db88f5281_init,
371 .map_io = orion5x_map_io,
372 .init_early = orion5x_init_early,
373 .init_irq = orion5x_init_irq,
374 .init_time = orion5x_timer_init,
375 .restart = orion5x_restart,
376 MACHINE_END
377