1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun6i-rtc.h> 44#include <dt-bindings/clock/sun8i-de2.h> 45#include <dt-bindings/clock/sun8i-h3-ccu.h> 46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/reset/sun8i-de2.h> 49#include <dt-bindings/reset/sun8i-h3-ccu.h> 50#include <dt-bindings/reset/sun8i-r-ccu.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 chosen { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges; 61 62 framebuffer-hdmi { 63 compatible = "allwinner,simple-framebuffer", 64 "simple-framebuffer"; 65 allwinner,pipeline = "mixer0-lcd0-hdmi"; 66 clocks = <&display_clocks CLK_MIXER0>, 67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; 68 status = "disabled"; 69 }; 70 71 framebuffer-tve { 72 compatible = "allwinner,simple-framebuffer", 73 "simple-framebuffer"; 74 allwinner,pipeline = "mixer1-lcd1-tve"; 75 clocks = <&display_clocks CLK_MIXER1>, 76 <&ccu CLK_TVE>; 77 status = "disabled"; 78 }; 79 }; 80 81 clocks { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 osc24M: osc24M_clk { 87 #clock-cells = <0>; 88 compatible = "fixed-clock"; 89 clock-frequency = <24000000>; 90 clock-accuracy = <50000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-accuracy = <50000>; 99 clock-output-names = "ext_osc32k"; 100 }; 101 }; 102 103 de: display-engine { 104 compatible = "allwinner,sun8i-h3-display-engine"; 105 allwinner,pipelines = <&mixer0>; 106 status = "disabled"; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 dma-ranges; 114 ranges; 115 116 display_clocks: clock@1000000 { 117 /* compatible is in per SoC .dtsi file */ 118 reg = <0x01000000 0x10000>; 119 clocks = <&ccu CLK_BUS_DE>, 120 <&ccu CLK_DE>; 121 clock-names = "bus", 122 "mod"; 123 resets = <&ccu RST_BUS_DE>; 124 #clock-cells = <1>; 125 #reset-cells = <1>; 126 }; 127 128 mixer0: mixer@1100000 { 129 compatible = "allwinner,sun8i-h3-de2-mixer-0"; 130 reg = <0x01100000 0x100000>; 131 clocks = <&display_clocks CLK_BUS_MIXER0>, 132 <&display_clocks CLK_MIXER0>; 133 clock-names = "bus", 134 "mod"; 135 resets = <&display_clocks RST_MIXER0>; 136 137 ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 mixer0_out: port@1 { 142 reg = <1>; 143 144 mixer0_out_tcon0: endpoint { 145 remote-endpoint = <&tcon0_in_mixer0>; 146 }; 147 }; 148 }; 149 }; 150 151 dma: dma-controller@1c02000 { 152 compatible = "allwinner,sun8i-h3-dma"; 153 reg = <0x01c02000 0x1000>; 154 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&ccu CLK_BUS_DMA>; 156 resets = <&ccu RST_BUS_DMA>; 157 #dma-cells = <1>; 158 }; 159 160 tcon0: lcd-controller@1c0c000 { 161 compatible = "allwinner,sun8i-h3-tcon-tv", 162 "allwinner,sun8i-a83t-tcon-tv"; 163 reg = <0x01c0c000 0x1000>; 164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 166 clock-names = "ahb", "tcon-ch1"; 167 resets = <&ccu RST_BUS_TCON0>; 168 reset-names = "lcd"; 169 170 ports { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 tcon0_in: port@0 { 175 reg = <0>; 176 177 tcon0_in_mixer0: endpoint { 178 remote-endpoint = <&mixer0_out_tcon0>; 179 }; 180 }; 181 182 tcon0_out: port@1 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <1>; 186 187 tcon0_out_hdmi: endpoint@1 { 188 reg = <1>; 189 remote-endpoint = <&hdmi_in_tcon0>; 190 }; 191 }; 192 }; 193 }; 194 195 mmc0: mmc@1c0f000 { 196 /* compatible and clocks are in per SoC .dtsi file */ 197 reg = <0x01c0f000 0x1000>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&mmc0_pins>; 200 resets = <&ccu RST_BUS_MMC0>; 201 reset-names = "ahb"; 202 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 203 status = "disabled"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 }; 207 208 mmc1: mmc@1c10000 { 209 /* compatible and clocks are in per SoC .dtsi file */ 210 reg = <0x01c10000 0x1000>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&mmc1_pins>; 213 resets = <&ccu RST_BUS_MMC1>; 214 reset-names = "ahb"; 215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 216 status = "disabled"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 mmc2: mmc@1c11000 { 222 /* compatible and clocks are in per SoC .dtsi file */ 223 reg = <0x01c11000 0x1000>; 224 resets = <&ccu RST_BUS_MMC2>; 225 reset-names = "ahb"; 226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 227 status = "disabled"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 sid: eeprom@1c14000 { 233 /* compatible is in per SoC .dtsi file */ 234 reg = <0x1c14000 0x400>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 238 ths_calibration: thermal-sensor-calibration@34 { 239 reg = <0x34 4>; 240 }; 241 }; 242 243 msgbox: mailbox@1c17000 { 244 compatible = "allwinner,sun8i-h3-msgbox", 245 "allwinner,sun6i-a31-msgbox"; 246 reg = <0x01c17000 0x1000>; 247 clocks = <&ccu CLK_BUS_MSGBOX>; 248 resets = <&ccu RST_BUS_MSGBOX>; 249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 250 #mbox-cells = <1>; 251 }; 252 253 usb_otg: usb@1c19000 { 254 compatible = "allwinner,sun8i-h3-musb"; 255 reg = <0x01c19000 0x400>; 256 clocks = <&ccu CLK_BUS_OTG>; 257 resets = <&ccu RST_BUS_OTG>; 258 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-names = "mc"; 260 phys = <&usbphy 0>; 261 phy-names = "usb"; 262 extcon = <&usbphy 0>; 263 dr_mode = "otg"; 264 status = "disabled"; 265 }; 266 267 usbphy: phy@1c19400 { 268 compatible = "allwinner,sun8i-h3-usb-phy"; 269 reg = <0x01c19400 0x2c>, 270 <0x01c1a800 0x4>, 271 <0x01c1b800 0x4>, 272 <0x01c1c800 0x4>, 273 <0x01c1d800 0x4>; 274 reg-names = "phy_ctrl", 275 "pmu0", 276 "pmu1", 277 "pmu2", 278 "pmu3"; 279 clocks = <&ccu CLK_USB_PHY0>, 280 <&ccu CLK_USB_PHY1>, 281 <&ccu CLK_USB_PHY2>, 282 <&ccu CLK_USB_PHY3>; 283 clock-names = "usb0_phy", 284 "usb1_phy", 285 "usb2_phy", 286 "usb3_phy"; 287 resets = <&ccu RST_USB_PHY0>, 288 <&ccu RST_USB_PHY1>, 289 <&ccu RST_USB_PHY2>, 290 <&ccu RST_USB_PHY3>; 291 reset-names = "usb0_reset", 292 "usb1_reset", 293 "usb2_reset", 294 "usb3_reset"; 295 status = "disabled"; 296 #phy-cells = <1>; 297 }; 298 299 ehci0: usb@1c1a000 { 300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 301 reg = <0x01c1a000 0x100>; 302 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 305 status = "disabled"; 306 }; 307 308 ohci0: usb@1c1a400 { 309 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 310 reg = <0x01c1a400 0x100>; 311 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 313 <&ccu CLK_USB_OHCI0>; 314 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 315 status = "disabled"; 316 }; 317 318 ehci1: usb@1c1b000 { 319 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 320 reg = <0x01c1b000 0x100>; 321 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 323 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 324 phys = <&usbphy 1>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 ohci1: usb@1c1b400 { 330 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 331 reg = <0x01c1b400 0x100>; 332 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 334 <&ccu CLK_USB_OHCI1>; 335 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 336 phys = <&usbphy 1>; 337 phy-names = "usb"; 338 status = "disabled"; 339 }; 340 341 ehci2: usb@1c1c000 { 342 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 343 reg = <0x01c1c000 0x100>; 344 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 346 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 347 phys = <&usbphy 2>; 348 phy-names = "usb"; 349 status = "disabled"; 350 }; 351 352 ohci2: usb@1c1c400 { 353 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 354 reg = <0x01c1c400 0x100>; 355 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 357 <&ccu CLK_USB_OHCI2>; 358 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 359 phys = <&usbphy 2>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 ehci3: usb@1c1d000 { 365 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 366 reg = <0x01c1d000 0x100>; 367 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 369 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 370 phys = <&usbphy 3>; 371 phy-names = "usb"; 372 status = "disabled"; 373 }; 374 375 ohci3: usb@1c1d400 { 376 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 377 reg = <0x01c1d400 0x100>; 378 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 380 <&ccu CLK_USB_OHCI3>; 381 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 382 phys = <&usbphy 3>; 383 phy-names = "usb"; 384 status = "disabled"; 385 }; 386 387 ccu: clock@1c20000 { 388 /* compatible is in per SoC .dtsi file */ 389 reg = <0x01c20000 0x400>; 390 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 391 clock-names = "hosc", "losc"; 392 #clock-cells = <1>; 393 #reset-cells = <1>; 394 }; 395 396 pio: pinctrl@1c20800 { 397 /* compatible is in per SoC .dtsi file */ 398 reg = <0x01c20800 0x400>; 399 interrupt-parent = <&r_intc>; 400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 403 <&rtc CLK_OSC32K>; 404 clock-names = "apb", "hosc", "losc"; 405 gpio-controller; 406 #gpio-cells = <3>; 407 interrupt-controller; 408 #interrupt-cells = <3>; 409 410 csi_pins: csi-pins { 411 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 412 "PE6", "PE7", "PE8", "PE9", "PE10", 413 "PE11"; 414 function = "csi"; 415 }; 416 417 emac_rgmii_pins: emac-rgmii-pins { 418 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 419 "PD5", "PD7", "PD8", "PD9", "PD10", 420 "PD12", "PD13", "PD15", "PD16", "PD17"; 421 function = "emac"; 422 drive-strength = <40>; 423 }; 424 425 i2c0_pins: i2c0-pins { 426 pins = "PA11", "PA12"; 427 function = "i2c0"; 428 }; 429 430 i2c1_pins: i2c1-pins { 431 pins = "PA18", "PA19"; 432 function = "i2c1"; 433 }; 434 435 i2c2_pins: i2c2-pins { 436 pins = "PE12", "PE13"; 437 function = "i2c2"; 438 }; 439 440 mmc0_pins: mmc0-pins { 441 pins = "PF0", "PF1", "PF2", "PF3", 442 "PF4", "PF5"; 443 function = "mmc0"; 444 drive-strength = <30>; 445 bias-pull-up; 446 }; 447 448 mmc1_pins: mmc1-pins { 449 pins = "PG0", "PG1", "PG2", "PG3", 450 "PG4", "PG5"; 451 function = "mmc1"; 452 drive-strength = <30>; 453 bias-pull-up; 454 }; 455 456 mmc2_8bit_pins: mmc2-8bit-pins { 457 pins = "PC5", "PC6", "PC8", 458 "PC9", "PC10", "PC11", 459 "PC12", "PC13", "PC14", 460 "PC15", "PC16"; 461 function = "mmc2"; 462 drive-strength = <30>; 463 bias-pull-up; 464 }; 465 466 spdif_tx_pin: spdif-tx-pin { 467 pins = "PA17"; 468 function = "spdif"; 469 }; 470 471 spi0_pins: spi0-pins { 472 pins = "PC0", "PC1", "PC2", "PC3"; 473 function = "spi0"; 474 }; 475 476 spi1_pins: spi1-pins { 477 pins = "PA15", "PA16", "PA14", "PA13"; 478 function = "spi1"; 479 }; 480 481 uart0_pa_pins: uart0-pa-pins { 482 pins = "PA4", "PA5"; 483 function = "uart0"; 484 }; 485 486 uart1_pins: uart1-pins { 487 pins = "PG6", "PG7"; 488 function = "uart1"; 489 }; 490 491 uart1_rts_cts_pins: uart1-rts-cts-pins { 492 pins = "PG8", "PG9"; 493 function = "uart1"; 494 }; 495 496 uart2_pins: uart2-pins { 497 pins = "PA0", "PA1"; 498 function = "uart2"; 499 }; 500 501 uart2_rts_cts_pins: uart2-rts-cts-pins { 502 pins = "PA2", "PA3"; 503 function = "uart2"; 504 }; 505 506 uart3_pins: uart3-pins { 507 pins = "PA13", "PA14"; 508 function = "uart3"; 509 }; 510 511 uart3_rts_cts_pins: uart3-rts-cts-pins { 512 pins = "PA15", "PA16"; 513 function = "uart3"; 514 }; 515 }; 516 517 timer@1c20c00 { 518 compatible = "allwinner,sun8i-a23-timer"; 519 reg = <0x01c20c00 0xa0>; 520 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&osc24M>; 523 }; 524 525 emac: ethernet@1c30000 { 526 compatible = "allwinner,sun8i-h3-emac"; 527 syscon = <&syscon>; 528 reg = <0x01c30000 0x10000>; 529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "macirq"; 531 resets = <&ccu RST_BUS_EMAC>; 532 reset-names = "stmmaceth"; 533 clocks = <&ccu CLK_BUS_EMAC>; 534 clock-names = "stmmaceth"; 535 status = "disabled"; 536 537 mdio: mdio { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 compatible = "snps,dwmac-mdio"; 541 }; 542 543 mdio-mux { 544 compatible = "allwinner,sun8i-h3-mdio-mux"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 548 mdio-parent-bus = <&mdio>; 549 /* Only one MDIO is usable at the time */ 550 internal_mdio: mdio@1 { 551 compatible = "allwinner,sun8i-h3-mdio-internal"; 552 reg = <1>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 556 int_mii_phy: ethernet-phy@1 { 557 compatible = "ethernet-phy-ieee802.3-c22"; 558 reg = <1>; 559 clocks = <&ccu CLK_BUS_EPHY>; 560 resets = <&ccu RST_BUS_EPHY>; 561 }; 562 }; 563 564 external_mdio: mdio@2 { 565 reg = <2>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 }; 569 }; 570 }; 571 572 mbus: dram-controller@1c62000 { 573 /* compatible is in per SoC .dtsi file */ 574 reg = <0x01c62000 0x1000>, 575 <0x01c63000 0x1000>; 576 reg-names = "mbus", "dram"; 577 clocks = <&ccu CLK_MBUS>, 578 <&ccu CLK_DRAM>, 579 <&ccu CLK_BUS_DRAM>; 580 clock-names = "mbus", "dram", "bus"; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 584 #interconnect-cells = <1>; 585 }; 586 587 spi0: spi@1c68000 { 588 compatible = "allwinner,sun8i-h3-spi"; 589 reg = <0x01c68000 0x1000>; 590 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 592 clock-names = "ahb", "mod"; 593 dmas = <&dma 23>, <&dma 23>; 594 dma-names = "rx", "tx"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&spi0_pins>; 597 resets = <&ccu RST_BUS_SPI0>; 598 status = "disabled"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 }; 602 603 spi1: spi@1c69000 { 604 compatible = "allwinner,sun8i-h3-spi"; 605 reg = <0x01c69000 0x1000>; 606 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 608 clock-names = "ahb", "mod"; 609 dmas = <&dma 24>, <&dma 24>; 610 dma-names = "rx", "tx"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&spi1_pins>; 613 resets = <&ccu RST_BUS_SPI1>; 614 status = "disabled"; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 }; 618 619 wdt0: watchdog@1c20ca0 { 620 compatible = "allwinner,sun6i-a31-wdt"; 621 reg = <0x01c20ca0 0x20>; 622 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&osc24M>; 624 }; 625 626 spdif: spdif@1c21000 { 627 #sound-dai-cells = <0>; 628 compatible = "allwinner,sun8i-h3-spdif"; 629 reg = <0x01c21000 0x400>; 630 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 632 resets = <&ccu RST_BUS_SPDIF>; 633 clock-names = "apb", "spdif"; 634 dmas = <&dma 2>; 635 dma-names = "tx"; 636 status = "disabled"; 637 }; 638 639 pwm: pwm@1c21400 { 640 compatible = "allwinner,sun8i-h3-pwm"; 641 reg = <0x01c21400 0x8>; 642 clocks = <&osc24M>; 643 #pwm-cells = <3>; 644 status = "disabled"; 645 }; 646 647 i2s0: i2s@1c22000 { 648 #sound-dai-cells = <0>; 649 compatible = "allwinner,sun8i-h3-i2s"; 650 reg = <0x01c22000 0x400>; 651 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 653 clock-names = "apb", "mod"; 654 dmas = <&dma 3>, <&dma 3>; 655 resets = <&ccu RST_BUS_I2S0>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 i2s1: i2s@1c22400 { 661 #sound-dai-cells = <0>; 662 compatible = "allwinner,sun8i-h3-i2s"; 663 reg = <0x01c22400 0x400>; 664 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 666 clock-names = "apb", "mod"; 667 dmas = <&dma 4>, <&dma 4>; 668 resets = <&ccu RST_BUS_I2S1>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 i2s2: i2s@1c22800 { 674 #sound-dai-cells = <0>; 675 compatible = "allwinner,sun8i-h3-i2s"; 676 reg = <0x01c22800 0x400>; 677 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 679 clock-names = "apb", "mod"; 680 dmas = <&dma 27>; 681 resets = <&ccu RST_BUS_I2S2>; 682 dma-names = "tx"; 683 status = "disabled"; 684 }; 685 686 codec: codec@1c22c00 { 687 #sound-dai-cells = <0>; 688 compatible = "allwinner,sun8i-h3-codec"; 689 reg = <0x01c22c00 0x400>; 690 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 692 clock-names = "apb", "codec"; 693 resets = <&ccu RST_BUS_CODEC>; 694 dmas = <&dma 15>, <&dma 15>; 695 dma-names = "rx", "tx"; 696 allwinner,codec-analog-controls = <&codec_analog>; 697 status = "disabled"; 698 }; 699 700 uart0: serial@1c28000 { 701 compatible = "snps,dw-apb-uart"; 702 reg = <0x01c28000 0x400>; 703 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 704 reg-shift = <2>; 705 reg-io-width = <4>; 706 clocks = <&ccu CLK_BUS_UART0>; 707 resets = <&ccu RST_BUS_UART0>; 708 dmas = <&dma 6>, <&dma 6>; 709 dma-names = "rx", "tx"; 710 status = "disabled"; 711 }; 712 713 uart1: serial@1c28400 { 714 compatible = "snps,dw-apb-uart"; 715 reg = <0x01c28400 0x400>; 716 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 717 reg-shift = <2>; 718 reg-io-width = <4>; 719 clocks = <&ccu CLK_BUS_UART1>; 720 resets = <&ccu RST_BUS_UART1>; 721 dmas = <&dma 7>, <&dma 7>; 722 dma-names = "rx", "tx"; 723 status = "disabled"; 724 }; 725 726 uart2: serial@1c28800 { 727 compatible = "snps,dw-apb-uart"; 728 reg = <0x01c28800 0x400>; 729 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 730 reg-shift = <2>; 731 reg-io-width = <4>; 732 clocks = <&ccu CLK_BUS_UART2>; 733 resets = <&ccu RST_BUS_UART2>; 734 dmas = <&dma 8>, <&dma 8>; 735 dma-names = "rx", "tx"; 736 status = "disabled"; 737 }; 738 739 uart3: serial@1c28c00 { 740 compatible = "snps,dw-apb-uart"; 741 reg = <0x01c28c00 0x400>; 742 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 743 reg-shift = <2>; 744 reg-io-width = <4>; 745 clocks = <&ccu CLK_BUS_UART3>; 746 resets = <&ccu RST_BUS_UART3>; 747 dmas = <&dma 9>, <&dma 9>; 748 dma-names = "rx", "tx"; 749 status = "disabled"; 750 }; 751 752 i2c0: i2c@1c2ac00 { 753 compatible = "allwinner,sun6i-a31-i2c"; 754 reg = <0x01c2ac00 0x400>; 755 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&ccu CLK_BUS_I2C0>; 757 resets = <&ccu RST_BUS_I2C0>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&i2c0_pins>; 760 status = "disabled"; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 }; 764 765 i2c1: i2c@1c2b000 { 766 compatible = "allwinner,sun6i-a31-i2c"; 767 reg = <0x01c2b000 0x400>; 768 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&ccu CLK_BUS_I2C1>; 770 resets = <&ccu RST_BUS_I2C1>; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&i2c1_pins>; 773 status = "disabled"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 }; 777 778 i2c2: i2c@1c2b400 { 779 compatible = "allwinner,sun6i-a31-i2c"; 780 reg = <0x01c2b400 0x400>; 781 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&ccu CLK_BUS_I2C2>; 783 resets = <&ccu RST_BUS_I2C2>; 784 pinctrl-names = "default"; 785 pinctrl-0 = <&i2c2_pins>; 786 status = "disabled"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 }; 790 791 gic: interrupt-controller@1c81000 { 792 compatible = "arm,gic-400"; 793 reg = <0x01c81000 0x1000>, 794 <0x01c82000 0x2000>, 795 <0x01c84000 0x2000>, 796 <0x01c86000 0x2000>; 797 interrupt-controller; 798 #interrupt-cells = <3>; 799 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 800 }; 801 802 csi: camera@1cb0000 { 803 compatible = "allwinner,sun8i-h3-csi"; 804 reg = <0x01cb0000 0x1000>; 805 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&ccu CLK_BUS_CSI>, 807 <&ccu CLK_CSI_SCLK>, 808 <&ccu CLK_DRAM_CSI>; 809 clock-names = "bus", "mod", "ram"; 810 resets = <&ccu RST_BUS_CSI>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&csi_pins>; 813 status = "disabled"; 814 }; 815 816 hdmi: hdmi@1ee0000 { 817 compatible = "allwinner,sun8i-h3-dw-hdmi", 818 "allwinner,sun8i-a83t-dw-hdmi"; 819 reg = <0x01ee0000 0x10000>; 820 reg-io-width = <1>; 821 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 823 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 824 clock-names = "iahb", "isfr", "tmds", "cec"; 825 resets = <&ccu RST_BUS_HDMI1>; 826 reset-names = "ctrl"; 827 phys = <&hdmi_phy>; 828 phy-names = "phy"; 829 status = "disabled"; 830 831 ports { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 835 hdmi_in: port@0 { 836 reg = <0>; 837 838 hdmi_in_tcon0: endpoint { 839 remote-endpoint = <&tcon0_out_hdmi>; 840 }; 841 }; 842 843 hdmi_out: port@1 { 844 reg = <1>; 845 }; 846 }; 847 }; 848 849 hdmi_phy: hdmi-phy@1ef0000 { 850 compatible = "allwinner,sun8i-h3-hdmi-phy"; 851 reg = <0x01ef0000 0x10000>; 852 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 853 <&ccu CLK_PLL_VIDEO>; 854 clock-names = "bus", "mod", "pll-0"; 855 resets = <&ccu RST_BUS_HDMI0>; 856 reset-names = "phy"; 857 #phy-cells = <0>; 858 }; 859 860 rtc: rtc@1f00000 { 861 /* compatible is in per SoC .dtsi file */ 862 reg = <0x01f00000 0x400>; 863 interrupt-parent = <&r_intc>; 864 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 866 clock-output-names = "osc32k", "osc32k-out", "iosc"; 867 clocks = <&osc32k>; 868 #clock-cells = <1>; 869 }; 870 871 r_intc: interrupt-controller@1f00c00 { 872 compatible = "allwinner,sun8i-h3-r-intc", 873 "allwinner,sun6i-a31-r-intc"; 874 interrupt-controller; 875 #interrupt-cells = <3>; 876 reg = <0x01f00c00 0x400>; 877 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 878 }; 879 880 r_ccu: clock@1f01400 { 881 compatible = "allwinner,sun8i-h3-r-ccu"; 882 reg = <0x01f01400 0x100>; 883 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 884 <&ccu CLK_PLL_PERIPH0>; 885 clock-names = "hosc", "losc", "iosc", "pll-periph"; 886 #clock-cells = <1>; 887 #reset-cells = <1>; 888 }; 889 890 codec_analog: codec-analog@1f015c0 { 891 compatible = "allwinner,sun8i-h3-codec-analog"; 892 reg = <0x01f015c0 0x4>; 893 }; 894 895 ir: ir@1f02000 { 896 compatible = "allwinner,sun6i-a31-ir"; 897 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 898 clock-names = "apb", "ir"; 899 resets = <&r_ccu RST_APB0_IR>; 900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 901 reg = <0x01f02000 0x400>; 902 status = "disabled"; 903 }; 904 905 r_i2c: i2c@1f02400 { 906 compatible = "allwinner,sun6i-a31-i2c"; 907 reg = <0x01f02400 0x400>; 908 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&r_i2c_pins>; 911 clocks = <&r_ccu CLK_APB0_I2C>; 912 resets = <&r_ccu RST_APB0_I2C>; 913 status = "disabled"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 }; 917 918 r_uart: serial@1f02800 { 919 compatible = "snps,dw-apb-uart"; 920 reg = <0x01f02800 0x400>; 921 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 922 reg-shift = <2>; 923 reg-io-width = <4>; 924 clocks = <&r_ccu CLK_APB0_UART>; 925 resets = <&r_ccu RST_APB0_UART>; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&r_uart_pins>; 928 status = "disabled"; 929 }; 930 931 r_pio: pinctrl@1f02c00 { 932 compatible = "allwinner,sun8i-h3-r-pinctrl"; 933 reg = <0x01f02c00 0x400>; 934 interrupt-parent = <&r_intc>; 935 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 937 <&rtc CLK_OSC32K>; 938 clock-names = "apb", "hosc", "losc"; 939 gpio-controller; 940 #gpio-cells = <3>; 941 interrupt-controller; 942 #interrupt-cells = <3>; 943 944 r_ir_rx_pin: r-ir-rx-pin { 945 pins = "PL11"; 946 function = "s_cir_rx"; 947 }; 948 949 r_i2c_pins: r-i2c-pins { 950 pins = "PL0", "PL1"; 951 function = "s_i2c"; 952 }; 953 954 r_pwm_pin: r-pwm-pin { 955 pins = "PL10"; 956 function = "s_pwm"; 957 }; 958 959 r_uart_pins: r-uart-pins { 960 pins = "PL2", "PL3"; 961 function = "s_uart"; 962 }; 963 }; 964 965 r_pwm: pwm@1f03800 { 966 compatible = "allwinner,sun8i-h3-pwm"; 967 reg = <0x01f03800 0x8>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&r_pwm_pin>; 970 clocks = <&osc24M>; 971 #pwm-cells = <3>; 972 status = "disabled"; 973 }; 974 }; 975}; 976