1// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2/*
3 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
4 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
5 */
6
7#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	interrupt-parent = <&intc>;
14
15	clocks {
16		osc24M: clk-24M {
17			#clock-cells = <0>;
18			compatible = "fixed-clock";
19			clock-frequency = <24000000>;
20			clock-output-names = "osc24M";
21		};
22
23		osc32k: clk-32k {
24			#clock-cells = <0>;
25			compatible = "fixed-clock";
26			clock-frequency = <32768>;
27			clock-output-names = "osc32k";
28		};
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			compatible = "arm,arm926ej-s";
37			device_type = "cpu";
38			reg = <0x0>;
39		};
40	};
41
42	soc {
43		compatible = "simple-bus";
44		#address-cells = <1>;
45		#size-cells = <1>;
46		ranges;
47
48		sram-controller@1c00000 {
49			compatible = "allwinner,suniv-f1c100s-system-control",
50				     "allwinner,sun4i-a10-system-control";
51			reg = <0x01c00000 0x30>;
52			#address-cells = <1>;
53			#size-cells = <1>;
54			ranges;
55
56			sram_d: sram@10000 {
57				compatible = "mmio-sram";
58				reg = <0x00010000 0x1000>;
59				#address-cells = <1>;
60				#size-cells = <1>;
61				ranges = <0 0x00010000 0x1000>;
62
63				otg_sram: sram-section@0 {
64					compatible = "allwinner,suniv-f1c100s-sram-d",
65						     "allwinner,sun4i-a10-sram-d";
66					reg = <0x0000 0x1000>;
67					status = "disabled";
68				};
69			};
70		};
71
72		spi0: spi@1c05000 {
73			compatible = "allwinner,suniv-f1c100s-spi",
74				     "allwinner,sun8i-h3-spi";
75			reg = <0x01c05000 0x1000>;
76			interrupts = <10>;
77			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
78			clock-names = "ahb", "mod";
79			resets = <&ccu RST_BUS_SPI0>;
80			status = "disabled";
81			num-cs = <1>;
82			#address-cells = <1>;
83			#size-cells = <0>;
84		};
85
86		spi1: spi@1c06000 {
87			compatible = "allwinner,suniv-f1c100s-spi",
88				     "allwinner,sun8i-h3-spi";
89			reg = <0x01c06000 0x1000>;
90			interrupts = <11>;
91			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
92			clock-names = "ahb", "mod";
93			resets = <&ccu RST_BUS_SPI1>;
94			status = "disabled";
95			num-cs = <1>;
96			#address-cells = <1>;
97			#size-cells = <0>;
98		};
99
100		mmc0: mmc@1c0f000 {
101			compatible = "allwinner,suniv-f1c100s-mmc",
102				     "allwinner,sun7i-a20-mmc";
103			reg = <0x01c0f000 0x1000>;
104			clocks = <&ccu CLK_BUS_MMC0>,
105				 <&ccu CLK_MMC0>,
106				 <&ccu CLK_MMC0_OUTPUT>,
107				 <&ccu CLK_MMC0_SAMPLE>;
108			clock-names = "ahb", "mmc", "output", "sample";
109			resets = <&ccu RST_BUS_MMC0>;
110			reset-names = "ahb";
111			interrupts = <23>;
112			pinctrl-names = "default";
113			pinctrl-0 = <&mmc0_pins>;
114			status = "disabled";
115			#address-cells = <1>;
116			#size-cells = <0>;
117		};
118
119		mmc1: mmc@1c10000 {
120			compatible = "allwinner,suniv-f1c100s-mmc",
121				     "allwinner,sun7i-a20-mmc";
122			reg = <0x01c10000 0x1000>;
123			clocks = <&ccu CLK_BUS_MMC1>,
124				 <&ccu CLK_MMC1>,
125				 <&ccu CLK_MMC1_OUTPUT>,
126				 <&ccu CLK_MMC1_SAMPLE>;
127			clock-names = "ahb", "mmc", "output", "sample";
128			resets = <&ccu RST_BUS_MMC1>;
129			reset-names = "ahb";
130			interrupts = <24>;
131			status = "disabled";
132			#address-cells = <1>;
133			#size-cells = <0>;
134		};
135
136		ccu: clock@1c20000 {
137			compatible = "allwinner,suniv-f1c100s-ccu";
138			reg = <0x01c20000 0x400>;
139			clocks = <&osc24M>, <&osc32k>;
140			clock-names = "hosc", "losc";
141			#clock-cells = <1>;
142			#reset-cells = <1>;
143		};
144
145		intc: interrupt-controller@1c20400 {
146			compatible = "allwinner,suniv-f1c100s-ic";
147			reg = <0x01c20400 0x400>;
148			interrupt-controller;
149			#interrupt-cells = <1>;
150		};
151
152		pio: pinctrl@1c20800 {
153			compatible = "allwinner,suniv-f1c100s-pinctrl";
154			reg = <0x01c20800 0x400>;
155			interrupts = <38>, <39>, <40>;
156			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
157			clock-names = "apb", "hosc", "losc";
158			gpio-controller;
159			interrupt-controller;
160			#interrupt-cells = <3>;
161			#gpio-cells = <3>;
162
163			mmc0_pins: mmc0-pins {
164				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
165				function = "mmc0";
166				drive-strength = <30>;
167			};
168
169			spi0_pc_pins: spi0-pc-pins {
170				pins = "PC0", "PC1", "PC2", "PC3";
171				function = "spi0";
172			};
173
174			uart0_pe_pins: uart0-pe-pins {
175				pins = "PE0", "PE1";
176				function = "uart0";
177			};
178		};
179
180		timer@1c20c00 {
181			compatible = "allwinner,suniv-f1c100s-timer";
182			reg = <0x01c20c00 0x90>;
183			interrupts = <13>, <14>, <15>;
184			clocks = <&osc24M>;
185		};
186
187		wdt: watchdog@1c20ca0 {
188			compatible = "allwinner,suniv-f1c100s-wdt",
189				     "allwinner,sun6i-a31-wdt";
190			reg = <0x01c20ca0 0x20>;
191			interrupts = <16>;
192			clocks = <&osc32k>;
193		};
194
195		uart0: serial@1c25000 {
196			compatible = "snps,dw-apb-uart";
197			reg = <0x01c25000 0x400>;
198			interrupts = <1>;
199			reg-shift = <2>;
200			reg-io-width = <4>;
201			clocks = <&ccu CLK_BUS_UART0>;
202			resets = <&ccu RST_BUS_UART0>;
203			status = "disabled";
204		};
205
206		uart1: serial@1c25400 {
207			compatible = "snps,dw-apb-uart";
208			reg = <0x01c25400 0x400>;
209			interrupts = <2>;
210			reg-shift = <2>;
211			reg-io-width = <4>;
212			clocks = <&ccu CLK_BUS_UART1>;
213			resets = <&ccu RST_BUS_UART1>;
214			status = "disabled";
215		};
216
217		uart2: serial@1c25800 {
218			compatible = "snps,dw-apb-uart";
219			reg = <0x01c25800 0x400>;
220			interrupts = <3>;
221			reg-shift = <2>;
222			reg-io-width = <4>;
223			clocks = <&ccu CLK_BUS_UART2>;
224			resets = <&ccu RST_BUS_UART2>;
225			status = "disabled";
226		};
227	};
228};
229