1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018 NXP
5 */
6
7/dts-v1/;
8#include "ls1021a.dtsi"
9
10/ {
11	model = "LS1021A QDS Board";
12	compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
13
14	aliases {
15		enet0_rgmii_phy = &rgmii_phy1;
16		enet1_rgmii_phy = &rgmii_phy2;
17		enet2_rgmii_phy = &rgmii_phy3;
18		enet0_sgmii_phy = &sgmii_phy1c;
19		enet1_sgmii_phy = &sgmii_phy1d;
20	};
21
22	sys_mclk: clock-mclk {
23		compatible = "fixed-clock";
24		#clock-cells = <0>;
25		clock-frequency = <24576000>;
26	};
27
28	reg_3p3v: regulator {
29		compatible = "regulator-fixed";
30		regulator-name = "3P3V";
31		regulator-min-microvolt = <3300000>;
32		regulator-max-microvolt = <3300000>;
33		regulator-always-on;
34	};
35
36	sound {
37		compatible = "simple-audio-card";
38		simple-audio-card,format = "i2s";
39		simple-audio-card,widgets =
40			"Microphone", "Microphone Jack",
41			"Headphone", "Headphone Jack",
42			"Speaker", "Speaker Ext",
43			"Line", "Line In Jack";
44		simple-audio-card,routing =
45			"MIC_IN", "Microphone Jack",
46			"Microphone Jack", "Mic Bias",
47			"LINE_IN", "Line In Jack",
48			"Headphone Jack", "HP_OUT",
49			"Speaker Ext", "LINE_OUT";
50
51		simple-audio-card,cpu {
52			sound-dai = <&sai2>;
53			frame-master;
54			bitclock-master;
55		};
56
57		simple-audio-card,codec {
58			sound-dai = <&codec>;
59			frame-master;
60			bitclock-master;
61		};
62	};
63};
64
65&dspi0 {
66	bus-num = <0>;
67	status = "okay";
68
69	dspiflash: at45db021d@0 {
70		#address-cells = <1>;
71		#size-cells = <1>;
72		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
73		spi-max-frequency = <16000000>;
74		spi-cpol;
75		spi-cpha;
76		reg = <0>;
77	};
78};
79
80&enet0 {
81	tbi-handle = <&tbi0>;
82	phy-handle = <&sgmii_phy1c>;
83	phy-connection-type = "sgmii";
84	status = "okay";
85};
86
87&enet1 {
88	tbi-handle = <&tbi0>;
89	phy-handle = <&sgmii_phy1d>;
90	phy-connection-type = "sgmii";
91	status = "okay";
92};
93
94&enet2 {
95	phy-handle = <&rgmii_phy3>;
96	phy-connection-type = "rgmii-id";
97	status = "okay";
98};
99
100&esdhc {
101	status = "okay";
102};
103
104&i2c0 {
105	status = "okay";
106
107	pca9547: mux@77 {
108		compatible = "nxp,pca9547";
109		reg = <0x77>;
110		#address-cells = <1>;
111		#size-cells = <0>;
112
113		i2c@0 {
114			#address-cells = <1>;
115			#size-cells = <0>;
116			reg = <0x0>;
117
118			ds3232: rtc@68 {
119				compatible = "dallas,ds3232";
120				reg = <0x68>;
121				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
122			};
123		};
124
125		i2c@2 {
126			#address-cells = <1>;
127			#size-cells = <0>;
128			reg = <0x2>;
129
130			ina220@40 {
131				compatible = "ti,ina220";
132				reg = <0x40>;
133				shunt-resistor = <1000>;
134			};
135
136			ina220@41 {
137				compatible = "ti,ina220";
138				reg = <0x41>;
139				shunt-resistor = <1000>;
140			};
141		};
142
143		i2c@3 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			reg = <0x3>;
147
148			eeprom@56 {
149				compatible = "atmel,24c512";
150				reg = <0x56>;
151			};
152
153			eeprom@57 {
154				compatible = "atmel,24c512";
155				reg = <0x57>;
156			};
157
158			adt7461a@4c {
159				compatible = "adi,adt7461a";
160				reg = <0x4c>;
161			};
162		};
163
164		i2c@4 {
165			#address-cells = <1>;
166			#size-cells = <0>;
167			reg = <0x4>;
168
169			codec: sgtl5000@2a {
170				#sound-dai-cells = <0>;
171				compatible = "fsl,sgtl5000";
172				reg = <0x2a>;
173				VDDA-supply = <&reg_3p3v>;
174				VDDIO-supply = <&reg_3p3v>;
175				clocks = <&sys_mclk>;
176			};
177		};
178	};
179};
180
181&ifc {
182	#address-cells = <2>;
183	#size-cells = <1>;
184	/* NOR, NAND Flashes and FPGA on board */
185	ranges = <0x0 0x0 0x0 0x60000000 0x08000000>,
186		 <0x2 0x0 0x0 0x7e800000 0x00010000>,
187		 <0x3 0x0 0x0 0x7fb00000 0x00000100>;
188	status = "okay";
189
190	nor@0,0 {
191		#address-cells = <1>;
192		#size-cells = <1>;
193		compatible = "cfi-flash";
194		reg = <0x0 0x0 0x8000000>;
195		big-endian;
196		bank-width = <2>;
197		device-width = <1>;
198	};
199
200	nand@2,0 {
201		compatible = "fsl,ifc-nand";
202		reg = <0x2 0x0 0x10000>;
203	};
204
205	fpga: board-control@3,0 {
206		#address-cells = <1>;
207		#size-cells = <1>;
208		compatible = "simple-mfd";
209		reg = <0x3 0x0 0x0000100>;
210		bank-width = <1>;
211		device-width = <1>;
212		ranges = <0 3 0 0x100>;
213
214		mdio-mux-emi1 {
215			compatible = "mdio-mux-mmioreg";
216			mdio-parent-bus = <&mdio0>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0x54 1>; /* BRDCFG4 */
220			mux-mask = <0xe0>; /* EMI1[2:0] */
221
222			/* Onboard PHYs */
223			ls1021amdio0: mdio@0 {
224				reg = <0>;
225				#address-cells = <1>;
226				#size-cells = <0>;
227				rgmii_phy1: ethernet-phy@1 {
228					reg = <0x1>;
229				};
230			};
231
232			ls1021amdio1: mdio@20 {
233				reg = <0x20>;
234				#address-cells = <1>;
235				#size-cells = <0>;
236				rgmii_phy2: ethernet-phy@2 {
237					reg = <0x2>;
238				};
239			};
240
241			ls1021amdio2: mdio@40 {
242				reg = <0x40>;
243				#address-cells = <1>;
244				#size-cells = <0>;
245				rgmii_phy3: ethernet-phy@3 {
246					reg = <0x3>;
247				};
248			};
249
250			ls1021amdio3: mdio@60 {
251				reg = <0x60>;
252				#address-cells = <1>;
253				#size-cells = <0>;
254				sgmii_phy1c: ethernet-phy@1c {
255					reg = <0x1c>;
256				};
257			};
258
259			ls1021amdio4: mdio@80 {
260				reg = <0x80>;
261				#address-cells = <1>;
262				#size-cells = <0>;
263				sgmii_phy1d: ethernet-phy@1d {
264					reg = <0x1d>;
265				};
266			};
267		};
268	};
269};
270
271&lpuart0 {
272	status = "okay";
273};
274
275&mdio0 {
276	tbi0: tbi-phy@8 {
277		reg = <0x8>;
278		device_type = "tbi-phy";
279	};
280};
281
282&qspi {
283	status = "okay";
284
285	flash@0 {
286		compatible = "jedec,spi-nor";
287		#address-cells = <1>;
288		#size-cells = <1>;
289		spi-max-frequency = <20000000>;
290		reg = <0>;
291		spi-rx-bus-width = <4>;
292		spi-tx-bus-width = <4>;
293	};
294};
295
296&sai2 {
297	status = "okay";
298};
299
300&sata {
301	status = "okay";
302};
303
304&uart0 {
305	status = "okay";
306};
307
308&uart1 {
309	status = "okay";
310};
311
312&can0 {
313	status = "okay";
314};
315
316&can1 {
317	status = "okay";
318};
319
320&can2 {
321	status = "disabled";
322};
323
324&can3 {
325	status = "disabled";
326};
327