1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2016 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include "imx6ul.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12	model = "Protonic PRTI6G Board";
13	compatible = "prt,prti6g", "fsl,imx6ul";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	clock_ksz8081_in: clock-ksz8081-in {
20		compatible = "fixed-clock";
21		#clock-cells = <0>;
22		clock-frequency = <25000000>;
23	};
24
25	clock_ksz8081_out: clock-ksz8081-out {
26		compatible = "fixed-clock";
27		#clock-cells = <0>;
28		clock-frequency = <50000000>;
29	};
30
31	leds {
32		compatible = "gpio-leds";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_leds>;
35
36		led-0 {
37			label = "debug0";
38			gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
39			linux,default-trigger = "heartbeat";
40		};
41	};
42
43	reg_3v2: regulator-3v2 {
44		compatible = "regulator-fixed";
45		regulator-name = "3v2";
46		regulator-min-microvolt = <3200000>;
47		regulator-max-microvolt = <3200000>;
48	};
49};
50
51&can1 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_can1>;
54	status = "okay";
55};
56
57&can2 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_can2>;
60	status = "okay";
61};
62
63&ecspi1 {
64	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
65	pinctrl-names = "default";
66	pinctrl-0 = <&pinctrl_ecspi1>;
67	status = "okay";
68
69	flash@0 {
70		compatible = "jedec,spi-nor";
71		reg = <0>;
72		spi-max-frequency = <20000000>;
73	};
74};
75
76&ecspi2 {
77	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_ecspi2>;
80	status = "okay";
81};
82
83&fec1 {
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_eth1>;
86	phy-mode = "rmii";
87	phy-handle = <&rmii_phy>;
88	clocks = <&clks IMX6UL_CLK_ENET>,
89		 <&clks IMX6UL_CLK_ENET_AHB>,
90		 <&clks IMX6UL_CLK_ENET_PTP>,
91		 <&clock_ksz8081_out>;
92	clock-names = "ipg", "ahb", "ptp",
93		      "enet_clk_ref";
94	status = "okay";
95
96	mdio {
97		#address-cells = <1>;
98		#size-cells = <0>;
99
100		/* Microchip KSZ8081RNA PHY */
101		rmii_phy: ethernet-phy@0 {
102			reg = <0>;
103			interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
104			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
105			reset-assert-us = <10000>;
106			reset-deassert-us = <300>;
107			clocks = <&clock_ksz8081_in>;
108			clock-names = "rmii-ref";
109		};
110	};
111};
112
113&i2c1 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_i2c1>;
116	clock-frequency = <100000>;
117	status = "okay";
118
119	/* additional i2c devices are added automatically by the boot loader */
120};
121
122&i2c2 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&pinctrl_i2c2>;
125	clock-frequency = <100000>;
126	status = "okay";
127
128	adc@49 {
129		compatible = "ti,ads1015";
130		reg = <0x49>;
131		#address-cells = <1>;
132		#size-cells = <0>;
133
134		channel@4 {
135			reg = <4>;
136			ti,gain = <3>;
137			ti,datarate = <3>;
138		};
139
140		channel@5 {
141			reg = <5>;
142			ti,gain = <3>;
143			ti,datarate = <3>;
144		};
145
146		channel@6 {
147			reg = <6>;
148			ti,gain = <3>;
149			ti,datarate = <3>;
150		};
151
152		channel@7 {
153			reg = <7>;
154			ti,gain = <3>;
155			ti,datarate = <3>;
156		};
157	};
158
159	rtc@51 {
160		compatible = "nxp,pcf8563";
161		reg = <0x51>;
162	};
163
164	temperature-sensor@70 {
165		compatible = "ti,tmp103";
166		reg = <0x70>;
167	};
168};
169
170&uart1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_uart1>;
173	status = "okay";
174};
175
176&usbotg1 {
177	dr_mode = "host";
178	status = "okay";
179};
180
181&usdhc1 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_usdhc1>;
184	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
185	vmmc-supply = <&reg_3v2>;
186	no-1-8-v;
187	disable-wp;
188	cap-sd-highspeed;
189	no-mmc;
190	no-sdio;
191	status = "okay";
192};
193
194&usdhc2 {
195	pinctrl-names = "default";
196	pinctrl-0 = <&pinctrl_usdhc2>;
197	bus-width = <8>;
198	no-1-8-v;
199	non-removable;
200	no-sd;
201	no-sdio;
202	status = "okay";
203};
204
205&iomuxc {
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_hog>;
208
209	pinctrl_can1: can1grp {
210		fsl,pins = <
211			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX		0x0b0b0
212			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX		0x0b0b0
213			/* SR */
214			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03		0x0b0b0
215			/* TERM */
216			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04		0x0b0b0
217			/* nSMBALERT */
218			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02		0x0b0b0
219		>;
220	};
221
222	pinctrl_can2: can2grp {
223		fsl,pins = <
224			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX		0x0b0b0
225			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX		0x0b0b0
226			/* SR */
227			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05		0x0b0b0
228		>;
229	};
230
231	pinctrl_ecspi1: ecspi1grp {
232		fsl,pins = <
233			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK		0x0b0b0
234			MX6UL_PAD_CSI_DATA05__GPIO4_IO26		0x000b1
235			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI		0x0b0b0
236			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO		0x0b0b0
237		>;
238	};
239
240	pinctrl_ecspi2: ecspi2grp {
241		fsl,pins = <
242			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK		0x0b0b0
243			MX6UL_PAD_CSI_DATA01__GPIO4_IO22		0x000b1
244			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI		0x0b0b0
245			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO		0x0b0b0
246		>;
247	};
248
249	pinctrl_eth1: eth1grp {
250		fsl,pins = <
251			MX6UL_PAD_GPIO1_IO07__ENET1_MDC			0x1b0b0
252			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO		0x100b0
253			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00		0x1b0b0
254			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01		0x1b0b0
255			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN		0x100b0
256			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER		0x1b0b0
257			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN		0x1b0b0
258			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00		0x1b0b0
259			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01		0x1b0b0
260			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1		0x1b000
261			/* PHY ENET1_RST */
262			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00		0x00880
263			/* PHY ENET1_IRQ */
264			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01		0x00880
265		>;
266	};
267
268	pinctrl_hog: hoggrp {
269		fsl,pins = <
270			/* HW revision detect */
271			/* REV_ID0 */
272			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08		0x1b0b0
273			/* REV_ID1 */
274			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09		0x1b0b0
275			/* REV_ID2 */
276			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10		0x1b0b0
277			/* REV_ID3 */
278			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11		0x1b0b0
279			/* BOARD_ID0 */
280			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13		0x1b0b0
281			/* BOARD_ID1 */
282			MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14		0x1b0b0
283			/* BOARD_ID2 */
284			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15		0x1b0b0
285			/* BOARD_ID3 */
286			MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12		0x1b0b0
287			/* Safety controller IO */
288			/* WAKE_SC */
289			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06		0x1b0b0
290			/* PROGRAM_SC */
291			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07		0x1b0b0
292		>;
293	};
294
295	pinctrl_i2c1: i2c1grp {
296		fsl,pins = <
297			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
298			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
299		>;
300	};
301
302	pinctrl_i2c2: i2c2grp {
303		fsl,pins = <
304			MX6UL_PAD_CSI_VSYNC__I2C2_SDA		0x4001b8b0
305			MX6UL_PAD_CSI_HSYNC__I2C2_SCL		0x4001b8b0
306		>;
307	};
308
309	pinctrl_leds: ledsgrp {
310		fsl,pins = <
311			MX6UL_PAD_NAND_DQS__GPIO4_IO16			0x1b0b0
312		>;
313	};
314
315	pinctrl_uart1: uart1grp {
316		fsl,pins = <
317			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX		0x1b0b1
318			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX		0x1b0b1
319		>;
320	};
321
322	pinctrl_usdhc1: usdhc1grp {
323		fsl,pins = <
324			MX6UL_PAD_SD1_CMD__USDHC1_CMD			0x070b1
325			MX6UL_PAD_SD1_CLK__USDHC1_CLK			0x07099
326			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0		0x070b1
327			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1		0x070b1
328			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2		0x070b1
329			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3		0x070b1
330			/* SD1 CD */
331			MX6UL_PAD_NAND_READY_B__GPIO4_IO12		0x170b0
332		>;
333	};
334
335	pinctrl_usdhc2: usdhc2grp {
336		fsl,pins = <
337			MX6UL_PAD_NAND_WE_B__USDHC2_CMD			0x170f9
338			MX6UL_PAD_NAND_RE_B__USDHC2_CLK			0x100f9
339			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0		0x170f9
340			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1		0x170f9
341			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2		0x170f9
342			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3		0x170f9
343			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4		0x170f9
344			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5		0x170f9
345			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6		0x170f9
346			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7		0x170f9
347			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B		0x170b0
348		>;
349	};
350};
351