1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2018 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include "imx6qp.dtsi"
10
11/ {
12	model = "Protonic WD3 board";
13	compatible = "prt,prtwd3", "fsl,imx6qp";
14
15	chosen {
16		stdout-path = &uart4;
17	};
18
19	memory@10000000 {
20		device_type = "memory";
21		reg = <0x10000000 0x20000000>;
22	};
23
24	memory@80000000 {
25		device_type = "memory";
26		reg = <0x80000000 0x20000000>;
27	};
28
29	clock_ksz8081: clock-ksz8081 {
30		compatible = "fixed-clock";
31		#clock-cells = <0>;
32		clock-frequency = <50000000>;
33	};
34
35	clock_ksz9031: clock-ksz9031 {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <25000000>;
39	};
40
41	clock_mcp251xfd: clock-mcp251xfd {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <20000000>;
45	};
46
47	clock_sja1105: clock-sja1105 {
48		compatible = "fixed-clock";
49		#clock-cells = <0>;
50		clock-frequency = <25000000>;
51	};
52
53	mdio {
54		compatible = "virtual,mdio-gpio";
55		pinctrl-names = "default";
56		pinctrl-0 = <&pinctrl_mdio>;
57
58		#address-cells = <1>;
59		#size-cells = <0>;
60		gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
61			 &gpio5 7 GPIO_ACTIVE_HIGH>;
62
63		/* Microchip KSZ8081 */
64		usbeth_phy: ethernet-phy@3 {
65			reg = <0x3>;
66
67			interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
68			reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
69			reset-assert-us = <500>;
70			reset-deassert-us = <1000>;
71			clocks = <&clock_ksz8081>;
72			clock-names = "rmii-ref";
73			micrel,led-mode = <0>;
74		};
75
76		tja1102_phy0: ethernet-phy@4 {
77			reg = <0x4>;
78
79			interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
80			reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
81			reset-assert-us = <20>;
82			reset-deassert-us = <2000>;
83			#address-cells = <1>;
84			#size-cells = <0>;
85
86			tja1102_phy1: ethernet-phy@5 {
87				reg = <0x5>;
88
89				interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
90			};
91		};
92	};
93
94	reg_5v0: regulator-5v0 {
95		compatible = "regulator-fixed";
96		regulator-name = "5v0";
97		regulator-min-microvolt = <5000000>;
98		regulator-max-microvolt = <5000000>;
99	};
100
101	reg_otg_vbus: regulator-otg-vbus {
102		compatible = "regulator-fixed";
103		regulator-name = "otg-vbus";
104		regulator-min-microvolt = <5000000>;
105		regulator-max-microvolt = <5000000>;
106		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
107		enable-active-high;
108	};
109
110	usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
111		compatible = "mmc-pwrseq-simple";
112		pinctrl-names = "default";
113		pinctrl-0 = <&pinctrl_wifi_npd>;
114		reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
115	};
116};
117
118&can1 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_can1>;
121	xceiver-supply = <&reg_5v0>;
122	status = "okay";
123};
124
125&ecspi2 {
126	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_ecspi2>;
129	status = "okay";
130
131	switch@0 {
132		compatible = "nxp,sja1105q";
133		reg = <0>;
134		spi-max-frequency = <4000000>;
135		spi-rx-delay-us = <1>;
136		spi-tx-delay-us = <1>;
137		spi-cpha;
138
139		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
140
141		clocks = <&clock_sja1105>;
142
143		ports {
144			#address-cells = <1>;
145			#size-cells = <0>;
146
147			port@0 {
148				reg = <0>;
149				label = "usb";
150				phy-handle = <&usbeth_phy>;
151				phy-mode = "rmii";
152			};
153
154			port@1 {
155				reg = <1>;
156				label = "t1slave";
157				phy-handle = <&tja1102_phy1>;
158				phy-mode = "rmii";
159			};
160
161			port@2 {
162				reg = <2>;
163				label = "t1master";
164				phy-handle = <&tja1102_phy0>;
165				phy-mode = "rmii";
166
167			};
168
169			port@3 {
170				reg = <3>;
171				label = "rj45";
172				phy-handle = <&rgmii_phy>;
173				phy-mode = "rgmii-id";
174			};
175
176			port@4 {
177				reg = <4>;
178				label = "cpu";
179				ethernet = <&fec>;
180				phy-mode = "rgmii-id";
181				rx-internal-delay-ps = <2000>;
182				tx-internal-delay-ps = <2000>;
183
184				fixed-link {
185					speed = <100>;
186					full-duplex;
187				};
188			};
189		};
190	};
191};
192
193&ecspi3 {
194	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
195	pinctrl-names = "default";
196	pinctrl-0 = <&pinctrl_ecspi3>;
197	status = "okay";
198
199	can@0 {
200		compatible = "microchip,mcp251xfd";
201		pinctrl-names = "default";
202		pinctrl-0 = <&pinctrl_can2>;
203		reg = <0>;
204		clocks = <&clock_mcp251xfd>;
205		spi-max-frequency = <10000000>;
206		interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
207	};
208};
209
210&fec {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_enet>;
213	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
214	assigned-clock-rates = <125000000>;
215	status = "okay";
216
217	phy-mode = "rgmii";
218
219	fixed-link {
220		speed = <100>;
221		full-duplex;
222	};
223
224	mdio {
225		#address-cells = <1>;
226		#size-cells = <0>;
227
228		/* Microchip KSZ9031 */
229		rgmii_phy: ethernet-phy@2 {
230			reg = <2>;
231
232			interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
233			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
234			reset-assert-us = <10000>;
235			reset-deassert-us = <1000>;
236
237			clocks = <&clock_ksz9031>;
238		};
239	};
240};
241
242&gpio1 {
243	gpio-line-names =
244		"", "SD1_CD", "", "", "", "", "", "",
245		"", "", "", "", "", "", "", "",
246		"", "", "", "", "", "", "", "",
247		"", "PHY3_RESET", "", "", "PHY3_INT", "", "", "";
248};
249
250&gpio2 {
251	gpio-line-names =
252		"", "", "", "", "", "", "", "",
253		"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3",
254			"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
255		"", "", "", "", "", "", "", "",
256		"", "", "ECSPI2_SS0", "", "", "", "", "";
257};
258
259&gpio3 {
260	gpio-line-names =
261		"", "", "", "", "", "", "", "",
262		"", "", "", "", "", "", "", "",
263		"", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "",
264		"", "", "", "", "", "", "", "";
265};
266
267&gpio4 {
268	gpio-line-names =
269		"", "", "", "", "", "", "", "",
270		"", "", "", "", "CAN1_SR", "CAN2_SR", "", "",
271		"", "", "", "", "", "", "", "",
272		"ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", "";
273};
274
275&gpio5 {
276	gpio-line-names =
277		"", "", "", "", "", "SW_RESET", "", "",
278		"PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET",
279			"PHY0_INT", "", "", "",
280		"", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD",
281			"", "",
282		"", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ",
283			"DISP0_EN", "CAM_GPIO0";
284};
285
286&gpio6 {
287	gpio-line-names =
288		"LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD",
289			"CAM_LOCK", "", "POWER_TG",
290		"POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "",
291			"USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1",
292		"USB_ETH_CHG_ID2", "", "", "", "", "", "", "",
293		"", "", "", "", "", "", "", "";
294};
295
296&i2c1 {
297	clock-frequency = <100000>;
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_i2c1>;
300	status = "okay";
301
302	/* additional i2c devices are added automatically by the boot loader */
303};
304
305&i2c3 {
306	adc@49 {
307		compatible = "ti,ads1015";
308		reg = <0x49>;
309		#address-cells = <1>;
310		#size-cells = <0>;
311
312		/* VIN */
313		channel@4 {
314			reg = <4>;
315			ti,gain = <1>;
316			ti,datarate = <3>;
317		};
318
319		/* VBUS */
320		channel@5 {
321			reg = <5>;
322			ti,gain = <1>;
323			ti,datarate = <3>;
324		};
325
326		/* ICHG */
327		channel@6 {
328			reg = <6>;
329			ti,gain = <1>;
330			ti,datarate = <3>;
331		};
332
333		channel@7 {
334			reg = <7>;
335			ti,gain = <1>;
336			ti,datarate = <3>;
337		};
338	};
339};
340
341&uart4 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_uart4>;
344	status = "okay";
345};
346
347&usbotg {
348	vbus-supply = <&reg_otg_vbus>;
349	pinctrl-names = "default";
350	pinctrl-0 = <&pinctrl_usbotg>;
351	phy_type = "utmi";
352	dr_mode = "host";
353	disable-over-current;
354	status = "okay";
355};
356
357&usbphynop1 {
358	status = "disabled";
359};
360
361&usbphynop2 {
362	status = "disabled";
363};
364
365&usdhc1 {
366	pinctrl-names = "default";
367	pinctrl-0 = <&pinctrl_usdhc1>;
368	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
369	no-1-8-v;
370	disable-wp;
371	cap-sd-highspeed;
372	no-mmc;
373	no-sdio;
374	status = "okay";
375};
376
377&usdhc2 {
378	pinctrl-names = "default";
379	pinctrl-0 = <&pinctrl_usdhc2>;
380	no-1-8-v;
381	non-removable;
382	mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
383	status = "okay";
384	#address-cells = <1>;
385	#size-cells = <0>;
386
387	brcmf: bcrmf@1 {
388		reg = <1>;
389		compatible = "brcm,bcm4329-fmac";
390	};
391};
392
393&usdhc3 {
394	pinctrl-names = "default";
395	pinctrl-0 = <&pinctrl_usdhc3>;
396	bus-width = <8>;
397	no-1-8-v;
398	non-removable;
399	no-sd;
400	no-sdio;
401	status = "okay";
402};
403
404&iomuxc {
405	pinctrl_can1: can1grp {
406		fsl,pins = <
407			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX		0x1b000
408			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX		0x3008
409			/* CAN1_SR */
410			MX6QDL_PAD_KEY_COL3__GPIO4_IO12			0x13008
411		>;
412	};
413
414	pinctrl_can2: can2grp {
415		fsl,pins = <
416			/* CAN2_nINT */
417			MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25		0x1b0b1
418			/* CAN2_SR */
419			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13			0x13070
420		>;
421	};
422
423	pinctrl_ecspi2: ecspi2grp {
424		fsl,pins = <
425			MX6QDL_PAD_EIM_OE__ECSPI2_MISO			0x100b1
426			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK			0x100b1
427			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI			0x100b1
428			MX6QDL_PAD_EIM_RW__GPIO2_IO26			0x000b1
429		>;
430	};
431
432	pinctrl_ecspi3: ecspi3grp {
433		fsl,pins = <
434			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK		0x100b1
435			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI		0x100b1
436			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO		0x100b1
437			/* CS */
438			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24		0x000b1
439		>;
440	};
441
442	pinctrl_enet: enetgrp {
443		fsl,pins = <
444			MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b030
445			MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b030
446			MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b030
447			MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b030
448			MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b030
449			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b030
450			MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x10030
451			MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x10030
452			MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x10030
453			MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x10030
454			MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x10030
455			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x10030
456
457			MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x10030
458			MX6QDL_PAD_ENET_MDC__ENET_MDC			0x10030
459
460			/* Configure clock provider for RGMII ref clock */
461			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x4001b0b0
462			/* Configure clock consumer for RGMII ref clock */
463			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x10030
464
465			/* SJA1105Q switch reset */
466			MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05		0x10030
467
468			/* phy3/rgmii_phy reset */
469			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25		0x10030
470			/* phy3/rgmii_phy int */
471			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28		0x40010000
472		>;
473	};
474
475	pinctrl_i2c1: i2c1grp {
476		fsl,pins = <
477			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA			0x4001f8b1
478			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL			0x4001f8b1
479		>;
480	};
481
482	pinctrl_mdio: mdiogrp {
483		fsl,pins = <
484			/* phy0/usbeth_phy reset */
485			MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11		0x10030
486			/* phy0/usbeth_phy int */
487			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12		0x100b1
488
489			/* phy12/tja1102_phy0 reset */
490			MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09		0x10030
491			/* phy12/tja1102_phy0 int */
492			MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08		0x100b1
493			/* phy12/tja1102_phy0 enable. Set 100K pull-up */
494			MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10		0x1f030
495		>;
496	};
497
498	pinctrl_uart4: uart4grp {
499		fsl,pins = <
500			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA		0x1b0b1
501			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA		0x1b0b1
502		>;
503	};
504
505	pinctrl_usbotg: usbotggrp {
506		fsl,pins = <
507			MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x1b0b0
508			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
509		>;
510	};
511
512	pinctrl_usdhc1: usdhc1grp {
513		fsl,pins = <
514			MX6QDL_PAD_SD1_CMD__SD1_CMD			0x170f9
515			MX6QDL_PAD_SD1_CLK__SD1_CLK			0x100f9
516			MX6QDL_PAD_SD1_DAT0__SD1_DATA0			0x170f9
517			MX6QDL_PAD_SD1_DAT1__SD1_DATA1			0x170f9
518			MX6QDL_PAD_SD1_DAT2__SD1_DATA2			0x170f9
519			MX6QDL_PAD_SD1_DAT3__SD1_DATA3			0x170f9
520			MX6QDL_PAD_GPIO_1__GPIO1_IO01			0x1b0b0
521		>;
522	};
523
524	pinctrl_usdhc2: usdhc2grp {
525		fsl,pins = <
526			MX6QDL_PAD_SD2_CMD__SD2_CMD			0x170b9
527			MX6QDL_PAD_SD2_CLK__SD2_CLK			0x100b9
528			MX6QDL_PAD_SD2_DAT0__SD2_DATA0			0x170b9
529			MX6QDL_PAD_SD2_DAT1__SD2_DATA1			0x170b9
530			MX6QDL_PAD_SD2_DAT2__SD2_DATA2			0x170b9
531			MX6QDL_PAD_SD2_DAT3__SD2_DATA3			0x170b9
532		>;
533	};
534
535	pinctrl_usdhc3: usdhc3grp {
536		fsl,pins = <
537			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17099
538			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10099
539			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17099
540			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17099
541			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17099
542			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17099
543			MX6QDL_PAD_SD3_DAT4__SD3_DATA4			0x17099
544			MX6QDL_PAD_SD3_DAT5__SD3_DATA5			0x17099
545			MX6QDL_PAD_SD3_DAT6__SD3_DATA6			0x17099
546			MX6QDL_PAD_SD3_DAT7__SD3_DATA7			0x17099
547			MX6QDL_PAD_SD3_RST__SD3_RESET			0x1b0b1
548		>;
549	};
550
551	pinctrl_wifi_npd: wifinpd {
552		fsl,pins = <
553			/* WL_REG_ON */
554			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10		0x13069
555		>;
556	};
557};
558