1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm RPMH RSC
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15  resources can be written to the Trigger Command Set (TCS)  registers and
16  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17  sequence over an internal bus.
18
19  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22  be written to from Linux. The structure of each DRV follows the same template
23  with a few variations that are captured by the properties here.
24
25  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26  have powered off to facilitate idle power saving. TCS could be classified as::
27    ACTIVE  - Triggered by Linux
28    SLEEP   - Triggered by F/W
29    WAKE    - Triggered by F/W
30    CONTROL - Triggered by F/W
31  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
32
33  The order in which they are described in the DT, should match the hardware
34  configuration.
35
36  Requests can be made for the state of a resource, when the subsystem is
37  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38  resource state will be an aggregate of the sleep votes from each of those
39  subsystems. Clients may request a sleep value for their shared resources in
40  addition to the active mode requests.
41
42  Drivers that want to use the RSC to communicate with RPMH must specify their
43  bindings as child nodes of the RSC controllers they wish to communicate with.
44
45properties:
46  compatible:
47    const: qcom,rpmh-rsc
48
49  interrupts:
50    minItems: 1
51    maxItems: 4
52    description:
53      The interrupt that trips when a message complete/response is received for
54      this DRV from the accelerators.
55      Number of interrupts must match number of DRV blocks.
56
57  label:
58    description:
59      Name for the RSC. The name would be used in trace logs.
60
61  qcom,drv-id:
62    $ref: /schemas/types.yaml#/definitions/uint32
63    description:
64      The ID of the DRV in the RSC block that will be used by this controller.
65
66  qcom,tcs-config:
67    $ref: /schemas/types.yaml#/definitions/uint32-matrix
68    minItems: 4
69    maxItems: 4
70    items:
71      items:
72        - description: |
73            TCS type::
74             - ACTIVE_TCS
75             - SLEEP_TCS
76             - WAKE_TCS
77             - CONTROL_TCS
78          enum: [ 0, 1, 2, 3 ]
79        - description: Number of TCS
80    description: |
81      The tuple defining the configuration of TCS. Must have two cells which
82      describe each TCS type.  The order of the TCS must match the hardware
83      configuration.
84
85  qcom,tcs-offset:
86    $ref: /schemas/types.yaml#/definitions/uint32
87    description:
88      The offset of the TCS blocks.
89
90  reg:
91    minItems: 1
92    maxItems: 4
93
94  reg-names:
95    minItems: 1
96    items:
97      - const: drv-0
98      - const: drv-1
99      - const: drv-2
100      - const: drv-3
101
102  bcm-voter:
103    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
104
105  clock-controller:
106    $ref: /schemas/clock/qcom,rpmhcc.yaml#
107
108  power-controller:
109    $ref: /schemas/power/qcom,rpmpd.yaml#
110
111patternProperties:
112  '-regulators$':
113    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
114
115required:
116  - compatible
117  - interrupts
118  - qcom,drv-id
119  - qcom,tcs-config
120  - qcom,tcs-offset
121  - reg
122  - reg-names
123
124additionalProperties: false
125
126examples:
127  - |
128    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
129    // 2, the register offsets for DRV2 start at 0D00, the register
130    // calculations are like this::
131    // DRV0: 0x179C0000
132    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
133    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
134    // TCS-OFFSET: 0xD00
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
137
138    rsc@179c0000 {
139        compatible = "qcom,rpmh-rsc";
140        reg = <0x179c0000 0x10000>,
141              <0x179d0000 0x10000>,
142              <0x179e0000 0x10000>;
143        reg-names = "drv-0", "drv-1", "drv-2";
144        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
145                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
146                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
147        label = "apps_rsc";
148        qcom,tcs-offset = <0xd00>;
149        qcom,drv-id = <2>;
150        qcom,tcs-config = <ACTIVE_TCS  2>,
151                          <SLEEP_TCS   3>,
152                          <WAKE_TCS    3>,
153                          <CONTROL_TCS 1>;
154      };
155
156  - |
157    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
158    // register offsets for DRV0 start at 01C00, the register calculations are
159    // like this::
160    // DRV0: 0xAF20000
161    // TCS-OFFSET: 0x1C00
162    #include <dt-bindings/interrupt-controller/arm-gic.h>
163    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
164
165    rsc@af20000 {
166        compatible = "qcom,rpmh-rsc";
167        reg = <0xaf20000 0x10000>;
168        reg-names = "drv-0";
169        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
170        label = "disp_rsc";
171        qcom,tcs-offset = <0x1c00>;
172        qcom,drv-id = <0>;
173        qcom,tcs-config = <ACTIVE_TCS  0>,
174                          <SLEEP_TCS   1>,
175                          <WAKE_TCS    1>,
176                          <CONTROL_TCS 0>;
177    };
178
179  - |
180    #include <dt-bindings/interrupt-controller/arm-gic.h>
181    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
182    #include <dt-bindings/power/qcom-rpmpd.h>
183
184    rsc@18200000 {
185        compatible = "qcom,rpmh-rsc";
186        reg = <0x18200000 0x10000>,
187              <0x18210000 0x10000>,
188              <0x18220000 0x10000>;
189        reg-names = "drv-0", "drv-1", "drv-2";
190        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
191                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
192                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
193        label = "apps_rsc";
194        qcom,tcs-offset = <0xd00>;
195        qcom,drv-id = <2>;
196        qcom,tcs-config = <ACTIVE_TCS  2>,
197                          <SLEEP_TCS   3>,
198                          <WAKE_TCS    3>,
199                          <CONTROL_TCS 0>;
200
201        clock-controller {
202            compatible = "qcom,sm8350-rpmh-clk";
203            #clock-cells = <1>;
204            clock-names = "xo";
205            clocks = <&xo_board>;
206        };
207
208        power-controller {
209            compatible = "qcom,sm8350-rpmhpd";
210            #power-domain-cells = <1>;
211            operating-points-v2 = <&rpmhpd_opp_table>;
212
213            rpmhpd_opp_table: opp-table {
214                compatible = "operating-points-v2";
215
216                rpmhpd_opp_ret: opp1 {
217                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
218                };
219
220                rpmhpd_opp_min_svs: opp2 {
221                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
222                };
223
224                rpmhpd_opp_low_svs: opp3 {
225                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
226                };
227
228                rpmhpd_opp_svs: opp4 {
229                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
230                };
231
232                rpmhpd_opp_svs_l1: opp5 {
233                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
234                };
235
236                rpmhpd_opp_nom: opp6 {
237                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
238                };
239
240                rpmhpd_opp_nom_l1: opp7 {
241                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
242                };
243
244                rpmhpd_opp_nom_l2: opp8 {
245                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
246                };
247
248                rpmhpd_opp_turbo: opp9 {
249                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
250                };
251
252                rpmhpd_opp_turbo_l1: opp10 {
253                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
254                };
255            };
256        };
257
258        bcm-voter {
259            compatible = "qcom,bcm-voter";
260        };
261    };
262