1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Composable Cache Controller
9
10maintainers:
11  - Sagar Kadam <sagar.kadam@sifive.com>
12  - Paul Walmsley  <paul.walmsley@sifive.com>
13
14description:
15  The SiFive Composable Cache Controller is used to provide access to fast copies
16  of memory for masters in a Core Complex. The Composable Cache Controller also
17  acts as directory-based coherency manager.
18  All the properties in ePAPR/DeviceTree specification applies for this platform.
19
20select:
21  properties:
22    compatible:
23      contains:
24        enum:
25          - sifive,ccache0
26          - sifive,fu540-c000-ccache
27          - sifive,fu740-c000-ccache
28
29  required:
30    - compatible
31
32properties:
33  compatible:
34    oneOf:
35      - items:
36          - enum:
37              - sifive,ccache0
38              - sifive,fu540-c000-ccache
39              - sifive,fu740-c000-ccache
40          - const: cache
41      - items:
42          - const: microchip,mpfs-ccache
43          - const: sifive,fu540-c000-ccache
44          - const: cache
45
46  cache-block-size:
47    const: 64
48
49  cache-level:
50    enum: [2, 3]
51
52  cache-sets:
53    enum: [1024, 2048]
54
55  cache-size:
56    const: 2097152
57
58  cache-unified: true
59
60  interrupts:
61    minItems: 3
62    items:
63      - description: DirError interrupt
64      - description: DataError interrupt
65      - description: DataFail interrupt
66      - description: DirFail interrupt
67
68  reg:
69    maxItems: 1
70
71  next-level-cache: true
72
73  memory-region:
74    maxItems: 1
75    description: |
76      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
77      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
78
79allOf:
80  - $ref: /schemas/cache-controller.yaml#
81
82  - if:
83      properties:
84        compatible:
85          contains:
86            enum:
87              - sifive,fu740-c000-ccache
88              - microchip,mpfs-ccache
89
90    then:
91      properties:
92        interrupts:
93          description: |
94            Must contain entries for DirError, DataError, DataFail, DirFail signals.
95          minItems: 4
96
97    else:
98      properties:
99        interrupts:
100          description: |
101            Must contain entries for DirError, DataError and DataFail signals.
102          maxItems: 3
103
104  - if:
105      properties:
106        compatible:
107          contains:
108            const: sifive,fu740-c000-ccache
109
110    then:
111      properties:
112        cache-sets:
113          const: 2048
114
115    else:
116      properties:
117        cache-sets:
118          const: 1024
119
120  - if:
121      properties:
122        compatible:
123          contains:
124            const: sifive,ccache0
125
126    then:
127      properties:
128        cache-level:
129          enum: [2, 3]
130
131    else:
132      properties:
133        cache-level:
134          const: 2
135
136additionalProperties: false
137
138required:
139  - compatible
140  - cache-block-size
141  - cache-level
142  - cache-sets
143  - cache-size
144  - cache-unified
145  - interrupts
146  - reg
147
148examples:
149  - |
150    cache-controller@2010000 {
151        compatible = "sifive,fu540-c000-ccache", "cache";
152        cache-block-size = <64>;
153        cache-level = <2>;
154        cache-sets = <1024>;
155        cache-size = <2097152>;
156        cache-unified;
157        reg = <0x2010000 0x1000>;
158        interrupt-parent = <&plic0>;
159        interrupts = <1>,
160                     <2>,
161                     <3>;
162        next-level-cache = <&L25>;
163        memory-region = <&l2_lim>;
164    };
165