1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8  Low Power Island (LPI) TLMM block
9
10maintainers:
11  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
13description: |
14  This binding describes the Top Level Mode Multiplexer block found in the
15  LPASS LPI IP on most Qualcomm SoCs
16
17properties:
18  compatible:
19    const: qcom,sc8280xp-lpass-lpi-pinctrl
20
21  reg:
22    items:
23      - description: LPASS LPI TLMM Control and Status registers
24      - description: LPASS LPI pins SLEW registers
25
26  clocks:
27    items:
28      - description: LPASS Core voting clock
29      - description: LPASS Audio voting clock
30
31  clock-names:
32    items:
33      - const: core
34      - const: audio
35
36  gpio-controller: true
37
38  '#gpio-cells':
39    description: Specifying the pin number and flags, as defined in
40      include/dt-bindings/gpio/gpio.h
41    const: 2
42
43  gpio-ranges:
44    maxItems: 1
45
46#PIN CONFIGURATION NODES
47patternProperties:
48  '-pins$':
49    type: object
50    description:
51      Pinctrl node's client devices use subnodes for desired pin configuration.
52      Client device subnodes use below standard properties.
53    $ref: /schemas/pinctrl/pincfg-node.yaml
54
55    properties:
56      pins:
57        description:
58          List of gpio pins affected by the properties specified in this
59          subnode.
60        items:
61          pattern: "^gpio([0-1]|1[0-8]])$"
62
63      function:
64        enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
65                dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
66                dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
67                qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
68                i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
69                wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
70                ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75      drive-strength:
76        enum: [2, 4, 6, 8, 10, 12, 14, 16]
77        default: 2
78        description:
79          Selects the drive strength for the specified pins, in mA.
80
81      slew-rate:
82        enum: [0, 1, 2, 3]
83        default: 0
84        description: |
85          0: No adjustments
86          1: Higher Slew rate (faster edges)
87          2: Lower Slew rate (slower edges)
88          3: Reserved (No adjustments)
89
90      bias-pull-down: true
91
92      bias-pull-up: true
93
94      bias-disable: true
95
96      output-high: true
97
98      output-low: true
99
100    required:
101      - pins
102      - function
103
104    additionalProperties: false
105
106allOf:
107  - $ref: pinctrl.yaml#
108
109required:
110  - compatible
111  - reg
112  - clocks
113  - clock-names
114  - gpio-controller
115  - '#gpio-cells'
116  - gpio-ranges
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/sound/qcom,q6afe.h>
123    pinctrl@33c0000 {
124        compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
125        reg = <0x33c0000 0x20000>,
126              <0x3550000 0x10000>;
127        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
128                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
129        clock-names = "core", "audio";
130        gpio-controller;
131        #gpio-cells = <2>;
132        gpio-ranges = <&lpi_tlmm 0 0 18>;
133    };
134