1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    enum:
18      - qcom,mdss-dsi-ctrl
19      - qcom,dsi-ctrl-6g-qcm2290
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: dsi_ctrl
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display byte clock
33      - description: Display byte interface clock
34      - description: Display pixel clock
35      - description: Display core clock
36      - description: Display AHB clock
37      - description: Display AXI clock
38
39  clock-names:
40    items:
41      - const: byte
42      - const: byte_intf
43      - const: pixel
44      - const: core
45      - const: iface
46      - const: bus
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    const: dsi
53
54  "#address-cells": true
55
56  "#size-cells": true
57
58  syscon-sfpb:
59    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
60    $ref: "/schemas/types.yaml#/definitions/phandle"
61
62  qcom,dual-dsi-mode:
63    type: boolean
64    description: |
65      Indicates if the DSI controller is driving a panel which needs
66      2 DSI links.
67
68  assigned-clocks:
69    maxItems: 2
70    description: |
71      Parents of "byte" and "pixel" for the given platform.
72
73  assigned-clock-parents:
74    maxItems: 2
75    description: |
76      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
77
78  power-domains:
79    maxItems: 1
80
81  operating-points-v2: true
82
83  ports:
84    $ref: "/schemas/graph.yaml#/properties/ports"
85    description: |
86      Contains DSI controller input and output ports as children, each
87      containing one endpoint subnode.
88
89    properties:
90      port@0:
91        $ref: "/schemas/graph.yaml#/$defs/port-base"
92        unevaluatedProperties: false
93        description: |
94          Input endpoints of the controller.
95        properties:
96          endpoint:
97            $ref: /schemas/media/video-interfaces.yaml#
98            unevaluatedProperties: false
99            properties:
100              data-lanes:
101                maxItems: 4
102                minItems: 4
103                items:
104                  enum: [ 0, 1, 2, 3 ]
105
106      port@1:
107        $ref: "/schemas/graph.yaml#/$defs/port-base"
108        unevaluatedProperties: false
109        description: |
110          Output endpoints of the controller.
111        properties:
112          endpoint:
113            $ref: /schemas/media/video-interfaces.yaml#
114            unevaluatedProperties: false
115            properties:
116              data-lanes:
117                maxItems: 4
118                minItems: 4
119                items:
120                  enum: [ 0, 1, 2, 3 ]
121
122    required:
123      - port@0
124      - port@1
125
126required:
127  - compatible
128  - reg
129  - reg-names
130  - interrupts
131  - clocks
132  - clock-names
133  - phys
134  - phy-names
135  - assigned-clocks
136  - assigned-clock-parents
137  - ports
138
139additionalProperties: false
140
141examples:
142  - |
143     #include <dt-bindings/interrupt-controller/arm-gic.h>
144     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
145     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
146     #include <dt-bindings/power/qcom-rpmpd.h>
147
148     dsi@ae94000 {
149           compatible = "qcom,mdss-dsi-ctrl";
150           reg = <0x0ae94000 0x400>;
151           reg-names = "dsi_ctrl";
152
153           #address-cells = <1>;
154           #size-cells = <0>;
155
156           interrupt-parent = <&mdss>;
157           interrupts = <4>;
158
159           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
160                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
161                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
162                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
163                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
164                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
165           clock-names = "byte",
166                         "byte_intf",
167                         "pixel",
168                         "core",
169                         "iface",
170                         "bus";
171
172           phys = <&dsi0_phy>;
173           phy-names = "dsi";
174
175           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
176           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
177
178           power-domains = <&rpmhpd SC7180_CX>;
179           operating-points-v2 = <&dsi_opp_table>;
180
181           ports {
182                  #address-cells = <1>;
183                  #size-cells = <0>;
184
185                  port@0 {
186                          reg = <0>;
187                          dsi0_in: endpoint {
188                                   remote-endpoint = <&dpu_intf1_out>;
189                          };
190                  };
191
192                  port@1 {
193                          reg = <1>;
194                          dsi0_out: endpoint {
195                                   remote-endpoint = <&sn65dsi86_in>;
196                                   data-lanes = <0 1 2 3>;
197                          };
198                  };
199           };
200     };
201...
202