1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A10 Display Engine Frontend 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: | 14 The display engine frontend does formats conversion, scaling, 15 deinterlacing and color space conversion. 16 17properties: 18 compatible: 19 enum: 20 - allwinner,sun4i-a10-display-frontend 21 - allwinner,sun5i-a13-display-frontend 22 - allwinner,sun6i-a31-display-frontend 23 - allwinner,sun7i-a20-display-frontend 24 - allwinner,sun8i-a23-display-frontend 25 - allwinner,sun8i-a33-display-frontend 26 - allwinner,sun9i-a80-display-frontend 27 28 reg: 29 maxItems: 1 30 31 interrupts: 32 maxItems: 1 33 34 clocks: 35 items: 36 - description: The frontend interface clock 37 - description: The frontend module clock 38 - description: The frontend DRAM clock 39 40 clock-names: 41 items: 42 - const: ahb 43 - const: mod 44 - const: ram 45 46 # FIXME: This should be made required eventually once every SoC will 47 # have the MBUS declared. 48 interconnects: 49 maxItems: 1 50 51 # FIXME: This should be made required eventually once every SoC will 52 # have the MBUS declared. 53 interconnect-names: 54 const: dma-mem 55 56 resets: 57 maxItems: 1 58 59 ports: 60 $ref: /schemas/graph.yaml#/properties/ports 61 62 properties: 63 port@0: 64 $ref: /schemas/graph.yaml#/properties/port 65 description: | 66 Input endpoints of the controller. 67 68 port@1: 69 $ref: /schemas/graph.yaml#/properties/port 70 description: | 71 Output endpoints of the controller. 72 73 required: 74 - port@1 75 76required: 77 - compatible 78 - reg 79 - interrupts 80 - clocks 81 - clock-names 82 - resets 83 - ports 84 85additionalProperties: false 86 87examples: 88 - | 89 #include <dt-bindings/clock/sun4i-a10-ccu.h> 90 #include <dt-bindings/reset/sun4i-a10-ccu.h> 91 92 fe0: display-frontend@1e00000 { 93 compatible = "allwinner,sun4i-a10-display-frontend"; 94 reg = <0x01e00000 0x20000>; 95 interrupts = <47>; 96 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 97 <&ccu CLK_DRAM_DE_FE0>; 98 clock-names = "ahb", "mod", 99 "ram"; 100 resets = <&ccu RST_DE_FE0>; 101 102 ports { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 fe0_out: port@1 { 107 #address-cells = <1>; 108 #size-cells = <0>; 109 reg = <1>; 110 111 fe0_out_be0: endpoint@0 { 112 reg = <0>; 113 remote-endpoint = <&be0_in_fe0>; 114 }; 115 116 fe0_out_be1: endpoint@1 { 117 reg = <1>; 118 remote-endpoint = <&be1_in_fe0>; 119 }; 120 }; 121 }; 122 }; 123 124 125... 126