1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Multimedia Clock & Reset Controller Binding
8
9maintainers:
10  - Jeffrey Hugo <quic_jhugo@quicinc.com>
11  - Taniya Das <tdas@codeaurora.org>
12
13description: |
14  Qualcomm multimedia clock control module which supports the clocks, resets and
15  power domains.
16
17properties:
18  compatible:
19    enum:
20      - qcom,mmcc-apq8064
21      - qcom,mmcc-apq8084
22      - qcom,mmcc-msm8226
23      - qcom,mmcc-msm8660
24      - qcom,mmcc-msm8960
25      - qcom,mmcc-msm8974
26      - qcom,mmcc-msm8992
27      - qcom,mmcc-msm8994
28      - qcom,mmcc-msm8996
29      - qcom,mmcc-msm8998
30      - qcom,mmcc-sdm630
31      - qcom,mmcc-sdm660
32
33  clocks:
34    minItems: 8
35    maxItems: 10
36
37  clock-names:
38    minItems: 8
39    maxItems: 10
40
41  '#clock-cells':
42    const: 1
43
44  '#reset-cells':
45    const: 1
46
47  '#power-domain-cells':
48    const: 1
49
50  reg:
51    maxItems: 1
52
53  protected-clocks:
54    description:
55      Protected clock specifier list as per common clock binding
56
57  vdd-gfx-supply:
58    description:
59      Regulator supply for the GPU_GX GDSC
60
61required:
62  - compatible
63  - reg
64  - '#clock-cells'
65  - '#reset-cells'
66  - '#power-domain-cells'
67
68additionalProperties: false
69
70allOf:
71  - if:
72      properties:
73        compatible:
74          contains:
75            enum:
76              - qcom,mmcc-apq8064
77              - qcom,mmcc-msm8960
78    then:
79      properties:
80        clocks:
81          items:
82            - description: Board PXO source
83            - description: PLL 3 clock
84            - description: PLL 3 Vote clock
85            - description: DSI phy instance 1 dsi clock
86            - description: DSI phy instance 1 byte clock
87            - description: DSI phy instance 2 dsi clock
88            - description: DSI phy instance 2 byte clock
89            - description: HDMI phy PLL clock
90
91        clock-names:
92          items:
93            - const: pxo
94            - const: pll3
95            - const: pll8_vote
96            - const: dsi1pll
97            - const: dsi1pllbyte
98            - const: dsi2pll
99            - const: dsi2pllbyte
100            - const: hdmipll
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            enum:
107              - qcom,mmcc-msm8994
108              - qcom,mmcc-msm8998
109              - qcom,mmcc-sdm630
110              - qcom,mmcc-sdm660
111    then:
112      required:
113        - clocks
114        - clock-names
115
116  - if:
117      properties:
118        compatible:
119          contains:
120            const: qcom,mmcc-msm8994
121    then:
122      properties:
123        clocks:
124          items:
125            - description: Board XO source
126            - description: Global PLL 0 clock
127            - description: MMSS NoC AHB clock
128            - description: GFX3D clock
129            - description: DSI phy instance 0 dsi clock
130            - description: DSI phy instance 0 byte clock
131            - description: DSI phy instance 1 dsi clock
132            - description: DSI phy instance 1 byte clock
133            - description: HDMI phy PLL clock
134
135        clock-names:
136          items:
137            - const: xo
138            - const: gpll0
139            - const: mmssnoc_ahb
140            - const: oxili_gfx3d_clk_src
141            - const: dsi0pll
142            - const: dsi0pllbyte
143            - const: dsi1pll
144            - const: dsi1pllbyte
145            - const: hdmipll
146
147  - if:
148      properties:
149        compatible:
150          contains:
151            const: qcom,mmcc-msm8996
152    then:
153      properties:
154        clocks:
155          items:
156            - description: Board XO source
157            - description: Global PLL 0 clock
158            - description: MMSS NoC AHB clock
159            - description: DSI phy instance 0 dsi clock
160            - description: DSI phy instance 0 byte clock
161            - description: DSI phy instance 1 dsi clock
162            - description: DSI phy instance 1 byte clock
163            - description: HDMI phy PLL clock
164
165        clock-names:
166          items:
167            - const: xo
168            - const: gpll0
169            - const: gcc_mmss_noc_cfg_ahb_clk
170            - const: dsi0pll
171            - const: dsi0pllbyte
172            - const: dsi1pll
173            - const: dsi1pllbyte
174            - const: hdmipll
175
176  - if:
177      properties:
178        compatible:
179          contains:
180            const: qcom,mmcc-msm8998
181    then:
182      properties:
183        clocks:
184          items:
185            - description: Board XO source
186            - description: Global PLL 0 clock
187            - description: DSI phy instance 0 dsi clock
188            - description: DSI phy instance 0 byte clock
189            - description: DSI phy instance 1 dsi clock
190            - description: DSI phy instance 1 byte clock
191            - description: HDMI phy PLL clock
192            - description: DisplayPort phy PLL link clock
193            - description: DisplayPort phy PLL vco clock
194            - description: Test clock
195
196        clock-names:
197          items:
198            - const: xo
199            - const: gpll0
200            - const: dsi0dsi
201            - const: dsi0byte
202            - const: dsi1dsi
203            - const: dsi1byte
204            - const: hdmipll
205            - const: dplink
206            - const: dpvco
207            - const: core_bi_pll_test_se
208
209  - if:
210      properties:
211        compatible:
212          contains:
213            enum:
214              - qcom,mmcc-sdm630
215              - qcom,mmcc-sdm660
216    then:
217      properties:
218        clocks:
219          items:
220            - description: Board XO source
221            - description: Board sleep source
222            - description: Global PLL 0 clock
223            - description: Global PLL 0 DIV clock
224            - description: DSI phy instance 0 dsi clock
225            - description: DSI phy instance 0 byte clock
226            - description: DSI phy instance 1 dsi clock
227            - description: DSI phy instance 1 byte clock
228            - description: DisplayPort phy PLL link clock
229            - description: DisplayPort phy PLL vco clock
230
231        clock-names:
232          items:
233            - const: xo
234            - const: sleep_clk
235            - const: gpll0
236            - const: gpll0_div
237            - const: dsi0pll
238            - const: dsi0pllbyte
239            - const: dsi1pll
240            - const: dsi1pllbyte
241            - const: dp_link_2x_clk_divsel_five
242            - const: dp_vco_divided_clk_src_mux
243
244examples:
245  # Example for MMCC for MSM8960:
246  - |
247    clock-controller@4000000 {
248      compatible = "qcom,mmcc-msm8960";
249      reg = <0x4000000 0x1000>;
250      #clock-cells = <1>;
251      #reset-cells = <1>;
252      #power-domain-cells = <1>;
253    };
254...
255