1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX8M Family Clock Control Module Binding 8 9maintainers: 10 - Anson Huang <Anson.Huang@nxp.com> 11 12description: | 13 NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock 14 controller, which generates and supplies to all modules. 15 16properties: 17 compatible: 18 enum: 19 - fsl,imx8mm-ccm 20 - fsl,imx8mn-ccm 21 - fsl,imx8mp-ccm 22 - fsl,imx8mq-ccm 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 minItems: 6 29 maxItems: 7 30 31 clock-names: 32 minItems: 6 33 maxItems: 7 34 35 '#clock-cells': 36 const: 1 37 description: 38 The clock consumer should specify the desired clock by having the clock 39 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h 40 for the full list of i.MX8M clock IDs. 41 42required: 43 - compatible 44 - reg 45 - clocks 46 - clock-names 47 - '#clock-cells' 48 49allOf: 50 - if: 51 properties: 52 compatible: 53 contains: 54 const: fsl,imx8mq-ccm 55 then: 56 properties: 57 clocks: 58 items: 59 - description: 32k osc 60 - description: 25m osc 61 - description: 27m osc 62 - description: ext1 clock input 63 - description: ext2 clock input 64 - description: ext3 clock input 65 - description: ext4 clock input 66 clock-names: 67 items: 68 - const: ckil 69 - const: osc_25m 70 - const: osc_27m 71 - const: clk_ext1 72 - const: clk_ext2 73 - const: clk_ext3 74 - const: clk_ext4 75 else: 76 properties: 77 clocks: 78 items: 79 - description: 32k osc 80 - description: 24m osc 81 - description: ext1 clock input 82 - description: ext2 clock input 83 - description: ext3 clock input 84 - description: ext4 clock input 85 86 clock-names: 87 items: 88 - const: osc_32k 89 - const: osc_24m 90 - const: clk_ext1 91 - const: clk_ext2 92 - const: clk_ext3 93 - const: clk_ext4 94 95additionalProperties: false 96 97examples: 98 # Clock Control Module node: 99 - | 100 clock-controller@30380000 { 101 compatible = "fsl,imx8mm-ccm"; 102 reg = <0x30380000 0x10000>; 103 #clock-cells = <1>; 104 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 105 <&clk_ext3>, <&clk_ext4>; 106 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 107 "clk_ext3", "clk_ext4"; 108 }; 109 110 - | 111 clock-controller@30390000 { 112 compatible = "fsl,imx8mq-ccm"; 113 reg = <0x30380000 0x10000>; 114 #clock-cells = <1>; 115 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, 116 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; 117 clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", 118 "clk_ext2", "clk_ext3", "clk_ext4"; 119 }; 120 121... 122