1[ 2 { 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x08", 7 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 9 "SampleAfterValue": "100003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "EventCode": "0x08", 17 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 18 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 19 "SampleAfterValue": "100003", 20 "UMask": "0x80" 21 }, 22 { 23 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0x08", 27 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 28 "PublicDescription": "Number of cache load STLB hits. No page walk.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x60" 31 }, 32 { 33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 34 "Counter": "0,1,2,3", 35 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "EventCode": "0x08", 37 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 38 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x40" 41 }, 42 { 43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0x08", 47 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 48 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 49 "SampleAfterValue": "2000003", 50 "UMask": "0x20" 51 }, 52 { 53 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 54 "Counter": "0,1,2,3", 55 "CounterHTOff": "0,1,2,3,4,5,6,7", 56 "EventCode": "0x08", 57 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 58 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 59 "SampleAfterValue": "100003", 60 "UMask": "0xe" 61 }, 62 { 63 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0x08", 67 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 68 "SampleAfterValue": "2000003", 69 "UMask": "0x8" 70 }, 71 { 72 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 73 "Counter": "0,1,2,3", 74 "CounterHTOff": "0,1,2,3,4,5,6,7", 75 "EventCode": "0x08", 76 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 77 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 78 "SampleAfterValue": "2000003", 79 "UMask": "0x4" 80 }, 81 { 82 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 83 "Counter": "0,1,2,3", 84 "CounterHTOff": "0,1,2,3,4,5,6,7", 85 "EventCode": "0x08", 86 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 87 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 88 "SampleAfterValue": "2000003", 89 "UMask": "0x2" 90 }, 91 { 92 "BriefDescription": "Cycles when PMH is busy with page walks", 93 "Counter": "0,1,2,3", 94 "CounterHTOff": "0,1,2,3,4,5,6,7", 95 "EventCode": "0x08", 96 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 97 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 98 "SampleAfterValue": "2000003", 99 "UMask": "0x10" 100 }, 101 { 102 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 103 "Counter": "0,1,2,3", 104 "CounterHTOff": "0,1,2,3,4,5,6,7", 105 "EventCode": "0x49", 106 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 107 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 108 "SampleAfterValue": "100003", 109 "UMask": "0x1" 110 }, 111 { 112 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 113 "Counter": "0,1,2,3", 114 "CounterHTOff": "0,1,2,3,4,5,6,7", 115 "EventCode": "0x49", 116 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 117 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 118 "SampleAfterValue": "100003", 119 "UMask": "0x80" 120 }, 121 { 122 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 123 "Counter": "0,1,2,3", 124 "CounterHTOff": "0,1,2,3,4,5,6,7", 125 "EventCode": "0x49", 126 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 127 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 128 "SampleAfterValue": "100003", 129 "UMask": "0x60" 130 }, 131 { 132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 133 "Counter": "0,1,2,3", 134 "CounterHTOff": "0,1,2,3,4,5,6,7", 135 "EventCode": "0x49", 136 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 137 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 138 "SampleAfterValue": "100003", 139 "UMask": "0x40" 140 }, 141 { 142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 143 "Counter": "0,1,2,3", 144 "CounterHTOff": "0,1,2,3,4,5,6,7", 145 "EventCode": "0x49", 146 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 147 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 148 "SampleAfterValue": "100003", 149 "UMask": "0x20" 150 }, 151 { 152 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 153 "Counter": "0,1,2,3", 154 "CounterHTOff": "0,1,2,3,4,5,6,7", 155 "EventCode": "0x49", 156 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 157 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 158 "SampleAfterValue": "100003", 159 "UMask": "0xe" 160 }, 161 { 162 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 163 "Counter": "0,1,2,3", 164 "CounterHTOff": "0,1,2,3,4,5,6,7", 165 "EventCode": "0x49", 166 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 167 "SampleAfterValue": "100003", 168 "UMask": "0x8" 169 }, 170 { 171 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 172 "Counter": "0,1,2,3", 173 "CounterHTOff": "0,1,2,3,4,5,6,7", 174 "EventCode": "0x49", 175 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 176 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 177 "SampleAfterValue": "100003", 178 "UMask": "0x4" 179 }, 180 { 181 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 182 "Counter": "0,1,2,3", 183 "CounterHTOff": "0,1,2,3,4,5,6,7", 184 "EventCode": "0x49", 185 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 186 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 187 "SampleAfterValue": "100003", 188 "UMask": "0x2" 189 }, 190 { 191 "BriefDescription": "Cycles when PMH is busy with page walks", 192 "Counter": "0,1,2,3", 193 "CounterHTOff": "0,1,2,3,4,5,6,7", 194 "EventCode": "0x49", 195 "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 196 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 197 "SampleAfterValue": "100003", 198 "UMask": "0x10" 199 }, 200 { 201 "BriefDescription": "Cycle count for an Extended Page table walk.", 202 "Counter": "0,1,2,3", 203 "CounterHTOff": "0,1,2,3,4,5,6,7", 204 "EventCode": "0x4f", 205 "EventName": "EPT.WALK_CYCLES", 206 "SampleAfterValue": "2000003", 207 "UMask": "0x10" 208 }, 209 { 210 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 211 "Counter": "0,1,2,3", 212 "CounterHTOff": "0,1,2,3,4,5,6,7", 213 "EventCode": "0xae", 214 "EventName": "ITLB.ITLB_FLUSH", 215 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 216 "SampleAfterValue": "100003", 217 "UMask": "0x1" 218 }, 219 { 220 "BriefDescription": "Misses at all ITLB levels that cause page walks", 221 "Counter": "0,1,2,3", 222 "CounterHTOff": "0,1,2,3,4,5,6,7", 223 "EventCode": "0x85", 224 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 225 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 226 "SampleAfterValue": "100003", 227 "UMask": "0x1" 228 }, 229 { 230 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 231 "Counter": "0,1,2,3", 232 "CounterHTOff": "0,1,2,3,4,5,6,7", 233 "EventCode": "0x85", 234 "EventName": "ITLB_MISSES.STLB_HIT", 235 "PublicDescription": "ITLB misses that hit STLB. No page walk.", 236 "SampleAfterValue": "100003", 237 "UMask": "0x60" 238 }, 239 { 240 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 241 "Counter": "0,1,2,3", 242 "CounterHTOff": "0,1,2,3,4,5,6,7", 243 "EventCode": "0x85", 244 "EventName": "ITLB_MISSES.STLB_HIT_2M", 245 "PublicDescription": "ITLB misses that hit STLB (2M).", 246 "SampleAfterValue": "100003", 247 "UMask": "0x40" 248 }, 249 { 250 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 251 "Counter": "0,1,2,3", 252 "CounterHTOff": "0,1,2,3,4,5,6,7", 253 "EventCode": "0x85", 254 "EventName": "ITLB_MISSES.STLB_HIT_4K", 255 "PublicDescription": "ITLB misses that hit STLB (4K).", 256 "SampleAfterValue": "100003", 257 "UMask": "0x20" 258 }, 259 { 260 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 261 "Counter": "0,1,2,3", 262 "CounterHTOff": "0,1,2,3,4,5,6,7", 263 "EventCode": "0x85", 264 "EventName": "ITLB_MISSES.WALK_COMPLETED", 265 "PublicDescription": "Completed page walks in ITLB of any page size.", 266 "SampleAfterValue": "100003", 267 "UMask": "0xe" 268 }, 269 { 270 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 271 "Counter": "0,1,2,3", 272 "CounterHTOff": "0,1,2,3,4,5,6,7", 273 "EventCode": "0x85", 274 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 275 "SampleAfterValue": "100003", 276 "UMask": "0x8" 277 }, 278 { 279 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 280 "Counter": "0,1,2,3", 281 "CounterHTOff": "0,1,2,3,4,5,6,7", 282 "EventCode": "0x85", 283 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 284 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 285 "SampleAfterValue": "100003", 286 "UMask": "0x4" 287 }, 288 { 289 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 290 "Counter": "0,1,2,3", 291 "CounterHTOff": "0,1,2,3,4,5,6,7", 292 "EventCode": "0x85", 293 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 294 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 295 "SampleAfterValue": "100003", 296 "UMask": "0x2" 297 }, 298 { 299 "BriefDescription": "Cycles when PMH is busy with page walks", 300 "Counter": "0,1,2,3", 301 "CounterHTOff": "0,1,2,3,4,5,6,7", 302 "EventCode": "0x85", 303 "EventName": "ITLB_MISSES.WALK_DURATION", 304 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 305 "SampleAfterValue": "100003", 306 "UMask": "0x10" 307 }, 308 { 309 "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 310 "Counter": "0,1,2,3", 311 "CounterHTOff": "0,1,2,3", 312 "EventCode": "0xBC", 313 "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 314 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 315 "SampleAfterValue": "2000003", 316 "UMask": "0x11" 317 }, 318 { 319 "BriefDescription": "Number of DTLB page walker hits in the L2", 320 "Counter": "0,1,2,3", 321 "CounterHTOff": "0,1,2,3", 322 "EventCode": "0xBC", 323 "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 324 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 325 "SampleAfterValue": "2000003", 326 "UMask": "0x12" 327 }, 328 { 329 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 330 "Counter": "0,1,2,3", 331 "CounterHTOff": "0,1,2,3", 332 "Errata": "HSD25", 333 "EventCode": "0xBC", 334 "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 335 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 336 "SampleAfterValue": "2000003", 337 "UMask": "0x14" 338 }, 339 { 340 "BriefDescription": "Number of DTLB page walker hits in Memory", 341 "Counter": "0,1,2,3", 342 "CounterHTOff": "0,1,2,3", 343 "Errata": "HSD25", 344 "EventCode": "0xBC", 345 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 346 "PublicDescription": "Number of DTLB page walker loads from memory.", 347 "SampleAfterValue": "2000003", 348 "UMask": "0x18" 349 }, 350 { 351 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 352 "Counter": "0,1,2,3", 353 "CounterHTOff": "0,1,2,3", 354 "EventCode": "0xBC", 355 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 356 "SampleAfterValue": "2000003", 357 "UMask": "0x41" 358 }, 359 { 360 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 361 "Counter": "0,1,2,3", 362 "CounterHTOff": "0,1,2,3", 363 "EventCode": "0xBC", 364 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 365 "SampleAfterValue": "2000003", 366 "UMask": "0x42" 367 }, 368 { 369 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 370 "Counter": "0,1,2,3", 371 "CounterHTOff": "0,1,2,3", 372 "EventCode": "0xBC", 373 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 374 "SampleAfterValue": "2000003", 375 "UMask": "0x44" 376 }, 377 { 378 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 379 "Counter": "0,1,2,3", 380 "CounterHTOff": "0,1,2,3", 381 "EventCode": "0xBC", 382 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 383 "SampleAfterValue": "2000003", 384 "UMask": "0x48" 385 }, 386 { 387 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 388 "Counter": "0,1,2,3", 389 "CounterHTOff": "0,1,2,3", 390 "EventCode": "0xBC", 391 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 392 "SampleAfterValue": "2000003", 393 "UMask": "0x81" 394 }, 395 { 396 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 397 "Counter": "0,1,2,3", 398 "CounterHTOff": "0,1,2,3", 399 "EventCode": "0xBC", 400 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 401 "SampleAfterValue": "2000003", 402 "UMask": "0x82" 403 }, 404 { 405 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 406 "Counter": "0,1,2,3", 407 "CounterHTOff": "0,1,2,3", 408 "EventCode": "0xBC", 409 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 410 "SampleAfterValue": "2000003", 411 "UMask": "0x84" 412 }, 413 { 414 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 415 "Counter": "0,1,2,3", 416 "CounterHTOff": "0,1,2,3", 417 "EventCode": "0xBC", 418 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 419 "SampleAfterValue": "2000003", 420 "UMask": "0x88" 421 }, 422 { 423 "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 424 "Counter": "0,1,2,3", 425 "CounterHTOff": "0,1,2,3", 426 "EventCode": "0xBC", 427 "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 428 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 429 "SampleAfterValue": "2000003", 430 "UMask": "0x21" 431 }, 432 { 433 "BriefDescription": "Number of ITLB page walker hits in the L2", 434 "Counter": "0,1,2,3", 435 "CounterHTOff": "0,1,2,3", 436 "EventCode": "0xBC", 437 "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 438 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 439 "SampleAfterValue": "2000003", 440 "UMask": "0x22" 441 }, 442 { 443 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 444 "Counter": "0,1,2,3", 445 "CounterHTOff": "0,1,2,3", 446 "Errata": "HSD25", 447 "EventCode": "0xBC", 448 "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 449 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 450 "SampleAfterValue": "2000003", 451 "UMask": "0x24" 452 }, 453 { 454 "BriefDescription": "Number of ITLB page walker hits in Memory", 455 "Counter": "0,1,2,3", 456 "CounterHTOff": "0,1,2,3", 457 "Errata": "HSD25", 458 "EventCode": "0xBC", 459 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 460 "PublicDescription": "Number of ITLB page walker loads from memory.", 461 "SampleAfterValue": "2000003", 462 "UMask": "0x28" 463 }, 464 { 465 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 466 "Counter": "0,1,2,3", 467 "CounterHTOff": "0,1,2,3,4,5,6,7", 468 "EventCode": "0xBD", 469 "EventName": "TLB_FLUSH.DTLB_THREAD", 470 "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 471 "SampleAfterValue": "100003", 472 "UMask": "0x1" 473 }, 474 { 475 "BriefDescription": "STLB flush attempts", 476 "Counter": "0,1,2,3", 477 "CounterHTOff": "0,1,2,3,4,5,6,7", 478 "EventCode": "0xBD", 479 "EventName": "TLB_FLUSH.STLB_ANY", 480 "PublicDescription": "Count number of STLB flush attempts.", 481 "SampleAfterValue": "100003", 482 "UMask": "0x20" 483 } 484]