1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4  *
5  * Multi-channel Audio Serial Port Driver
6  *
7  * Author: Nirmal Pandey <n-pandey@ti.com>,
8  *         Suresh Rajashekara <suresh.r@ti.com>
9  *         Steve Chen <schen@.mvista.com>
10  *
11  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12  * Copyright:   (C) 2009  Texas Instruments, India
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
30 
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
38 
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
43 
44 #define MCASP_MAX_AFIFO_DEPTH	64
45 
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 	DAVINCI_MCASP_TXFMCTL_REG,
49 	DAVINCI_MCASP_RXFMCTL_REG,
50 	DAVINCI_MCASP_TXFMT_REG,
51 	DAVINCI_MCASP_RXFMT_REG,
52 	DAVINCI_MCASP_ACLKXCTL_REG,
53 	DAVINCI_MCASP_ACLKRCTL_REG,
54 	DAVINCI_MCASP_AHCLKXCTL_REG,
55 	DAVINCI_MCASP_AHCLKRCTL_REG,
56 	DAVINCI_MCASP_PDIR_REG,
57 	DAVINCI_MCASP_PFUNC_REG,
58 	DAVINCI_MCASP_RXMASK_REG,
59 	DAVINCI_MCASP_TXMASK_REG,
60 	DAVINCI_MCASP_RXTDM_REG,
61 	DAVINCI_MCASP_TXTDM_REG,
62 };
63 
64 struct davinci_mcasp_context {
65 	u32	config_regs[ARRAY_SIZE(context_regs)];
66 	u32	afifo_regs[2]; /* for read/write fifo control registers */
67 	u32	*xrsr_regs; /* for serializer configuration */
68 	bool	pm_state;
69 };
70 #endif
71 
72 struct davinci_mcasp_ruledata {
73 	struct davinci_mcasp *mcasp;
74 	int serializers;
75 };
76 
77 struct davinci_mcasp {
78 	struct snd_dmaengine_dai_dma_data dma_data[2];
79 	struct davinci_mcasp_pdata *pdata;
80 	void __iomem *base;
81 	u32 fifo_base;
82 	struct device *dev;
83 	struct snd_pcm_substream *substreams[2];
84 	unsigned int dai_fmt;
85 
86 	u32 iec958_status;
87 
88 	/* Audio can not be enabled due to missing parameter(s) */
89 	bool	missing_audio_param;
90 
91 	/* McASP specific data */
92 	int	tdm_slots;
93 	u32	tdm_mask[2];
94 	int	slot_width;
95 	u8	op_mode;
96 	u8	dismod;
97 	u8	num_serializer;
98 	u8	*serial_dir;
99 	u8	version;
100 	u8	bclk_div;
101 	int	streams;
102 	u32	irq_request[2];
103 
104 	int	sysclk_freq;
105 	bool	bclk_master;
106 	u32	auxclk_fs_ratio;
107 
108 	unsigned long pdir; /* Pin direction bitfield */
109 
110 	/* McASP FIFO related */
111 	u8	txnumevt;
112 	u8	rxnumevt;
113 
114 	bool	dat_port;
115 
116 	/* Used for comstraint setting on the second stream */
117 	u32	channels;
118 	int	max_format_width;
119 	u8	active_serializers[2];
120 
121 #ifdef CONFIG_GPIOLIB
122 	struct gpio_chip gpio_chip;
123 #endif
124 
125 #ifdef CONFIG_PM
126 	struct davinci_mcasp_context context;
127 #endif
128 
129 	struct davinci_mcasp_ruledata ruledata[2];
130 	struct snd_pcm_hw_constraint_list chconstr[2];
131 };
132 
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)133 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
134 				  u32 val)
135 {
136 	void __iomem *reg = mcasp->base + offset;
137 	__raw_writel(__raw_readl(reg) | val, reg);
138 }
139 
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)140 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
141 				  u32 val)
142 {
143 	void __iomem *reg = mcasp->base + offset;
144 	__raw_writel((__raw_readl(reg) & ~(val)), reg);
145 }
146 
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)147 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
148 				  u32 val, u32 mask)
149 {
150 	void __iomem *reg = mcasp->base + offset;
151 	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
152 }
153 
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)154 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
155 				 u32 val)
156 {
157 	__raw_writel(val, mcasp->base + offset);
158 }
159 
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)160 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
161 {
162 	return (u32)__raw_readl(mcasp->base + offset);
163 }
164 
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)165 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
166 {
167 	int i = 0;
168 
169 	mcasp_set_bits(mcasp, ctl_reg, val);
170 
171 	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
172 	/* loop count is to avoid the lock-up */
173 	for (i = 0; i < 1000; i++) {
174 		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
175 			break;
176 	}
177 
178 	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
179 		printk(KERN_ERR "GBLCTL write error\n");
180 }
181 
mcasp_is_synchronous(struct davinci_mcasp * mcasp)182 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
183 {
184 	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
185 	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
186 
187 	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
188 }
189 
mcasp_set_clk_pdir(struct davinci_mcasp * mcasp,bool enable)190 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
191 {
192 	u32 bit = PIN_BIT_AMUTE;
193 
194 	for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
195 		if (enable)
196 			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
197 		else
198 			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
199 	}
200 }
201 
mcasp_set_axr_pdir(struct davinci_mcasp * mcasp,bool enable)202 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
203 {
204 	u32 bit;
205 
206 	for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
207 		if (enable)
208 			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
209 		else
210 			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
211 	}
212 }
213 
mcasp_start_rx(struct davinci_mcasp * mcasp)214 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
215 {
216 	if (mcasp->rxnumevt) {	/* enable FIFO */
217 		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
218 
219 		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
220 		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
221 	}
222 
223 	/* Start clocks */
224 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
225 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
226 	/*
227 	 * When ASYNC == 0 the transmit and receive sections operate
228 	 * synchronously from the transmit clock and frame sync. We need to make
229 	 * sure that the TX signlas are enabled when starting reception.
230 	 */
231 	if (mcasp_is_synchronous(mcasp)) {
232 		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
233 		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
234 		mcasp_set_clk_pdir(mcasp, true);
235 	}
236 
237 	/* Activate serializer(s) */
238 	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
239 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
240 	/* Release RX state machine */
241 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
242 	/* Release Frame Sync generator */
243 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
244 	if (mcasp_is_synchronous(mcasp))
245 		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
246 
247 	/* enable receive IRQs */
248 	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
249 		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
250 }
251 
mcasp_start_tx(struct davinci_mcasp * mcasp)252 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
253 {
254 	u32 cnt;
255 
256 	if (mcasp->txnumevt) {	/* enable FIFO */
257 		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
258 
259 		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
260 		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
261 	}
262 
263 	/* Start clocks */
264 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
265 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
266 	mcasp_set_clk_pdir(mcasp, true);
267 
268 	/* Activate serializer(s) */
269 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
270 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
271 
272 	/* wait for XDATA to be cleared */
273 	cnt = 0;
274 	while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
275 	       (cnt < 100000))
276 		cnt++;
277 
278 	mcasp_set_axr_pdir(mcasp, true);
279 
280 	/* Release TX state machine */
281 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
282 	/* Release Frame Sync generator */
283 	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
284 
285 	/* enable transmit IRQs */
286 	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
287 		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
288 }
289 
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)290 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
291 {
292 	mcasp->streams++;
293 
294 	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
295 		mcasp_start_tx(mcasp);
296 	else
297 		mcasp_start_rx(mcasp);
298 }
299 
mcasp_stop_rx(struct davinci_mcasp * mcasp)300 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
301 {
302 	/* disable IRQ sources */
303 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
304 		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
305 
306 	/*
307 	 * In synchronous mode stop the TX clocks if no other stream is
308 	 * running
309 	 */
310 	if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
311 		mcasp_set_clk_pdir(mcasp, false);
312 		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
313 	}
314 
315 	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
316 	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
317 
318 	if (mcasp->rxnumevt) {	/* disable FIFO */
319 		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
320 
321 		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
322 	}
323 }
324 
mcasp_stop_tx(struct davinci_mcasp * mcasp)325 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
326 {
327 	u32 val = 0;
328 
329 	/* disable IRQ sources */
330 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
331 		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
332 
333 	/*
334 	 * In synchronous mode keep TX clocks running if the capture stream is
335 	 * still running.
336 	 */
337 	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
338 		val =  TXHCLKRST | TXCLKRST | TXFSRST;
339 	else
340 		mcasp_set_clk_pdir(mcasp, false);
341 
342 
343 	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
344 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
345 
346 	if (mcasp->txnumevt) {	/* disable FIFO */
347 		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
348 
349 		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
350 	}
351 
352 	mcasp_set_axr_pdir(mcasp, false);
353 }
354 
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)355 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
356 {
357 	mcasp->streams--;
358 
359 	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
360 		mcasp_stop_tx(mcasp);
361 	else
362 		mcasp_stop_rx(mcasp);
363 }
364 
davinci_mcasp_tx_irq_handler(int irq,void * data)365 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
366 {
367 	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
368 	struct snd_pcm_substream *substream;
369 	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
370 	u32 handled_mask = 0;
371 	u32 stat;
372 
373 	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
374 	if (stat & XUNDRN & irq_mask) {
375 		dev_warn(mcasp->dev, "Transmit buffer underflow\n");
376 		handled_mask |= XUNDRN;
377 
378 		substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
379 		if (substream)
380 			snd_pcm_stop_xrun(substream);
381 	}
382 
383 	if (!handled_mask)
384 		dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
385 			 stat);
386 
387 	if (stat & XRERR)
388 		handled_mask |= XRERR;
389 
390 	/* Ack the handled event only */
391 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
392 
393 	return IRQ_RETVAL(handled_mask);
394 }
395 
davinci_mcasp_rx_irq_handler(int irq,void * data)396 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
397 {
398 	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
399 	struct snd_pcm_substream *substream;
400 	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
401 	u32 handled_mask = 0;
402 	u32 stat;
403 
404 	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
405 	if (stat & ROVRN & irq_mask) {
406 		dev_warn(mcasp->dev, "Receive buffer overflow\n");
407 		handled_mask |= ROVRN;
408 
409 		substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
410 		if (substream)
411 			snd_pcm_stop_xrun(substream);
412 	}
413 
414 	if (!handled_mask)
415 		dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
416 			 stat);
417 
418 	if (stat & XRERR)
419 		handled_mask |= XRERR;
420 
421 	/* Ack the handled event only */
422 	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
423 
424 	return IRQ_RETVAL(handled_mask);
425 }
426 
davinci_mcasp_common_irq_handler(int irq,void * data)427 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
428 {
429 	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
430 	irqreturn_t ret = IRQ_NONE;
431 
432 	if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
433 		ret = davinci_mcasp_tx_irq_handler(irq, data);
434 
435 	if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
436 		ret |= davinci_mcasp_rx_irq_handler(irq, data);
437 
438 	return ret;
439 }
440 
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)441 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
442 					 unsigned int fmt)
443 {
444 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
445 	int ret = 0;
446 	u32 data_delay;
447 	bool fs_pol_rising;
448 	bool inv_fs = false;
449 
450 	if (!fmt)
451 		return 0;
452 
453 	pm_runtime_get_sync(mcasp->dev);
454 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
455 	case SND_SOC_DAIFMT_DSP_A:
456 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
457 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
458 		/* 1st data bit occur one ACLK cycle after the frame sync */
459 		data_delay = 1;
460 		break;
461 	case SND_SOC_DAIFMT_DSP_B:
462 	case SND_SOC_DAIFMT_AC97:
463 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
464 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
465 		/* No delay after FS */
466 		data_delay = 0;
467 		break;
468 	case SND_SOC_DAIFMT_I2S:
469 		/* configure a full-word SYNC pulse (LRCLK) */
470 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
471 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
472 		/* 1st data bit occur one ACLK cycle after the frame sync */
473 		data_delay = 1;
474 		/* FS need to be inverted */
475 		inv_fs = true;
476 		break;
477 	case SND_SOC_DAIFMT_RIGHT_J:
478 	case SND_SOC_DAIFMT_LEFT_J:
479 		/* configure a full-word SYNC pulse (LRCLK) */
480 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
481 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
482 		/* No delay after FS */
483 		data_delay = 0;
484 		break;
485 	default:
486 		ret = -EINVAL;
487 		goto out;
488 	}
489 
490 	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
491 		       FSXDLY(3));
492 	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
493 		       FSRDLY(3));
494 
495 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
496 	case SND_SOC_DAIFMT_CBS_CFS:
497 		/* codec is clock and frame slave */
498 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
499 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
500 
501 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
502 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
503 
504 		/* BCLK */
505 		set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
506 		set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
507 		/* Frame Sync */
508 		set_bit(PIN_BIT_AFSX, &mcasp->pdir);
509 		set_bit(PIN_BIT_AFSR, &mcasp->pdir);
510 
511 		mcasp->bclk_master = 1;
512 		break;
513 	case SND_SOC_DAIFMT_CBS_CFM:
514 		/* codec is clock slave and frame master */
515 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517 
518 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520 
521 		/* BCLK */
522 		set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
523 		set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
524 		/* Frame Sync */
525 		clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
526 		clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
527 
528 		mcasp->bclk_master = 1;
529 		break;
530 	case SND_SOC_DAIFMT_CBM_CFS:
531 		/* codec is clock master and frame slave */
532 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
533 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
534 
535 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
536 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
537 
538 		/* BCLK */
539 		clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
540 		clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
541 		/* Frame Sync */
542 		set_bit(PIN_BIT_AFSX, &mcasp->pdir);
543 		set_bit(PIN_BIT_AFSR, &mcasp->pdir);
544 
545 		mcasp->bclk_master = 0;
546 		break;
547 	case SND_SOC_DAIFMT_CBM_CFM:
548 		/* codec is clock and frame master */
549 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
550 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
551 
552 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
553 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
554 
555 		/* BCLK */
556 		clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
557 		clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
558 		/* Frame Sync */
559 		clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
560 		clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
561 
562 		mcasp->bclk_master = 0;
563 		break;
564 	default:
565 		ret = -EINVAL;
566 		goto out;
567 	}
568 
569 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
570 	case SND_SOC_DAIFMT_IB_NF:
571 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
572 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
573 		fs_pol_rising = true;
574 		break;
575 	case SND_SOC_DAIFMT_NB_IF:
576 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
577 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
578 		fs_pol_rising = false;
579 		break;
580 	case SND_SOC_DAIFMT_IB_IF:
581 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
582 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
583 		fs_pol_rising = false;
584 		break;
585 	case SND_SOC_DAIFMT_NB_NF:
586 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
587 		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
588 		fs_pol_rising = true;
589 		break;
590 	default:
591 		ret = -EINVAL;
592 		goto out;
593 	}
594 
595 	if (inv_fs)
596 		fs_pol_rising = !fs_pol_rising;
597 
598 	if (fs_pol_rising) {
599 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
600 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
601 	} else {
602 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
603 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
604 	}
605 
606 	mcasp->dai_fmt = fmt;
607 out:
608 	pm_runtime_put(mcasp->dev);
609 	return ret;
610 }
611 
__davinci_mcasp_set_clkdiv(struct davinci_mcasp * mcasp,int div_id,int div,bool explicit)612 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
613 				      int div, bool explicit)
614 {
615 	pm_runtime_get_sync(mcasp->dev);
616 	switch (div_id) {
617 	case MCASP_CLKDIV_AUXCLK:			/* MCLK divider */
618 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
619 			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
620 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
621 			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
622 		break;
623 
624 	case MCASP_CLKDIV_BCLK:			/* BCLK divider */
625 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
626 			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
627 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
628 			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
629 		if (explicit)
630 			mcasp->bclk_div = div;
631 		break;
632 
633 	case MCASP_CLKDIV_BCLK_FS_RATIO:
634 		/*
635 		 * BCLK/LRCLK ratio descries how many bit-clock cycles
636 		 * fit into one frame. The clock ratio is given for a
637 		 * full period of data (for I2S format both left and
638 		 * right channels), so it has to be divided by number
639 		 * of tdm-slots (for I2S - divided by 2).
640 		 * Instead of storing this ratio, we calculate a new
641 		 * tdm_slot width by dividing the ratio by the
642 		 * number of configured tdm slots.
643 		 */
644 		mcasp->slot_width = div / mcasp->tdm_slots;
645 		if (div % mcasp->tdm_slots)
646 			dev_warn(mcasp->dev,
647 				 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
648 				 __func__, div, mcasp->tdm_slots);
649 		break;
650 
651 	default:
652 		return -EINVAL;
653 	}
654 
655 	pm_runtime_put(mcasp->dev);
656 	return 0;
657 }
658 
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)659 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
660 				    int div)
661 {
662 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
663 
664 	return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
665 }
666 
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)667 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
668 				    unsigned int freq, int dir)
669 {
670 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
671 
672 	pm_runtime_get_sync(mcasp->dev);
673 
674 	if (dir == SND_SOC_CLOCK_IN) {
675 		switch (clk_id) {
676 		case MCASP_CLK_HCLK_AHCLK:
677 			mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
678 				       AHCLKXE);
679 			mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
680 				       AHCLKRE);
681 			clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
682 			break;
683 		case MCASP_CLK_HCLK_AUXCLK:
684 			mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
685 				       AHCLKXE);
686 			mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
687 				       AHCLKRE);
688 			set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
689 			break;
690 		default:
691 			dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
692 			goto out;
693 		}
694 	} else {
695 		/* Select AUXCLK as HCLK */
696 		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
697 		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
698 		set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
699 	}
700 	/*
701 	 * When AHCLK X/R is selected to be output it means that the HCLK is
702 	 * the same clock - coming via AUXCLK.
703 	 */
704 	mcasp->sysclk_freq = freq;
705 out:
706 	pm_runtime_put(mcasp->dev);
707 	return 0;
708 }
709 
710 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)711 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
712 				       int serializers)
713 {
714 	struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
715 	unsigned int *list = (unsigned int *) cl->list;
716 	int slots = mcasp->tdm_slots;
717 	int i, count = 0;
718 
719 	if (mcasp->tdm_mask[stream])
720 		slots = hweight32(mcasp->tdm_mask[stream]);
721 
722 	for (i = 1; i <= slots; i++)
723 		list[count++] = i;
724 
725 	for (i = 2; i <= serializers; i++)
726 		list[count++] = i*slots;
727 
728 	cl->count = count;
729 
730 	return 0;
731 }
732 
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)733 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
734 {
735 	int rx_serializers = 0, tx_serializers = 0, ret, i;
736 
737 	for (i = 0; i < mcasp->num_serializer; i++)
738 		if (mcasp->serial_dir[i] == TX_MODE)
739 			tx_serializers++;
740 		else if (mcasp->serial_dir[i] == RX_MODE)
741 			rx_serializers++;
742 
743 	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
744 					  tx_serializers);
745 	if (ret)
746 		return ret;
747 
748 	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
749 					  rx_serializers);
750 
751 	return ret;
752 }
753 
754 
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)755 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
756 				      unsigned int tx_mask,
757 				      unsigned int rx_mask,
758 				      int slots, int slot_width)
759 {
760 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
761 
762 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
763 		return 0;
764 
765 	dev_dbg(mcasp->dev,
766 		 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
767 		 __func__, tx_mask, rx_mask, slots, slot_width);
768 
769 	if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
770 		dev_err(mcasp->dev,
771 			"Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
772 			tx_mask, rx_mask, slots);
773 		return -EINVAL;
774 	}
775 
776 	if (slot_width &&
777 	    (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
778 		dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
779 			__func__, slot_width);
780 		return -EINVAL;
781 	}
782 
783 	mcasp->tdm_slots = slots;
784 	mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
785 	mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
786 	mcasp->slot_width = slot_width;
787 
788 	return davinci_mcasp_set_ch_constraints(mcasp);
789 }
790 
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)791 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
792 				       int sample_width)
793 {
794 	u32 fmt;
795 	u32 tx_rotate, rx_rotate, slot_width;
796 	u32 mask = (1ULL << sample_width) - 1;
797 
798 	if (mcasp->slot_width)
799 		slot_width = mcasp->slot_width;
800 	else if (mcasp->max_format_width)
801 		slot_width = mcasp->max_format_width;
802 	else
803 		slot_width = sample_width;
804 	/*
805 	 * TX rotation:
806 	 * right aligned formats: rotate w/ slot_width
807 	 * left aligned formats: rotate w/ sample_width
808 	 *
809 	 * RX rotation:
810 	 * right aligned formats: no rotation needed
811 	 * left aligned formats: rotate w/ (slot_width - sample_width)
812 	 */
813 	if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
814 	    SND_SOC_DAIFMT_RIGHT_J) {
815 		tx_rotate = (slot_width / 4) & 0x7;
816 		rx_rotate = 0;
817 	} else {
818 		tx_rotate = (sample_width / 4) & 0x7;
819 		rx_rotate = (slot_width - sample_width) / 4;
820 	}
821 
822 	/* mapping of the XSSZ bit-field as described in the datasheet */
823 	fmt = (slot_width >> 1) - 1;
824 
825 	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
826 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
827 			       RXSSZ(0x0F));
828 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
829 			       TXSSZ(0x0F));
830 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
831 			       TXROT(7));
832 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
833 			       RXROT(7));
834 		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
835 	} else {
836 		/*
837 		 * according to the TRM it should be TXROT=0, this one works:
838 		 * 16 bit to 23-8 (TXROT=6, rotate 24 bits)
839 		 * 24 bit to 23-0 (TXROT=0, rotate 0 bits)
840 		 *
841 		 * TXROT = 0 only works with 24bit samples
842 		 */
843 		tx_rotate = (sample_width / 4 + 2) & 0x7;
844 
845 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
846 			       TXROT(7));
847 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
848 			       TXSSZ(0x0F));
849 	}
850 
851 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
852 
853 	return 0;
854 }
855 
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)856 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
857 				 int period_words, int channels)
858 {
859 	struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
860 	int i;
861 	u8 tx_ser = 0;
862 	u8 rx_ser = 0;
863 	u8 slots = mcasp->tdm_slots;
864 	u8 max_active_serializers, max_rx_serializers, max_tx_serializers;
865 	int active_serializers, numevt;
866 	u32 reg;
867 
868 	/* In DIT mode we only allow maximum of one serializers for now */
869 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
870 		max_active_serializers = 1;
871 	else
872 		max_active_serializers = (channels + slots - 1) / slots;
873 
874 	/* Default configuration */
875 	if (mcasp->version < MCASP_VERSION_3)
876 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
877 
878 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
879 		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
880 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
881 		max_tx_serializers = max_active_serializers;
882 		max_rx_serializers =
883 			mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
884 	} else {
885 		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
886 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
887 		max_tx_serializers =
888 			mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
889 		max_rx_serializers = max_active_serializers;
890 	}
891 
892 	for (i = 0; i < mcasp->num_serializer; i++) {
893 		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
894 			       mcasp->serial_dir[i]);
895 		if (mcasp->serial_dir[i] == TX_MODE &&
896 					tx_ser < max_tx_serializers) {
897 			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
898 				       mcasp->dismod, DISMOD_MASK);
899 			set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
900 			tx_ser++;
901 		} else if (mcasp->serial_dir[i] == RX_MODE &&
902 					rx_ser < max_rx_serializers) {
903 			clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
904 			rx_ser++;
905 		} else {
906 			/* Inactive or unused pin, set it to inactive */
907 			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
908 				       SRMOD_INACTIVE, SRMOD_MASK);
909 			/* If unused, set DISMOD for the pin */
910 			if (mcasp->serial_dir[i] != INACTIVE_MODE)
911 				mcasp_mod_bits(mcasp,
912 					       DAVINCI_MCASP_XRSRCTL_REG(i),
913 					       mcasp->dismod, DISMOD_MASK);
914 			clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
915 		}
916 	}
917 
918 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
919 		active_serializers = tx_ser;
920 		numevt = mcasp->txnumevt;
921 		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
922 	} else {
923 		active_serializers = rx_ser;
924 		numevt = mcasp->rxnumevt;
925 		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
926 	}
927 
928 	if (active_serializers < max_active_serializers) {
929 		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
930 			 "enabled in mcasp (%d)\n", channels,
931 			 active_serializers * slots);
932 		return -EINVAL;
933 	}
934 
935 	/* AFIFO is not in use */
936 	if (!numevt) {
937 		/* Configure the burst size for platform drivers */
938 		if (active_serializers > 1) {
939 			/*
940 			 * If more than one serializers are in use we have one
941 			 * DMA request to provide data for all serializers.
942 			 * For example if three serializers are enabled the DMA
943 			 * need to transfer three words per DMA request.
944 			 */
945 			dma_data->maxburst = active_serializers;
946 		} else {
947 			dma_data->maxburst = 0;
948 		}
949 
950 		goto out;
951 	}
952 
953 	if (period_words % active_serializers) {
954 		dev_err(mcasp->dev, "Invalid combination of period words and "
955 			"active serializers: %d, %d\n", period_words,
956 			active_serializers);
957 		return -EINVAL;
958 	}
959 
960 	/*
961 	 * Calculate the optimal AFIFO depth for platform side:
962 	 * The number of words for numevt need to be in steps of active
963 	 * serializers.
964 	 */
965 	numevt = (numevt / active_serializers) * active_serializers;
966 
967 	while (period_words % numevt && numevt > 0)
968 		numevt -= active_serializers;
969 	if (numevt <= 0)
970 		numevt = active_serializers;
971 
972 	mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
973 	mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
974 
975 	/* Configure the burst size for platform drivers */
976 	if (numevt == 1)
977 		numevt = 0;
978 	dma_data->maxburst = numevt;
979 
980 out:
981 	mcasp->active_serializers[stream] = active_serializers;
982 
983 	return 0;
984 }
985 
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)986 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
987 			      int channels)
988 {
989 	int i, active_slots;
990 	int total_slots;
991 	int active_serializers;
992 	u32 mask = 0;
993 	u32 busel = 0;
994 
995 	total_slots = mcasp->tdm_slots;
996 
997 	/*
998 	 * If more than one serializer is needed, then use them with
999 	 * all the specified tdm_slots. Otherwise, one serializer can
1000 	 * cope with the transaction using just as many slots as there
1001 	 * are channels in the stream.
1002 	 */
1003 	if (mcasp->tdm_mask[stream]) {
1004 		active_slots = hweight32(mcasp->tdm_mask[stream]);
1005 		active_serializers = (channels + active_slots - 1) /
1006 			active_slots;
1007 		if (active_serializers == 1)
1008 			active_slots = channels;
1009 		for (i = 0; i < total_slots; i++) {
1010 			if ((1 << i) & mcasp->tdm_mask[stream]) {
1011 				mask |= (1 << i);
1012 				if (--active_slots <= 0)
1013 					break;
1014 			}
1015 		}
1016 	} else {
1017 		active_serializers = (channels + total_slots - 1) / total_slots;
1018 		if (active_serializers == 1)
1019 			active_slots = channels;
1020 		else
1021 			active_slots = total_slots;
1022 
1023 		for (i = 0; i < active_slots; i++)
1024 			mask |= (1 << i);
1025 	}
1026 
1027 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1028 
1029 	if (!mcasp->dat_port)
1030 		busel = TXSEL;
1031 
1032 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1033 		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1034 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1035 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1036 			       FSXMOD(total_slots), FSXMOD(0x1FF));
1037 	} else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1038 		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1039 		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1040 		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1041 			       FSRMOD(total_slots), FSRMOD(0x1FF));
1042 		/*
1043 		 * If McASP is set to be TX/RX synchronous and the playback is
1044 		 * not running already we need to configure the TX slots in
1045 		 * order to have correct FSX on the bus
1046 		 */
1047 		if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1048 			mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1049 				       FSXMOD(total_slots), FSXMOD(0x1FF));
1050 	}
1051 
1052 	return 0;
1053 }
1054 
1055 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)1056 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1057 			      unsigned int rate)
1058 {
1059 	u8 *cs_bytes = (u8 *)&mcasp->iec958_status;
1060 
1061 	if (!mcasp->dat_port)
1062 		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1063 	else
1064 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1065 
1066 	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1067 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1068 
1069 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);
1070 
1071 	/* Set the TX tdm : for all the slots */
1072 	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1073 
1074 	/* Set the TX clock controls : div = 1 and internal */
1075 	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1076 
1077 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1078 
1079 	/* Set S/PDIF channel status bits */
1080 	cs_bytes[3] &= ~IEC958_AES3_CON_FS;
1081 	switch (rate) {
1082 	case 22050:
1083 		cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1084 		break;
1085 	case 24000:
1086 		cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1087 		break;
1088 	case 32000:
1089 		cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1090 		break;
1091 	case 44100:
1092 		cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1093 		break;
1094 	case 48000:
1095 		cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1096 		break;
1097 	case 88200:
1098 		cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1099 		break;
1100 	case 96000:
1101 		cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1102 		break;
1103 	case 176400:
1104 		cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1105 		break;
1106 	case 192000:
1107 		cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1108 		break;
1109 	default:
1110 		dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);
1111 		return -EINVAL;
1112 	}
1113 
1114 	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);
1115 	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);
1116 
1117 	/* Enable the DIT */
1118 	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1119 
1120 	return 0;
1121 }
1122 
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int sysclk_freq,unsigned int bclk_freq,bool set)1123 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1124 				      unsigned int sysclk_freq,
1125 				      unsigned int bclk_freq, bool set)
1126 {
1127 	u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1128 	int div = sysclk_freq / bclk_freq;
1129 	int rem = sysclk_freq % bclk_freq;
1130 	int error_ppm;
1131 	int aux_div = 1;
1132 
1133 	if (div > (ACLKXDIV_MASK + 1)) {
1134 		if (reg & AHCLKXE) {
1135 			aux_div = div / (ACLKXDIV_MASK + 1);
1136 			if (div % (ACLKXDIV_MASK + 1))
1137 				aux_div++;
1138 
1139 			sysclk_freq /= aux_div;
1140 			div = sysclk_freq / bclk_freq;
1141 			rem = sysclk_freq % bclk_freq;
1142 		} else if (set) {
1143 			dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1144 				 sysclk_freq);
1145 		}
1146 	}
1147 
1148 	if (rem != 0) {
1149 		if (div == 0 ||
1150 		    ((sysclk_freq / div) - bclk_freq) >
1151 		    (bclk_freq - (sysclk_freq / (div+1)))) {
1152 			div++;
1153 			rem = rem - bclk_freq;
1154 		}
1155 	}
1156 	error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1157 		     (int)bclk_freq)) / div - 1000000;
1158 
1159 	if (set) {
1160 		if (error_ppm)
1161 			dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1162 				 error_ppm);
1163 
1164 		__davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1165 		if (reg & AHCLKXE)
1166 			__davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1167 						   aux_div, 0);
1168 	}
1169 
1170 	return error_ppm;
1171 }
1172 
davinci_mcasp_tx_delay(struct davinci_mcasp * mcasp)1173 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1174 {
1175 	if (!mcasp->txnumevt)
1176 		return 0;
1177 
1178 	return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1179 }
1180 
davinci_mcasp_rx_delay(struct davinci_mcasp * mcasp)1181 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1182 {
1183 	if (!mcasp->rxnumevt)
1184 		return 0;
1185 
1186 	return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1187 }
1188 
davinci_mcasp_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1189 static snd_pcm_sframes_t davinci_mcasp_delay(
1190 			struct snd_pcm_substream *substream,
1191 			struct snd_soc_dai *cpu_dai)
1192 {
1193 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1194 	u32 fifo_use;
1195 
1196 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1197 		fifo_use = davinci_mcasp_tx_delay(mcasp);
1198 	else
1199 		fifo_use = davinci_mcasp_rx_delay(mcasp);
1200 
1201 	/*
1202 	 * Divide the used locations with the channel count to get the
1203 	 * FIFO usage in samples (don't care about partial samples in the
1204 	 * buffer).
1205 	 */
1206 	return fifo_use / substream->runtime->channels;
1207 }
1208 
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1209 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1210 					struct snd_pcm_hw_params *params,
1211 					struct snd_soc_dai *cpu_dai)
1212 {
1213 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1214 	int word_length;
1215 	int channels = params_channels(params);
1216 	int period_size = params_period_size(params);
1217 	int ret;
1218 
1219 	switch (params_format(params)) {
1220 	case SNDRV_PCM_FORMAT_U8:
1221 	case SNDRV_PCM_FORMAT_S8:
1222 		word_length = 8;
1223 		break;
1224 
1225 	case SNDRV_PCM_FORMAT_U16_LE:
1226 	case SNDRV_PCM_FORMAT_S16_LE:
1227 		word_length = 16;
1228 		break;
1229 
1230 	case SNDRV_PCM_FORMAT_U24_3LE:
1231 	case SNDRV_PCM_FORMAT_S24_3LE:
1232 		word_length = 24;
1233 		break;
1234 
1235 	case SNDRV_PCM_FORMAT_U24_LE:
1236 	case SNDRV_PCM_FORMAT_S24_LE:
1237 		word_length = 24;
1238 		break;
1239 
1240 	case SNDRV_PCM_FORMAT_U32_LE:
1241 	case SNDRV_PCM_FORMAT_S32_LE:
1242 		word_length = 32;
1243 		break;
1244 
1245 	default:
1246 		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1247 		return -EINVAL;
1248 	}
1249 
1250 	ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1251 	if (ret)
1252 		return ret;
1253 
1254 	/*
1255 	 * If mcasp is BCLK master, and a BCLK divider was not provided by
1256 	 * the machine driver, we need to calculate the ratio.
1257 	 */
1258 	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1259 		int slots = mcasp->tdm_slots;
1260 		int rate = params_rate(params);
1261 		int sbits = params_width(params);
1262 		unsigned int bclk_target;
1263 
1264 		if (mcasp->slot_width)
1265 			sbits = mcasp->slot_width;
1266 
1267 		if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1268 			bclk_target = rate * sbits * slots;
1269 		else
1270 			bclk_target = rate * 128;
1271 
1272 		davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1273 					   bclk_target, true);
1274 	}
1275 
1276 	ret = mcasp_common_hw_param(mcasp, substream->stream,
1277 				    period_size * channels, channels);
1278 	if (ret)
1279 		return ret;
1280 
1281 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1282 		ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1283 	else
1284 		ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1285 					 channels);
1286 
1287 	if (ret)
1288 		return ret;
1289 
1290 	davinci_config_channel_size(mcasp, word_length);
1291 
1292 	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1293 		mcasp->channels = channels;
1294 		if (!mcasp->max_format_width)
1295 			mcasp->max_format_width = word_length;
1296 	}
1297 
1298 	return 0;
1299 }
1300 
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1301 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1302 				     int cmd, struct snd_soc_dai *cpu_dai)
1303 {
1304 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1305 	int ret = 0;
1306 
1307 	switch (cmd) {
1308 	case SNDRV_PCM_TRIGGER_RESUME:
1309 	case SNDRV_PCM_TRIGGER_START:
1310 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1311 		davinci_mcasp_start(mcasp, substream->stream);
1312 		break;
1313 	case SNDRV_PCM_TRIGGER_SUSPEND:
1314 	case SNDRV_PCM_TRIGGER_STOP:
1315 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1316 		davinci_mcasp_stop(mcasp, substream->stream);
1317 		break;
1318 
1319 	default:
1320 		ret = -EINVAL;
1321 	}
1322 
1323 	return ret;
1324 }
1325 
davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1326 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1327 					    struct snd_pcm_hw_rule *rule)
1328 {
1329 	struct davinci_mcasp_ruledata *rd = rule->private;
1330 	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1331 	struct snd_mask nfmt;
1332 	int i, slot_width;
1333 
1334 	snd_mask_none(&nfmt);
1335 	slot_width = rd->mcasp->slot_width;
1336 
1337 	for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1338 		if (snd_mask_test(fmt, i)) {
1339 			if (snd_pcm_format_width(i) <= slot_width) {
1340 				snd_mask_set(&nfmt, i);
1341 			}
1342 		}
1343 	}
1344 
1345 	return snd_mask_refine(fmt, &nfmt);
1346 }
1347 
davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1348 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1349 					      struct snd_pcm_hw_rule *rule)
1350 {
1351 	struct davinci_mcasp_ruledata *rd = rule->private;
1352 	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1353 	struct snd_mask nfmt;
1354 	int i, format_width;
1355 
1356 	snd_mask_none(&nfmt);
1357 	format_width = rd->mcasp->max_format_width;
1358 
1359 	for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1360 		if (snd_mask_test(fmt, i)) {
1361 			if (snd_pcm_format_width(i) == format_width) {
1362 				snd_mask_set(&nfmt, i);
1363 			}
1364 		}
1365 	}
1366 
1367 	return snd_mask_refine(fmt, &nfmt);
1368 }
1369 
1370 static const unsigned int davinci_mcasp_dai_rates[] = {
1371 	8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1372 	88200, 96000, 176400, 192000,
1373 };
1374 
1375 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1376 
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1377 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1378 				      struct snd_pcm_hw_rule *rule)
1379 {
1380 	struct davinci_mcasp_ruledata *rd = rule->private;
1381 	struct snd_interval *ri =
1382 		hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1383 	int sbits = params_width(params);
1384 	int slots = rd->mcasp->tdm_slots;
1385 	struct snd_interval range;
1386 	int i;
1387 
1388 	if (rd->mcasp->slot_width)
1389 		sbits = rd->mcasp->slot_width;
1390 
1391 	snd_interval_any(&range);
1392 	range.empty = 1;
1393 
1394 	for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1395 		if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1396 			uint bclk_freq = sbits * slots *
1397 					 davinci_mcasp_dai_rates[i];
1398 			unsigned int sysclk_freq;
1399 			int ppm;
1400 
1401 			if (rd->mcasp->auxclk_fs_ratio)
1402 				sysclk_freq =  davinci_mcasp_dai_rates[i] *
1403 					       rd->mcasp->auxclk_fs_ratio;
1404 			else
1405 				sysclk_freq = rd->mcasp->sysclk_freq;
1406 
1407 			ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1408 							 bclk_freq, false);
1409 			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1410 				if (range.empty) {
1411 					range.min = davinci_mcasp_dai_rates[i];
1412 					range.empty = 0;
1413 				}
1414 				range.max = davinci_mcasp_dai_rates[i];
1415 			}
1416 		}
1417 	}
1418 
1419 	dev_dbg(rd->mcasp->dev,
1420 		"Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1421 		ri->min, ri->max, range.min, range.max, sbits, slots);
1422 
1423 	return snd_interval_refine(hw_param_interval(params, rule->var),
1424 				   &range);
1425 }
1426 
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1427 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1428 					struct snd_pcm_hw_rule *rule)
1429 {
1430 	struct davinci_mcasp_ruledata *rd = rule->private;
1431 	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1432 	struct snd_mask nfmt;
1433 	int rate = params_rate(params);
1434 	int slots = rd->mcasp->tdm_slots;
1435 	int i, count = 0;
1436 
1437 	snd_mask_none(&nfmt);
1438 
1439 	for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1440 		if (snd_mask_test(fmt, i)) {
1441 			uint sbits = snd_pcm_format_width(i);
1442 			unsigned int sysclk_freq;
1443 			int ppm;
1444 
1445 			if (rd->mcasp->auxclk_fs_ratio)
1446 				sysclk_freq =  rate *
1447 					       rd->mcasp->auxclk_fs_ratio;
1448 			else
1449 				sysclk_freq = rd->mcasp->sysclk_freq;
1450 
1451 			if (rd->mcasp->slot_width)
1452 				sbits = rd->mcasp->slot_width;
1453 
1454 			ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1455 							 sbits * slots * rate,
1456 							 false);
1457 			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1458 				snd_mask_set(&nfmt, i);
1459 				count++;
1460 			}
1461 		}
1462 	}
1463 	dev_dbg(rd->mcasp->dev,
1464 		"%d possible sample format for %d Hz and %d tdm slots\n",
1465 		count, rate, slots);
1466 
1467 	return snd_mask_refine(fmt, &nfmt);
1468 }
1469 
davinci_mcasp_hw_rule_min_periodsize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1470 static int davinci_mcasp_hw_rule_min_periodsize(
1471 		struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1472 {
1473 	struct snd_interval *period_size = hw_param_interval(params,
1474 						SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1475 	struct snd_interval frames;
1476 
1477 	snd_interval_any(&frames);
1478 	frames.min = 64;
1479 	frames.integer = 1;
1480 
1481 	return snd_interval_refine(period_size, &frames);
1482 }
1483 
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1484 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1485 				 struct snd_soc_dai *cpu_dai)
1486 {
1487 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1488 	struct davinci_mcasp_ruledata *ruledata =
1489 					&mcasp->ruledata[substream->stream];
1490 	u32 max_channels = 0;
1491 	int i, dir, ret;
1492 	int tdm_slots = mcasp->tdm_slots;
1493 
1494 	/* Do not allow more then one stream per direction */
1495 	if (mcasp->substreams[substream->stream])
1496 		return -EBUSY;
1497 
1498 	mcasp->substreams[substream->stream] = substream;
1499 
1500 	if (mcasp->tdm_mask[substream->stream])
1501 		tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1502 
1503 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1504 		return 0;
1505 
1506 	/*
1507 	 * Limit the maximum allowed channels for the first stream:
1508 	 * number of serializers for the direction * tdm slots per serializer
1509 	 */
1510 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1511 		dir = TX_MODE;
1512 	else
1513 		dir = RX_MODE;
1514 
1515 	for (i = 0; i < mcasp->num_serializer; i++) {
1516 		if (mcasp->serial_dir[i] == dir)
1517 			max_channels++;
1518 	}
1519 	ruledata->serializers = max_channels;
1520 	ruledata->mcasp = mcasp;
1521 	max_channels *= tdm_slots;
1522 	/*
1523 	 * If the already active stream has less channels than the calculated
1524 	 * limit based on the seirializers * tdm_slots, and only one serializer
1525 	 * is in use we need to use that as a constraint for the second stream.
1526 	 * Otherwise (first stream or less allowed channels or more than one
1527 	 * serializer in use) we use the calculated constraint.
1528 	 */
1529 	if (mcasp->channels && mcasp->channels < max_channels &&
1530 	    ruledata->serializers == 1)
1531 		max_channels = mcasp->channels;
1532 	/*
1533 	 * But we can always allow channels upto the amount of
1534 	 * the available tdm_slots.
1535 	 */
1536 	if (max_channels < tdm_slots)
1537 		max_channels = tdm_slots;
1538 
1539 	snd_pcm_hw_constraint_minmax(substream->runtime,
1540 				     SNDRV_PCM_HW_PARAM_CHANNELS,
1541 				     0, max_channels);
1542 
1543 	snd_pcm_hw_constraint_list(substream->runtime,
1544 				   0, SNDRV_PCM_HW_PARAM_CHANNELS,
1545 				   &mcasp->chconstr[substream->stream]);
1546 
1547 	if (mcasp->max_format_width) {
1548 		/*
1549 		 * Only allow formats which require same amount of bits on the
1550 		 * bus as the currently running stream
1551 		 */
1552 		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1553 					  SNDRV_PCM_HW_PARAM_FORMAT,
1554 					  davinci_mcasp_hw_rule_format_width,
1555 					  ruledata,
1556 					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
1557 		if (ret)
1558 			return ret;
1559 	}
1560 	else if (mcasp->slot_width) {
1561 		/* Only allow formats require <= slot_width bits on the bus */
1562 		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1563 					  SNDRV_PCM_HW_PARAM_FORMAT,
1564 					  davinci_mcasp_hw_rule_slot_width,
1565 					  ruledata,
1566 					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
1567 		if (ret)
1568 			return ret;
1569 	}
1570 
1571 	/*
1572 	 * If we rely on implicit BCLK divider setting we should
1573 	 * set constraints based on what we can provide.
1574 	 */
1575 	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1576 		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1577 					  SNDRV_PCM_HW_PARAM_RATE,
1578 					  davinci_mcasp_hw_rule_rate,
1579 					  ruledata,
1580 					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
1581 		if (ret)
1582 			return ret;
1583 		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1584 					  SNDRV_PCM_HW_PARAM_FORMAT,
1585 					  davinci_mcasp_hw_rule_format,
1586 					  ruledata,
1587 					  SNDRV_PCM_HW_PARAM_RATE, -1);
1588 		if (ret)
1589 			return ret;
1590 	}
1591 
1592 	snd_pcm_hw_rule_add(substream->runtime, 0,
1593 			    SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1594 			    davinci_mcasp_hw_rule_min_periodsize, NULL,
1595 			    SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1596 
1597 	return 0;
1598 }
1599 
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1600 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1601 				   struct snd_soc_dai *cpu_dai)
1602 {
1603 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1604 
1605 	mcasp->substreams[substream->stream] = NULL;
1606 	mcasp->active_serializers[substream->stream] = 0;
1607 
1608 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1609 		return;
1610 
1611 	if (!snd_soc_dai_active(cpu_dai)) {
1612 		mcasp->channels = 0;
1613 		mcasp->max_format_width = 0;
1614 	}
1615 }
1616 
1617 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1618 	.startup	= davinci_mcasp_startup,
1619 	.shutdown	= davinci_mcasp_shutdown,
1620 	.trigger	= davinci_mcasp_trigger,
1621 	.delay		= davinci_mcasp_delay,
1622 	.hw_params	= davinci_mcasp_hw_params,
1623 	.set_fmt	= davinci_mcasp_set_dai_fmt,
1624 	.set_clkdiv	= davinci_mcasp_set_clkdiv,
1625 	.set_sysclk	= davinci_mcasp_set_sysclk,
1626 	.set_tdm_slot	= davinci_mcasp_set_tdm_slot,
1627 };
1628 
davinci_mcasp_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1629 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol,
1630 				     struct snd_ctl_elem_info *uinfo)
1631 {
1632 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1633 	uinfo->count = 1;
1634 
1635 	return 0;
1636 }
1637 
davinci_mcasp_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)1638 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol,
1639 				    struct snd_ctl_elem_value *uctl)
1640 {
1641 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1642 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1643 
1644 	memcpy(uctl->value.iec958.status, &mcasp->iec958_status,
1645 	       sizeof(mcasp->iec958_status));
1646 
1647 	return 0;
1648 }
1649 
davinci_mcasp_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)1650 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol,
1651 				    struct snd_ctl_elem_value *uctl)
1652 {
1653 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1654 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1655 
1656 	memcpy(&mcasp->iec958_status, uctl->value.iec958.status,
1657 	       sizeof(mcasp->iec958_status));
1658 
1659 	return 0;
1660 }
1661 
davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1662 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol,
1663 					     struct snd_ctl_elem_value *ucontrol)
1664 {
1665 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1666 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1667 
1668 	memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));
1669 	return 0;
1670 }
1671 
1672 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = {
1673 	{
1674 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1675 			   SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1676 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1677 		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1678 		.info = davinci_mcasp_iec958_info,
1679 		.get = davinci_mcasp_iec958_get,
1680 		.put = davinci_mcasp_iec958_put,
1681 	}, {
1682 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1683 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1684 		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1685 		.info = davinci_mcasp_iec958_info,
1686 		.get = davinci_mcasp_iec958_con_mask_get,
1687 	},
1688 };
1689 
davinci_mcasp_init_iec958_status(struct davinci_mcasp * mcasp)1690 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)
1691 {
1692 	unsigned char *cs = (u8 *)&mcasp->iec958_status;
1693 
1694 	cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
1695 	cs[1] = IEC958_AES1_CON_PCM_CODER;
1696 	cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
1697 	cs[3] = IEC958_AES3_CON_CLOCK_1000PPM;
1698 }
1699 
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1700 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1701 {
1702 	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1703 
1704 	dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1705 	dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1706 
1707 	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {
1708 		davinci_mcasp_init_iec958_status(mcasp);
1709 		snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls,
1710 					 ARRAY_SIZE(davinci_mcasp_iec958_ctls));
1711 	}
1712 
1713 	return 0;
1714 }
1715 
1716 #define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000
1717 
1718 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1719 				SNDRV_PCM_FMTBIT_U8 | \
1720 				SNDRV_PCM_FMTBIT_S16_LE | \
1721 				SNDRV_PCM_FMTBIT_U16_LE | \
1722 				SNDRV_PCM_FMTBIT_S24_LE | \
1723 				SNDRV_PCM_FMTBIT_U24_LE | \
1724 				SNDRV_PCM_FMTBIT_S24_3LE | \
1725 				SNDRV_PCM_FMTBIT_U24_3LE | \
1726 				SNDRV_PCM_FMTBIT_S32_LE | \
1727 				SNDRV_PCM_FMTBIT_U32_LE)
1728 
1729 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1730 	{
1731 		.name		= "davinci-mcasp.0",
1732 		.probe		= davinci_mcasp_dai_probe,
1733 		.playback	= {
1734 			.stream_name = "IIS Playback",
1735 			.channels_min	= 1,
1736 			.channels_max	= 32 * 16,
1737 			.rates 		= DAVINCI_MCASP_RATES,
1738 			.formats	= DAVINCI_MCASP_PCM_FMTS,
1739 		},
1740 		.capture 	= {
1741 			.stream_name = "IIS Capture",
1742 			.channels_min 	= 1,
1743 			.channels_max	= 32 * 16,
1744 			.rates 		= DAVINCI_MCASP_RATES,
1745 			.formats	= DAVINCI_MCASP_PCM_FMTS,
1746 		},
1747 		.ops 		= &davinci_mcasp_dai_ops,
1748 
1749 		.symmetric_rate		= 1,
1750 	},
1751 	{
1752 		.name		= "davinci-mcasp.1",
1753 		.probe		= davinci_mcasp_dai_probe,
1754 		.playback 	= {
1755 			.stream_name = "DIT Playback",
1756 			.channels_min	= 1,
1757 			.channels_max	= 384,
1758 			.rates		= DAVINCI_MCASP_RATES,
1759 			.formats	= SNDRV_PCM_FMTBIT_S16_LE |
1760 					  SNDRV_PCM_FMTBIT_S24_LE,
1761 		},
1762 		.ops 		= &davinci_mcasp_dai_ops,
1763 	},
1764 
1765 };
1766 
1767 static const struct snd_soc_component_driver davinci_mcasp_component = {
1768 	.name		= "davinci-mcasp",
1769 };
1770 
1771 /* Some HW specific values and defaults. The rest is filled in from DT. */
1772 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1773 	.tx_dma_offset = 0x400,
1774 	.rx_dma_offset = 0x400,
1775 	.version = MCASP_VERSION_1,
1776 };
1777 
1778 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1779 	.tx_dma_offset = 0x2000,
1780 	.rx_dma_offset = 0x2000,
1781 	.version = MCASP_VERSION_2,
1782 };
1783 
1784 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1785 	.tx_dma_offset = 0,
1786 	.rx_dma_offset = 0,
1787 	.version = MCASP_VERSION_3,
1788 };
1789 
1790 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1791 	/* The CFG port offset will be calculated if it is needed */
1792 	.tx_dma_offset = 0,
1793 	.rx_dma_offset = 0,
1794 	.version = MCASP_VERSION_4,
1795 };
1796 
1797 static struct davinci_mcasp_pdata omap_mcasp_pdata = {
1798 	.tx_dma_offset = 0x200,
1799 	.rx_dma_offset = 0,
1800 	.version = MCASP_VERSION_OMAP,
1801 };
1802 
1803 static const struct of_device_id mcasp_dt_ids[] = {
1804 	{
1805 		.compatible = "ti,dm646x-mcasp-audio",
1806 		.data = &dm646x_mcasp_pdata,
1807 	},
1808 	{
1809 		.compatible = "ti,da830-mcasp-audio",
1810 		.data = &da830_mcasp_pdata,
1811 	},
1812 	{
1813 		.compatible = "ti,am33xx-mcasp-audio",
1814 		.data = &am33xx_mcasp_pdata,
1815 	},
1816 	{
1817 		.compatible = "ti,dra7-mcasp-audio",
1818 		.data = &dra7_mcasp_pdata,
1819 	},
1820 	{
1821 		.compatible = "ti,omap4-mcasp-audio",
1822 		.data = &omap_mcasp_pdata,
1823 	},
1824 	{ /* sentinel */ }
1825 };
1826 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1827 
mcasp_reparent_fck(struct platform_device * pdev)1828 static int mcasp_reparent_fck(struct platform_device *pdev)
1829 {
1830 	struct device_node *node = pdev->dev.of_node;
1831 	struct clk *gfclk, *parent_clk;
1832 	const char *parent_name;
1833 	int ret;
1834 
1835 	if (!node)
1836 		return 0;
1837 
1838 	parent_name = of_get_property(node, "fck_parent", NULL);
1839 	if (!parent_name)
1840 		return 0;
1841 
1842 	dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1843 
1844 	gfclk = clk_get(&pdev->dev, "fck");
1845 	if (IS_ERR(gfclk)) {
1846 		dev_err(&pdev->dev, "failed to get fck\n");
1847 		return PTR_ERR(gfclk);
1848 	}
1849 
1850 	parent_clk = clk_get(NULL, parent_name);
1851 	if (IS_ERR(parent_clk)) {
1852 		dev_err(&pdev->dev, "failed to get parent clock\n");
1853 		ret = PTR_ERR(parent_clk);
1854 		goto err1;
1855 	}
1856 
1857 	ret = clk_set_parent(gfclk, parent_clk);
1858 	if (ret) {
1859 		dev_err(&pdev->dev, "failed to reparent fck\n");
1860 		goto err2;
1861 	}
1862 
1863 err2:
1864 	clk_put(parent_clk);
1865 err1:
1866 	clk_put(gfclk);
1867 	return ret;
1868 }
1869 
davinci_mcasp_have_gpiochip(struct davinci_mcasp * mcasp)1870 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)
1871 {
1872 #ifdef CONFIG_OF_GPIO
1873 	return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");
1874 #else
1875 	return false;
1876 #endif
1877 }
1878 
davinci_mcasp_get_config(struct davinci_mcasp * mcasp,struct platform_device * pdev)1879 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
1880 				    struct platform_device *pdev)
1881 {
1882 	const struct of_device_id *match = of_match_device(mcasp_dt_ids, &pdev->dev);
1883 	struct device_node *np = pdev->dev.of_node;
1884 	struct davinci_mcasp_pdata *pdata = NULL;
1885 	const u32 *of_serial_dir32;
1886 	u32 val;
1887 	int i;
1888 
1889 	if (pdev->dev.platform_data) {
1890 		pdata = pdev->dev.platform_data;
1891 		pdata->dismod = DISMOD_LOW;
1892 		goto out;
1893 	} else if (match) {
1894 		pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1895 				     GFP_KERNEL);
1896 		if (!pdata)
1897 			return -ENOMEM;
1898 	} else {
1899 		dev_err(&pdev->dev, "No compatible match found\n");
1900 		return -EINVAL;
1901 	}
1902 
1903 	if (of_property_read_u32(np, "op-mode", &val) == 0) {
1904 		pdata->op_mode = val;
1905 	} else {
1906 		mcasp->missing_audio_param = true;
1907 		goto out;
1908 	}
1909 
1910 	if (of_property_read_u32(np, "tdm-slots", &val) == 0) {
1911 		if (val < 2 || val > 32) {
1912 			dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n");
1913 			return -EINVAL;
1914 		}
1915 
1916 		pdata->tdm_slots = val;
1917 	} else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) {
1918 		mcasp->missing_audio_param = true;
1919 		goto out;
1920 	}
1921 
1922 	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1923 	val /= sizeof(u32);
1924 	if (of_serial_dir32) {
1925 		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1926 						 (sizeof(*of_serial_dir) * val),
1927 						 GFP_KERNEL);
1928 		if (!of_serial_dir)
1929 			return -ENOMEM;
1930 
1931 		for (i = 0; i < val; i++)
1932 			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1933 
1934 		pdata->num_serializer = val;
1935 		pdata->serial_dir = of_serial_dir;
1936 	} else {
1937 		mcasp->missing_audio_param = true;
1938 		goto out;
1939 	}
1940 
1941 	if (of_property_read_u32(np, "tx-num-evt", &val) == 0)
1942 		pdata->txnumevt = val;
1943 
1944 	if (of_property_read_u32(np, "rx-num-evt", &val) == 0)
1945 		pdata->rxnumevt = val;
1946 
1947 	if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0)
1948 		mcasp->auxclk_fs_ratio = val;
1949 
1950 	if (of_property_read_u32(np, "dismod", &val) == 0) {
1951 		if (val == 0 || val == 2 || val == 3) {
1952 			pdata->dismod = DISMOD_VAL(val);
1953 		} else {
1954 			dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1955 			pdata->dismod = DISMOD_LOW;
1956 		}
1957 	} else {
1958 		pdata->dismod = DISMOD_LOW;
1959 	}
1960 
1961 out:
1962 	mcasp->pdata = pdata;
1963 
1964 	if (mcasp->missing_audio_param) {
1965 		if (davinci_mcasp_have_gpiochip(mcasp)) {
1966 			dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n");
1967 			return 0;
1968 		}
1969 
1970 		dev_err(&pdev->dev, "Insufficient DT parameter(s)\n");
1971 		return -ENODEV;
1972 	}
1973 
1974 	mcasp->op_mode = pdata->op_mode;
1975 	/* sanity check for tdm slots parameter */
1976 	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1977 		if (pdata->tdm_slots < 2) {
1978 			dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1979 				 pdata->tdm_slots);
1980 			mcasp->tdm_slots = 2;
1981 		} else if (pdata->tdm_slots > 32) {
1982 			dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1983 				 pdata->tdm_slots);
1984 			mcasp->tdm_slots = 32;
1985 		} else {
1986 			mcasp->tdm_slots = pdata->tdm_slots;
1987 		}
1988 	} else {
1989 		mcasp->tdm_slots = 32;
1990 	}
1991 
1992 	mcasp->num_serializer = pdata->num_serializer;
1993 #ifdef CONFIG_PM
1994 	mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1995 						mcasp->num_serializer, sizeof(u32),
1996 						GFP_KERNEL);
1997 	if (!mcasp->context.xrsr_regs)
1998 		return -ENOMEM;
1999 #endif
2000 	mcasp->serial_dir = pdata->serial_dir;
2001 	mcasp->version = pdata->version;
2002 	mcasp->txnumevt = pdata->txnumevt;
2003 	mcasp->rxnumevt = pdata->rxnumevt;
2004 	mcasp->dismod = pdata->dismod;
2005 
2006 	return 0;
2007 }
2008 
2009 enum {
2010 	PCM_EDMA,
2011 	PCM_SDMA,
2012 	PCM_UDMA,
2013 };
2014 static const char *sdma_prefix = "ti,omap";
2015 
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)2016 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
2017 {
2018 	struct dma_chan *chan;
2019 	const char *tmp;
2020 	int ret = PCM_EDMA;
2021 
2022 	if (!mcasp->dev->of_node)
2023 		return PCM_EDMA;
2024 
2025 	tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
2026 	chan = dma_request_chan(mcasp->dev, tmp);
2027 	if (IS_ERR(chan))
2028 		return dev_err_probe(mcasp->dev, PTR_ERR(chan),
2029 				     "Can't verify DMA configuration\n");
2030 	if (WARN_ON(!chan->device || !chan->device->dev)) {
2031 		dma_release_channel(chan);
2032 		return -EINVAL;
2033 	}
2034 
2035 	if (chan->device->dev->of_node)
2036 		ret = of_property_read_string(chan->device->dev->of_node,
2037 					      "compatible", &tmp);
2038 	else
2039 		dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
2040 
2041 	dma_release_channel(chan);
2042 	if (ret)
2043 		return ret;
2044 
2045 	dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
2046 	if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
2047 		return PCM_SDMA;
2048 	else if (strstr(tmp, "udmap"))
2049 		return PCM_UDMA;
2050 	else if (strstr(tmp, "bcdma"))
2051 		return PCM_UDMA;
2052 
2053 	return PCM_EDMA;
2054 }
2055 
davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata * pdata)2056 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
2057 {
2058 	int i;
2059 	u32 offset = 0;
2060 
2061 	if (pdata->version != MCASP_VERSION_4)
2062 		return pdata->tx_dma_offset;
2063 
2064 	for (i = 0; i < pdata->num_serializer; i++) {
2065 		if (pdata->serial_dir[i] == TX_MODE) {
2066 			if (!offset) {
2067 				offset = DAVINCI_MCASP_TXBUF_REG(i);
2068 			} else {
2069 				pr_err("%s: Only one serializer allowed!\n",
2070 				       __func__);
2071 				break;
2072 			}
2073 		}
2074 	}
2075 
2076 	return offset;
2077 }
2078 
davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata * pdata)2079 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
2080 {
2081 	int i;
2082 	u32 offset = 0;
2083 
2084 	if (pdata->version != MCASP_VERSION_4)
2085 		return pdata->rx_dma_offset;
2086 
2087 	for (i = 0; i < pdata->num_serializer; i++) {
2088 		if (pdata->serial_dir[i] == RX_MODE) {
2089 			if (!offset) {
2090 				offset = DAVINCI_MCASP_RXBUF_REG(i);
2091 			} else {
2092 				pr_err("%s: Only one serializer allowed!\n",
2093 				       __func__);
2094 				break;
2095 			}
2096 		}
2097 	}
2098 
2099 	return offset;
2100 }
2101 
2102 #ifdef CONFIG_GPIOLIB
davinci_mcasp_gpio_request(struct gpio_chip * chip,unsigned offset)2103 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
2104 {
2105 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2106 
2107 	if (mcasp->num_serializer && offset < mcasp->num_serializer &&
2108 	    mcasp->serial_dir[offset] != INACTIVE_MODE) {
2109 		dev_err(mcasp->dev, "AXR%u pin is  used for audio\n", offset);
2110 		return -EBUSY;
2111 	}
2112 
2113 	/* Do not change the PIN yet */
2114 
2115 	return pm_runtime_get_sync(mcasp->dev);
2116 }
2117 
davinci_mcasp_gpio_free(struct gpio_chip * chip,unsigned offset)2118 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
2119 {
2120 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2121 
2122 	/* Set the direction to input */
2123 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2124 
2125 	/* Set the pin as McASP pin */
2126 	mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2127 
2128 	pm_runtime_put_sync(mcasp->dev);
2129 }
2130 
davinci_mcasp_gpio_direction_out(struct gpio_chip * chip,unsigned offset,int value)2131 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
2132 					    unsigned offset, int value)
2133 {
2134 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2135 	u32 val;
2136 
2137 	if (value)
2138 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2139 	else
2140 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2141 
2142 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2143 	if (!(val & BIT(offset))) {
2144 		/* Set the pin as GPIO pin */
2145 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2146 
2147 		/* Set the direction to output */
2148 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2149 	}
2150 
2151 	return 0;
2152 }
2153 
davinci_mcasp_gpio_set(struct gpio_chip * chip,unsigned offset,int value)2154 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2155 				  int value)
2156 {
2157 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2158 
2159 	if (value)
2160 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2161 	else
2162 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2163 }
2164 
davinci_mcasp_gpio_direction_in(struct gpio_chip * chip,unsigned offset)2165 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2166 					   unsigned offset)
2167 {
2168 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2169 	u32 val;
2170 
2171 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2172 	if (!(val & BIT(offset))) {
2173 		/* Set the direction to input */
2174 		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2175 
2176 		/* Set the pin as GPIO pin */
2177 		mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2178 	}
2179 
2180 	return 0;
2181 }
2182 
davinci_mcasp_gpio_get(struct gpio_chip * chip,unsigned offset)2183 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2184 {
2185 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2186 	u32 val;
2187 
2188 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2189 	if (val & BIT(offset))
2190 		return 1;
2191 
2192 	return 0;
2193 }
2194 
davinci_mcasp_gpio_get_direction(struct gpio_chip * chip,unsigned offset)2195 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2196 					    unsigned offset)
2197 {
2198 	struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2199 	u32 val;
2200 
2201 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2202 	if (val & BIT(offset))
2203 		return 0;
2204 
2205 	return 1;
2206 }
2207 
2208 static const struct gpio_chip davinci_mcasp_template_chip = {
2209 	.owner			= THIS_MODULE,
2210 	.request		= davinci_mcasp_gpio_request,
2211 	.free			= davinci_mcasp_gpio_free,
2212 	.direction_output	= davinci_mcasp_gpio_direction_out,
2213 	.set			= davinci_mcasp_gpio_set,
2214 	.direction_input	= davinci_mcasp_gpio_direction_in,
2215 	.get			= davinci_mcasp_gpio_get,
2216 	.get_direction		= davinci_mcasp_gpio_get_direction,
2217 	.base			= -1,
2218 	.ngpio			= 32,
2219 };
2220 
davinci_mcasp_init_gpiochip(struct davinci_mcasp * mcasp)2221 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2222 {
2223 	if (!davinci_mcasp_have_gpiochip(mcasp))
2224 		return 0;
2225 
2226 	mcasp->gpio_chip = davinci_mcasp_template_chip;
2227 	mcasp->gpio_chip.label = dev_name(mcasp->dev);
2228 	mcasp->gpio_chip.parent = mcasp->dev;
2229 
2230 	return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2231 }
2232 
2233 #else /* CONFIG_GPIOLIB */
davinci_mcasp_init_gpiochip(struct davinci_mcasp * mcasp)2234 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2235 {
2236 	return 0;
2237 }
2238 #endif /* CONFIG_GPIOLIB */
2239 
davinci_mcasp_probe(struct platform_device * pdev)2240 static int davinci_mcasp_probe(struct platform_device *pdev)
2241 {
2242 	struct snd_dmaengine_dai_dma_data *dma_data;
2243 	struct resource *mem, *dat;
2244 	struct davinci_mcasp *mcasp;
2245 	char *irq_name;
2246 	int irq;
2247 	int ret;
2248 
2249 	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2250 		dev_err(&pdev->dev, "No platform data supplied\n");
2251 		return -EINVAL;
2252 	}
2253 
2254 	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2255 			   GFP_KERNEL);
2256 	if (!mcasp)
2257 		return	-ENOMEM;
2258 
2259 	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2260 	if (!mem) {
2261 		dev_warn(&pdev->dev,
2262 			 "\"mpu\" mem resource not found, using index 0\n");
2263 		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2264 		if (!mem) {
2265 			dev_err(&pdev->dev, "no mem resource?\n");
2266 			return -ENODEV;
2267 		}
2268 	}
2269 
2270 	mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2271 	if (IS_ERR(mcasp->base))
2272 		return PTR_ERR(mcasp->base);
2273 
2274 	dev_set_drvdata(&pdev->dev, mcasp);
2275 	pm_runtime_enable(&pdev->dev);
2276 
2277 	mcasp->dev = &pdev->dev;
2278 	ret = davinci_mcasp_get_config(mcasp, pdev);
2279 	if (ret)
2280 		goto err;
2281 
2282 	/* All PINS as McASP */
2283 	pm_runtime_get_sync(mcasp->dev);
2284 	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2285 	pm_runtime_put(mcasp->dev);
2286 
2287 	/* Skip audio related setup code if the configuration is not adequat */
2288 	if (mcasp->missing_audio_param)
2289 		goto no_audio;
2290 
2291 	irq = platform_get_irq_byname_optional(pdev, "common");
2292 	if (irq > 0) {
2293 		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2294 					  dev_name(&pdev->dev));
2295 		if (!irq_name) {
2296 			ret = -ENOMEM;
2297 			goto err;
2298 		}
2299 		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2300 						davinci_mcasp_common_irq_handler,
2301 						IRQF_ONESHOT | IRQF_SHARED,
2302 						irq_name, mcasp);
2303 		if (ret) {
2304 			dev_err(&pdev->dev, "common IRQ request failed\n");
2305 			goto err;
2306 		}
2307 
2308 		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2309 		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2310 	}
2311 
2312 	irq = platform_get_irq_byname_optional(pdev, "rx");
2313 	if (irq > 0) {
2314 		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2315 					  dev_name(&pdev->dev));
2316 		if (!irq_name) {
2317 			ret = -ENOMEM;
2318 			goto err;
2319 		}
2320 		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2321 						davinci_mcasp_rx_irq_handler,
2322 						IRQF_ONESHOT, irq_name, mcasp);
2323 		if (ret) {
2324 			dev_err(&pdev->dev, "RX IRQ request failed\n");
2325 			goto err;
2326 		}
2327 
2328 		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2329 	}
2330 
2331 	irq = platform_get_irq_byname_optional(pdev, "tx");
2332 	if (irq > 0) {
2333 		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2334 					  dev_name(&pdev->dev));
2335 		if (!irq_name) {
2336 			ret = -ENOMEM;
2337 			goto err;
2338 		}
2339 		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2340 						davinci_mcasp_tx_irq_handler,
2341 						IRQF_ONESHOT, irq_name, mcasp);
2342 		if (ret) {
2343 			dev_err(&pdev->dev, "TX IRQ request failed\n");
2344 			goto err;
2345 		}
2346 
2347 		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2348 	}
2349 
2350 	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2351 	if (dat)
2352 		mcasp->dat_port = true;
2353 
2354 	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2355 	dma_data->filter_data = "tx";
2356 	if (dat) {
2357 		dma_data->addr = dat->start;
2358 		/*
2359 		 * According to the TRM there should be 0x200 offset added to
2360 		 * the DAT port address
2361 		 */
2362 		if (mcasp->version == MCASP_VERSION_OMAP)
2363 			dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);
2364 	} else {
2365 		dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);
2366 	}
2367 
2368 
2369 	/* RX is not valid in DIT mode */
2370 	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2371 		dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2372 		dma_data->filter_data = "rx";
2373 		if (dat)
2374 			dma_data->addr = dat->start;
2375 		else
2376 			dma_data->addr =
2377 				mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);
2378 	}
2379 
2380 	if (mcasp->version < MCASP_VERSION_3) {
2381 		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2382 		/* dma_params->dma_addr is pointing to the data port address */
2383 		mcasp->dat_port = true;
2384 	} else {
2385 		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2386 	}
2387 
2388 	/* Allocate memory for long enough list for all possible
2389 	 * scenarios. Maximum number tdm slots is 32 and there cannot
2390 	 * be more serializers than given in the configuration.  The
2391 	 * serializer directions could be taken into account, but it
2392 	 * would make code much more complex and save only couple of
2393 	 * bytes.
2394 	 */
2395 	mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2396 		devm_kcalloc(mcasp->dev,
2397 			     32 + mcasp->num_serializer - 1,
2398 			     sizeof(unsigned int),
2399 			     GFP_KERNEL);
2400 
2401 	mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2402 		devm_kcalloc(mcasp->dev,
2403 			     32 + mcasp->num_serializer - 1,
2404 			     sizeof(unsigned int),
2405 			     GFP_KERNEL);
2406 
2407 	if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2408 	    !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2409 		ret = -ENOMEM;
2410 		goto err;
2411 	}
2412 
2413 	ret = davinci_mcasp_set_ch_constraints(mcasp);
2414 	if (ret)
2415 		goto err;
2416 
2417 	mcasp_reparent_fck(pdev);
2418 
2419 	ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
2420 					      &davinci_mcasp_dai[mcasp->op_mode], 1);
2421 
2422 	if (ret != 0)
2423 		goto err;
2424 
2425 	ret = davinci_mcasp_get_dma_type(mcasp);
2426 	switch (ret) {
2427 	case PCM_EDMA:
2428 		ret = edma_pcm_platform_register(&pdev->dev);
2429 		break;
2430 	case PCM_SDMA:
2431 		if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
2432 			ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2433 		else
2434 			ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL);
2435 		break;
2436 	case PCM_UDMA:
2437 		ret = udma_pcm_platform_register(&pdev->dev);
2438 		break;
2439 	default:
2440 		dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2441 		fallthrough;
2442 	case -EPROBE_DEFER:
2443 		goto err;
2444 	}
2445 
2446 	if (ret) {
2447 		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2448 		goto err;
2449 	}
2450 
2451 no_audio:
2452 	ret = davinci_mcasp_init_gpiochip(mcasp);
2453 	if (ret) {
2454 		dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret);
2455 		goto err;
2456 	}
2457 
2458 	return 0;
2459 err:
2460 	pm_runtime_disable(&pdev->dev);
2461 	return ret;
2462 }
2463 
davinci_mcasp_remove(struct platform_device * pdev)2464 static int davinci_mcasp_remove(struct platform_device *pdev)
2465 {
2466 	pm_runtime_disable(&pdev->dev);
2467 
2468 	return 0;
2469 }
2470 
2471 #ifdef CONFIG_PM
davinci_mcasp_runtime_suspend(struct device * dev)2472 static int davinci_mcasp_runtime_suspend(struct device *dev)
2473 {
2474 	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2475 	struct davinci_mcasp_context *context = &mcasp->context;
2476 	u32 reg;
2477 	int i;
2478 
2479 	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2480 		context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2481 
2482 	if (mcasp->txnumevt) {
2483 		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2484 		context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2485 	}
2486 	if (mcasp->rxnumevt) {
2487 		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2488 		context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2489 	}
2490 
2491 	for (i = 0; i < mcasp->num_serializer; i++)
2492 		context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2493 						DAVINCI_MCASP_XRSRCTL_REG(i));
2494 
2495 	return 0;
2496 }
2497 
davinci_mcasp_runtime_resume(struct device * dev)2498 static int davinci_mcasp_runtime_resume(struct device *dev)
2499 {
2500 	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2501 	struct davinci_mcasp_context *context = &mcasp->context;
2502 	u32 reg;
2503 	int i;
2504 
2505 	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2506 		mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2507 
2508 	if (mcasp->txnumevt) {
2509 		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2510 		mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2511 	}
2512 	if (mcasp->rxnumevt) {
2513 		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2514 		mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2515 	}
2516 
2517 	for (i = 0; i < mcasp->num_serializer; i++)
2518 		mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2519 			      context->xrsr_regs[i]);
2520 
2521 	return 0;
2522 }
2523 
2524 #endif
2525 
2526 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2527 	SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2528 			   davinci_mcasp_runtime_resume,
2529 			   NULL)
2530 };
2531 
2532 static struct platform_driver davinci_mcasp_driver = {
2533 	.probe		= davinci_mcasp_probe,
2534 	.remove		= davinci_mcasp_remove,
2535 	.driver		= {
2536 		.name	= "davinci-mcasp",
2537 		.pm     = &davinci_mcasp_pm_ops,
2538 		.of_match_table = mcasp_dt_ids,
2539 	},
2540 };
2541 
2542 module_platform_driver(davinci_mcasp_driver);
2543 
2544 MODULE_AUTHOR("Steve Chen");
2545 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2546 MODULE_LICENSE("GPL");
2547