1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __TAG_QCA_H 4 #define __TAG_QCA_H 5 6 #define QCA_HDR_LEN 2 7 #define QCA_HDR_VERSION 0x2 8 9 #define QCA_HDR_RECV_VERSION GENMASK(15, 14) 10 #define QCA_HDR_RECV_PRIORITY GENMASK(13, 11) 11 #define QCA_HDR_RECV_TYPE GENMASK(10, 6) 12 #define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) 13 #define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0) 14 15 /* Packet type for recv */ 16 #define QCA_HDR_RECV_TYPE_NORMAL 0x0 17 #define QCA_HDR_RECV_TYPE_MIB 0x1 18 #define QCA_HDR_RECV_TYPE_RW_REG_ACK 0x2 19 20 #define QCA_HDR_XMIT_VERSION GENMASK(15, 14) 21 #define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11) 22 #define QCA_HDR_XMIT_CONTROL GENMASK(10, 8) 23 #define QCA_HDR_XMIT_FROM_CPU BIT(7) 24 #define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0) 25 26 /* Packet type for xmit */ 27 #define QCA_HDR_XMIT_TYPE_NORMAL 0x0 28 #define QCA_HDR_XMIT_TYPE_RW_REG 0x1 29 30 /* Check code for a valid mgmt packet. Switch will ignore the packet 31 * with this wrong. 32 */ 33 #define QCA_HDR_MGMT_CHECK_CODE_VAL 0x5 34 35 /* Specific define for in-band MDIO read/write with Ethernet packet */ 36 #define QCA_HDR_MGMT_SEQ_LEN 4 /* 4 byte for the seq */ 37 #define QCA_HDR_MGMT_COMMAND_LEN 4 /* 4 byte for the command */ 38 #define QCA_HDR_MGMT_DATA1_LEN 4 /* First 4 byte for the mdio data */ 39 #define QCA_HDR_MGMT_HEADER_LEN (QCA_HDR_MGMT_SEQ_LEN + \ 40 QCA_HDR_MGMT_COMMAND_LEN + \ 41 QCA_HDR_MGMT_DATA1_LEN) 42 43 #define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */ 44 #define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */ 45 46 #define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \ 47 QCA_HDR_LEN + \ 48 QCA_HDR_MGMT_DATA2_LEN + \ 49 QCA_HDR_MGMT_PADDING_LEN) 50 51 #define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */ 52 #define QCA_HDR_MGMT_CHECK_CODE GENMASK(31, 29) /* 31, 29 */ 53 #define QCA_HDR_MGMT_CMD BIT(28) /* 28 */ 54 #define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */ 55 #define QCA_HDR_MGMT_ADDR GENMASK(18, 0) /* 18, 0 */ 56 57 /* Special struct emulating a Ethernet header */ 58 struct qca_mgmt_ethhdr { 59 u32 command; /* command bit 31:0 */ 60 u32 seq; /* seq 63:32 */ 61 u32 mdio_data; /* first 4byte mdio */ 62 __be16 hdr; /* qca hdr */ 63 } __packed; 64 65 enum mdio_cmd { 66 MDIO_WRITE = 0x0, 67 MDIO_READ 68 }; 69 70 struct mib_ethhdr { 71 u32 data[3]; /* first 3 mib counter */ 72 __be16 hdr; /* qca hdr */ 73 } __packed; 74 75 struct qca_tagger_data { 76 void (*rw_reg_ack_handler)(struct dsa_switch *ds, 77 struct sk_buff *skb); 78 void (*mib_autocast_handler)(struct dsa_switch *ds, 79 struct sk_buff *skb); 80 }; 81 82 #endif /* __TAG_QCA_H */ 83