1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/mb862xx/mb862xxfb.c
4 *
5 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
6 *
7 * (C) 2008 Anatolij Gustschin <agust@denx.de>
8 * DENX Software Engineering
9 */
10
11 #undef DEBUG
12
13 #include <linux/fb.h>
14 #include <linux/delay.h>
15 #include <linux/uaccess.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #if defined(CONFIG_OF)
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #endif
25 #include "mb862xxfb.h"
26 #include "mb862xx_reg.h"
27
28 #define NR_PALETTE 256
29 #define MB862XX_MEM_SIZE 0x1000000
30 #define CORALP_MEM_SIZE 0x2000000
31 #define CARMINE_MEM_SIZE 0x8000000
32 #define DRV_NAME "mb862xxfb"
33
34 #if defined(CONFIG_SOCRATES)
35 static struct mb862xx_gc_mode socrates_gc_mode = {
36 /* Mode for Prime View PM070WL4 TFT LCD Panel */
37 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
38 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
39 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
40 };
41 #endif
42
43 /* Helpers */
h_total(struct fb_var_screeninfo * var)44 static inline int h_total(struct fb_var_screeninfo *var)
45 {
46 return var->xres + var->left_margin +
47 var->right_margin + var->hsync_len;
48 }
49
v_total(struct fb_var_screeninfo * var)50 static inline int v_total(struct fb_var_screeninfo *var)
51 {
52 return var->yres + var->upper_margin +
53 var->lower_margin + var->vsync_len;
54 }
55
hsp(struct fb_var_screeninfo * var)56 static inline int hsp(struct fb_var_screeninfo *var)
57 {
58 return var->xres + var->right_margin - 1;
59 }
60
vsp(struct fb_var_screeninfo * var)61 static inline int vsp(struct fb_var_screeninfo *var)
62 {
63 return var->yres + var->lower_margin - 1;
64 }
65
d_pitch(struct fb_var_screeninfo * var)66 static inline int d_pitch(struct fb_var_screeninfo *var)
67 {
68 return var->xres * var->bits_per_pixel / 8;
69 }
70
chan_to_field(unsigned int chan,struct fb_bitfield * bf)71 static inline unsigned int chan_to_field(unsigned int chan,
72 struct fb_bitfield *bf)
73 {
74 chan &= 0xffff;
75 chan >>= 16 - bf->length;
76 return chan << bf->offset;
77 }
78
mb862xxfb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)79 static int mb862xxfb_setcolreg(unsigned regno,
80 unsigned red, unsigned green, unsigned blue,
81 unsigned transp, struct fb_info *info)
82 {
83 struct mb862xxfb_par *par = info->par;
84 unsigned int val;
85
86 switch (info->fix.visual) {
87 case FB_VISUAL_TRUECOLOR:
88 if (regno < 16) {
89 val = chan_to_field(red, &info->var.red);
90 val |= chan_to_field(green, &info->var.green);
91 val |= chan_to_field(blue, &info->var.blue);
92 par->pseudo_palette[regno] = val;
93 }
94 break;
95 case FB_VISUAL_PSEUDOCOLOR:
96 if (regno < 256) {
97 val = (red >> 8) << 16;
98 val |= (green >> 8) << 8;
99 val |= blue >> 8;
100 outreg(disp, GC_L0PAL0 + (regno * 4), val);
101 }
102 break;
103 default:
104 return 1; /* unsupported type */
105 }
106 return 0;
107 }
108
mb862xxfb_check_var(struct fb_var_screeninfo * var,struct fb_info * fbi)109 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
110 struct fb_info *fbi)
111 {
112 unsigned long tmp;
113
114 if (fbi->dev)
115 dev_dbg(fbi->dev, "%s\n", __func__);
116
117 /* check if these values fit into the registers */
118 if (var->hsync_len > 255 || var->vsync_len > 255)
119 return -EINVAL;
120
121 if ((var->xres + var->right_margin) >= 4096)
122 return -EINVAL;
123
124 if ((var->yres + var->lower_margin) > 4096)
125 return -EINVAL;
126
127 if (h_total(var) > 4096 || v_total(var) > 4096)
128 return -EINVAL;
129
130 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
131 return -EINVAL;
132
133 if (var->bits_per_pixel <= 8)
134 var->bits_per_pixel = 8;
135 else if (var->bits_per_pixel <= 16)
136 var->bits_per_pixel = 16;
137 else if (var->bits_per_pixel <= 32)
138 var->bits_per_pixel = 32;
139
140 /*
141 * can cope with 8,16 or 24/32bpp if resulting
142 * pitch is divisible by 64 without remainder
143 */
144 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
145 int r;
146
147 var->bits_per_pixel = 0;
148 do {
149 var->bits_per_pixel += 8;
150 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
151 } while (r && var->bits_per_pixel <= 32);
152
153 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
154 return -EINVAL;
155 }
156
157 /* line length is going to be 128 bit aligned */
158 tmp = (var->xres * var->bits_per_pixel) / 8;
159 if ((tmp & 15) != 0)
160 return -EINVAL;
161
162 /* set r/g/b positions and validate bpp */
163 switch (var->bits_per_pixel) {
164 case 8:
165 var->red.length = var->bits_per_pixel;
166 var->green.length = var->bits_per_pixel;
167 var->blue.length = var->bits_per_pixel;
168 var->red.offset = 0;
169 var->green.offset = 0;
170 var->blue.offset = 0;
171 var->transp.length = 0;
172 break;
173 case 16:
174 var->red.length = 5;
175 var->green.length = 5;
176 var->blue.length = 5;
177 var->red.offset = 10;
178 var->green.offset = 5;
179 var->blue.offset = 0;
180 var->transp.length = 0;
181 break;
182 case 24:
183 case 32:
184 var->transp.length = 8;
185 var->red.length = 8;
186 var->green.length = 8;
187 var->blue.length = 8;
188 var->transp.offset = 24;
189 var->red.offset = 16;
190 var->green.offset = 8;
191 var->blue.offset = 0;
192 break;
193 default:
194 return -EINVAL;
195 }
196 return 0;
197 }
198
199 static struct fb_ops mb862xxfb_ops;
200
201 /*
202 * set display parameters
203 */
mb862xxfb_set_par(struct fb_info * fbi)204 static int mb862xxfb_set_par(struct fb_info *fbi)
205 {
206 struct mb862xxfb_par *par = fbi->par;
207 unsigned long reg, sc;
208
209 dev_dbg(par->dev, "%s\n", __func__);
210 if (par->type == BT_CORALP)
211 mb862xxfb_init_accel(fbi, &mb862xxfb_ops, fbi->var.xres);
212
213 if (par->pre_init)
214 return 0;
215
216 /* disp off */
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
220
221 /* set display reference clock div. */
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
225 reg |= sc << 8;
226 outreg(disp, GC_DCM1, reg);
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
228
229 /* disp dimension, format */
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
231 (fbi->var.yres - 1));
232 if (fbi->var.bits_per_pixel == 16)
233 reg |= GC_L0M_L0C_16;
234 outreg(disp, GC_L0M, reg);
235
236 if (fbi->var.bits_per_pixel == 32) {
237 reg = inreg(disp, GC_L0EM);
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
239 }
240 outreg(disp, GC_WY_WX, 0);
241 reg = pack(fbi->var.yres - 1, fbi->var.xres);
242 outreg(disp, GC_WH_WW, reg);
243 outreg(disp, GC_L0OA0, 0);
244 outreg(disp, GC_L0DA0, 0);
245 outreg(disp, GC_L0DY_L0DX, 0);
246 outreg(disp, GC_L0WY_L0WX, 0);
247 outreg(disp, GC_L0WH_L0WW, reg);
248
249 /* both HW-cursors off */
250 reg = inreg(disp, GC_CPM_CUTC);
251 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
252 outreg(disp, GC_CPM_CUTC, reg);
253
254 /* timings */
255 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
256 outreg(disp, GC_HDB_HDP, reg);
257 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
258 outreg(disp, GC_VDP_VSP, reg);
259 reg = ((fbi->var.vsync_len - 1) << 24) |
260 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
261 outreg(disp, GC_VSW_HSW_HSP, reg);
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
264
265 /* display on */
266 reg = inreg(disp, GC_DCM1);
267 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
268 reg &= ~GC_DCM01_ESY;
269 outreg(disp, GC_DCM1, reg);
270 return 0;
271 }
272
mb862xxfb_pan(struct fb_var_screeninfo * var,struct fb_info * info)273 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
274 struct fb_info *info)
275 {
276 struct mb862xxfb_par *par = info->par;
277 unsigned long reg;
278
279 reg = pack(var->yoffset, var->xoffset);
280 outreg(disp, GC_L0WY_L0WX, reg);
281
282 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
283 outreg(disp, GC_L0WH_L0WW, reg);
284 return 0;
285 }
286
mb862xxfb_blank(int mode,struct fb_info * fbi)287 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
288 {
289 struct mb862xxfb_par *par = fbi->par;
290 unsigned long reg;
291
292 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
293
294 switch (mode) {
295 case FB_BLANK_POWERDOWN:
296 reg = inreg(disp, GC_DCM1);
297 reg &= ~GC_DCM01_DEN;
298 outreg(disp, GC_DCM1, reg);
299 break;
300 case FB_BLANK_UNBLANK:
301 reg = inreg(disp, GC_DCM1);
302 reg |= GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_NORMAL:
306 case FB_BLANK_VSYNC_SUSPEND:
307 case FB_BLANK_HSYNC_SUSPEND:
308 default:
309 return 1;
310 }
311 return 0;
312 }
313
mb862xxfb_ioctl(struct fb_info * fbi,unsigned int cmd,unsigned long arg)314 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
315 unsigned long arg)
316 {
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
319 void __user *argp = (void __user *)arg;
320 int *enable;
321 u32 l1em = 0;
322
323 switch (cmd) {
324 case MB862XX_L1_GET_CFG:
325 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
326 return -EFAULT;
327 break;
328 case MB862XX_L1_SET_CFG:
329 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
330 return -EFAULT;
331 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
332 return -EINVAL;
333 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
334 /* downscaling */
335 outreg(cap, GC_CAP_CSC,
336 pack((l1_cfg->sh << 11) / l1_cfg->dh,
337 (l1_cfg->sw << 11) / l1_cfg->dw));
338 l1em = inreg(disp, GC_L1EM);
339 l1em &= ~GC_L1EM_DM;
340 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
341 (l1_cfg->sh <= l1_cfg->dh)) {
342 /* upscaling */
343 outreg(cap, GC_CAP_CSC,
344 pack((l1_cfg->sh << 11) / l1_cfg->dh,
345 (l1_cfg->sw << 11) / l1_cfg->dw));
346 outreg(cap, GC_CAP_CMSS,
347 pack(l1_cfg->sw >> 1, l1_cfg->sh));
348 outreg(cap, GC_CAP_CMDS,
349 pack(l1_cfg->dw >> 1, l1_cfg->dh));
350 l1em = inreg(disp, GC_L1EM);
351 l1em |= GC_L1EM_DM;
352 }
353
354 if (l1_cfg->mirror) {
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
357 l1em |= l1_cfg->dw * 2 - 8;
358 } else {
359 outreg(cap, GC_CAP_CBM,
360 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
361 l1em &= 0xffff0000;
362 }
363 outreg(disp, GC_L1EM, l1em);
364 break;
365 case MB862XX_L1_ENABLE:
366 enable = (int *)arg;
367 if (*enable) {
368 outreg(disp, GC_L1DA, par->cap_buf);
369 outreg(cap, GC_CAP_IMG_START,
370 pack(l1_cfg->sy >> 1, l1_cfg->sx));
371 outreg(cap, GC_CAP_IMG_END,
372 pack(l1_cfg->sh, l1_cfg->sw));
373 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
374 (par->l1_stride << 16));
375 outreg(disp, GC_L1WY_L1WX,
376 pack(l1_cfg->dy, l1_cfg->dx));
377 outreg(disp, GC_L1WH_L1WW,
378 pack(l1_cfg->dh - 1, l1_cfg->dw));
379 outreg(disp, GC_DLS, 1);
380 outreg(cap, GC_CAP_VCM,
381 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
382 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
383 GC_DCM1_DEN | GC_DCM1_L1E);
384 } else {
385 outreg(cap, GC_CAP_VCM,
386 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
387 outreg(disp, GC_DCM1,
388 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
389 }
390 break;
391 case MB862XX_L1_CAP_CTL:
392 enable = (int *)arg;
393 if (*enable) {
394 outreg(cap, GC_CAP_VCM,
395 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
396 } else {
397 outreg(cap, GC_CAP_VCM,
398 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
399 }
400 break;
401 default:
402 return -EINVAL;
403 }
404 return 0;
405 }
406
407 /* framebuffer ops */
408 static struct fb_ops mb862xxfb_ops = {
409 .owner = THIS_MODULE,
410 .fb_check_var = mb862xxfb_check_var,
411 .fb_set_par = mb862xxfb_set_par,
412 .fb_setcolreg = mb862xxfb_setcolreg,
413 .fb_blank = mb862xxfb_blank,
414 .fb_pan_display = mb862xxfb_pan,
415 .fb_fillrect = cfb_fillrect,
416 .fb_copyarea = cfb_copyarea,
417 .fb_imageblit = cfb_imageblit,
418 .fb_ioctl = mb862xxfb_ioctl,
419 };
420
421 /* initialize fb_info data */
mb862xxfb_init_fbinfo(struct fb_info * fbi)422 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
423 {
424 struct mb862xxfb_par *par = fbi->par;
425 struct mb862xx_gc_mode *mode = par->gc_mode;
426 unsigned long reg;
427 int stride;
428
429 fbi->fbops = &mb862xxfb_ops;
430 fbi->pseudo_palette = par->pseudo_palette;
431 fbi->screen_base = par->fb_base;
432 fbi->screen_size = par->mapped_vram;
433
434 strcpy(fbi->fix.id, DRV_NAME);
435 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
436 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
437 fbi->fix.mmio_len = par->mmio_len;
438 fbi->fix.accel = FB_ACCEL_NONE;
439 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
440 fbi->fix.type_aux = 0;
441 fbi->fix.xpanstep = 1;
442 fbi->fix.ypanstep = 1;
443 fbi->fix.ywrapstep = 0;
444
445 reg = inreg(disp, GC_DCM1);
446 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
447 /* get the disp mode from active display cfg */
448 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
449 unsigned long hsp, vsp, ht, vt;
450
451 dev_dbg(par->dev, "using bootloader's disp. mode\n");
452 fbi->var.pixclock = (sc * 1000000) / par->refclk;
453 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
454 reg = inreg(disp, GC_VDP_VSP);
455 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
456 vsp = (reg & 0x0fff) + 1;
457 fbi->var.xres_virtual = fbi->var.xres;
458 fbi->var.yres_virtual = fbi->var.yres;
459 reg = inreg(disp, GC_L0EM);
460 if (reg & GC_L0EM_L0EC_24) {
461 fbi->var.bits_per_pixel = 32;
462 } else {
463 reg = inreg(disp, GC_L0M);
464 if (reg & GC_L0M_L0C_16)
465 fbi->var.bits_per_pixel = 16;
466 else
467 fbi->var.bits_per_pixel = 8;
468 }
469 reg = inreg(disp, GC_VSW_HSW_HSP);
470 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
471 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
472 hsp = (reg & 0xffff) + 1;
473 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
474 fbi->var.right_margin = hsp - fbi->var.xres;
475 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
476 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
477 fbi->var.lower_margin = vsp - fbi->var.yres;
478 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
479 } else if (mode) {
480 dev_dbg(par->dev, "using supplied mode\n");
481 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
482 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
483 } else {
484 int ret;
485
486 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
487 NULL, 0, NULL, 16);
488 if (ret == 0 || ret == 4) {
489 dev_err(par->dev,
490 "failed to get initial mode\n");
491 return -EINVAL;
492 }
493 }
494
495 fbi->var.xoffset = 0;
496 fbi->var.yoffset = 0;
497 fbi->var.grayscale = 0;
498 fbi->var.nonstd = 0;
499 fbi->var.height = -1;
500 fbi->var.width = -1;
501 fbi->var.accel_flags = 0;
502 fbi->var.vmode = FB_VMODE_NONINTERLACED;
503 fbi->var.activate = FB_ACTIVATE_NOW;
504 fbi->flags = FBINFO_DEFAULT |
505 #ifdef __BIG_ENDIAN
506 FBINFO_FOREIGN_ENDIAN |
507 #endif
508 FBINFO_HWACCEL_XPAN |
509 FBINFO_HWACCEL_YPAN;
510
511 /* check and possibly fix bpp */
512 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
513 dev_err(par->dev, "check_var() failed on initial setup?\n");
514
515 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
516 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
517 fbi->fix.line_length = (fbi->var.xres_virtual *
518 fbi->var.bits_per_pixel) / 8;
519 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
520
521 /*
522 * reserve space for capture buffers and two cursors
523 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
524 */
525 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
526 par->cap_len = 0x1bd800;
527 par->l1_cfg.sx = 0;
528 par->l1_cfg.sy = 0;
529 par->l1_cfg.sw = 720;
530 par->l1_cfg.sh = 576;
531 par->l1_cfg.dx = 0;
532 par->l1_cfg.dy = 0;
533 par->l1_cfg.dw = 720;
534 par->l1_cfg.dh = 576;
535 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
536 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
537 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
538 (par->l1_stride << 16));
539 outreg(cap, GC_CAP_CBOA, par->cap_buf);
540 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
541 return 0;
542 }
543
544 /*
545 * show some display controller and cursor registers
546 */
dispregs_show(struct device * dev,struct device_attribute * attr,char * buf)547 static ssize_t dispregs_show(struct device *dev,
548 struct device_attribute *attr, char *buf)
549 {
550 struct fb_info *fbi = dev_get_drvdata(dev);
551 struct mb862xxfb_par *par = fbi->par;
552 char *ptr = buf;
553 unsigned int reg;
554
555 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
556 ptr += sprintf(ptr, "%08x = %08x\n",
557 reg, inreg(disp, reg));
558
559 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
560 ptr += sprintf(ptr, "%08x = %08x\n",
561 reg, inreg(disp, reg));
562
563 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
564 ptr += sprintf(ptr, "%08x = %08x\n",
565 reg, inreg(disp, reg));
566
567 for (reg = 0x400; reg <= 0x410; reg += 4)
568 ptr += sprintf(ptr, "geo %08x = %08x\n",
569 reg, inreg(geo, reg));
570
571 for (reg = 0x400; reg <= 0x410; reg += 4)
572 ptr += sprintf(ptr, "draw %08x = %08x\n",
573 reg, inreg(draw, reg));
574
575 for (reg = 0x440; reg <= 0x450; reg += 4)
576 ptr += sprintf(ptr, "draw %08x = %08x\n",
577 reg, inreg(draw, reg));
578
579 return ptr - buf;
580 }
581
582 static DEVICE_ATTR_RO(dispregs);
583
mb862xx_intr(int irq,void * dev_id)584 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
585 {
586 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
587 unsigned long reg_ist, mask;
588
589 if (!par)
590 return IRQ_NONE;
591
592 if (par->type == BT_CARMINE) {
593 /* Get Interrupt Status */
594 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
595 mask = inreg(ctrl, GC_CTRL_INT_MASK);
596 if (reg_ist == 0)
597 return IRQ_HANDLED;
598
599 reg_ist &= mask;
600 if (reg_ist == 0)
601 return IRQ_HANDLED;
602
603 /* Clear interrupt status */
604 outreg(ctrl, 0x0, reg_ist);
605 } else {
606 /* Get status */
607 reg_ist = inreg(host, GC_IST);
608 mask = inreg(host, GC_IMASK);
609
610 reg_ist &= mask;
611 if (reg_ist == 0)
612 return IRQ_HANDLED;
613
614 /* Clear status */
615 outreg(host, GC_IST, ~reg_ist);
616 }
617 return IRQ_HANDLED;
618 }
619
620 #if defined(CONFIG_FB_MB862XX_LIME)
621 /*
622 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
623 */
mb862xx_gdc_init(struct mb862xxfb_par * par)624 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
625 {
626 unsigned long ccf, mmr;
627 unsigned long ver, rev;
628
629 if (!par)
630 return -ENODEV;
631
632 #if defined(CONFIG_FB_PRE_INIT_FB)
633 par->pre_init = 1;
634 #endif
635 par->host = par->mmio_base;
636 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
637 par->disp = par->mmio_base + MB862XX_DISP_BASE;
638 par->cap = par->mmio_base + MB862XX_CAP_BASE;
639 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
640 par->geo = par->mmio_base + MB862XX_GEO_BASE;
641 par->pio = par->mmio_base + MB862XX_PIO_BASE;
642
643 par->refclk = GC_DISP_REFCLK_400;
644
645 ver = inreg(host, GC_CID);
646 rev = inreg(pio, GC_REVISION);
647 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
648 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
649 (int)rev & 0xff);
650 par->type = BT_LIME;
651 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
652 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
653 } else {
654 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
655 return -ENODEV;
656 }
657
658 if (!par->pre_init) {
659 outreg(host, GC_CCF, ccf);
660 udelay(200);
661 outreg(host, GC_MMR, mmr);
662 udelay(10);
663 }
664
665 /* interrupt status */
666 outreg(host, GC_IST, 0);
667 outreg(host, GC_IMASK, GC_INT_EN);
668 return 0;
669 }
670
of_platform_mb862xx_probe(struct platform_device * ofdev)671 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
672 {
673 struct device_node *np = ofdev->dev.of_node;
674 struct device *dev = &ofdev->dev;
675 struct mb862xxfb_par *par;
676 struct fb_info *info;
677 struct resource res;
678 resource_size_t res_size;
679 unsigned long ret = -ENODEV;
680
681 if (of_address_to_resource(np, 0, &res)) {
682 dev_err(dev, "Invalid address\n");
683 return -ENXIO;
684 }
685
686 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
687 if (!info)
688 return -ENOMEM;
689
690 par = info->par;
691 par->info = info;
692 par->dev = dev;
693
694 par->irq = irq_of_parse_and_map(np, 0);
695 if (par->irq == NO_IRQ) {
696 dev_err(dev, "failed to map irq\n");
697 ret = -ENODEV;
698 goto fbrel;
699 }
700
701 res_size = resource_size(&res);
702 par->res = request_mem_region(res.start, res_size, DRV_NAME);
703 if (par->res == NULL) {
704 dev_err(dev, "Cannot claim framebuffer/mmio\n");
705 ret = -ENXIO;
706 goto irqdisp;
707 }
708
709 #if defined(CONFIG_SOCRATES)
710 par->gc_mode = &socrates_gc_mode;
711 #endif
712
713 par->fb_base_phys = res.start;
714 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
715 par->mmio_len = MB862XX_MMIO_SIZE;
716 if (par->gc_mode)
717 par->mapped_vram = par->gc_mode->max_vram;
718 else
719 par->mapped_vram = MB862XX_MEM_SIZE;
720
721 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
722 if (par->fb_base == NULL) {
723 dev_err(dev, "Cannot map framebuffer\n");
724 goto rel_reg;
725 }
726
727 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
728 if (par->mmio_base == NULL) {
729 dev_err(dev, "Cannot map registers\n");
730 goto fb_unmap;
731 }
732
733 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
734 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
735 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
736 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
737
738 if (mb862xx_gdc_init(par))
739 goto io_unmap;
740
741 if (request_irq(par->irq, mb862xx_intr, 0,
742 DRV_NAME, (void *)par)) {
743 dev_err(dev, "Cannot request irq\n");
744 goto io_unmap;
745 }
746
747 mb862xxfb_init_fbinfo(info);
748
749 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
750 dev_err(dev, "Could not allocate cmap for fb_info.\n");
751 goto free_irq;
752 }
753
754 if ((info->fbops->fb_set_par)(info))
755 dev_err(dev, "set_var() failed on initial setup?\n");
756
757 if (register_framebuffer(info)) {
758 dev_err(dev, "failed to register framebuffer\n");
759 goto rel_cmap;
760 }
761
762 dev_set_drvdata(dev, info);
763
764 if (device_create_file(dev, &dev_attr_dispregs))
765 dev_err(dev, "Can't create sysfs regdump file\n");
766 return 0;
767
768 rel_cmap:
769 fb_dealloc_cmap(&info->cmap);
770 free_irq:
771 outreg(host, GC_IMASK, 0);
772 free_irq(par->irq, (void *)par);
773 io_unmap:
774 iounmap(par->mmio_base);
775 fb_unmap:
776 iounmap(par->fb_base);
777 rel_reg:
778 release_mem_region(res.start, res_size);
779 irqdisp:
780 irq_dispose_mapping(par->irq);
781 fbrel:
782 framebuffer_release(info);
783 return ret;
784 }
785
of_platform_mb862xx_remove(struct platform_device * ofdev)786 static int of_platform_mb862xx_remove(struct platform_device *ofdev)
787 {
788 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
789 struct mb862xxfb_par *par = fbi->par;
790 resource_size_t res_size = resource_size(par->res);
791 unsigned long reg;
792
793 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
794
795 /* display off */
796 reg = inreg(disp, GC_DCM1);
797 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
798 outreg(disp, GC_DCM1, reg);
799
800 /* disable interrupts */
801 outreg(host, GC_IMASK, 0);
802
803 free_irq(par->irq, (void *)par);
804 irq_dispose_mapping(par->irq);
805
806 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
807
808 unregister_framebuffer(fbi);
809 fb_dealloc_cmap(&fbi->cmap);
810
811 iounmap(par->mmio_base);
812 iounmap(par->fb_base);
813
814 release_mem_region(par->res->start, res_size);
815 framebuffer_release(fbi);
816 return 0;
817 }
818
819 /*
820 * common types
821 */
822 static struct of_device_id of_platform_mb862xx_tbl[] = {
823 { .compatible = "fujitsu,MB86276", },
824 { .compatible = "fujitsu,lime", },
825 { .compatible = "fujitsu,MB86277", },
826 { .compatible = "fujitsu,mint", },
827 { .compatible = "fujitsu,MB86293", },
828 { .compatible = "fujitsu,MB86294", },
829 { .compatible = "fujitsu,coral", },
830 { /* end */ }
831 };
832 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
833
834 static struct platform_driver of_platform_mb862xxfb_driver = {
835 .driver = {
836 .name = DRV_NAME,
837 .of_match_table = of_platform_mb862xx_tbl,
838 },
839 .probe = of_platform_mb862xx_probe,
840 .remove = of_platform_mb862xx_remove,
841 };
842 #endif
843
844 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
coralp_init(struct mb862xxfb_par * par)845 static int coralp_init(struct mb862xxfb_par *par)
846 {
847 int cn, ver;
848
849 par->host = par->mmio_base;
850 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
851 par->disp = par->mmio_base + MB862XX_DISP_BASE;
852 par->cap = par->mmio_base + MB862XX_CAP_BASE;
853 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
854 par->geo = par->mmio_base + MB862XX_GEO_BASE;
855 par->pio = par->mmio_base + MB862XX_PIO_BASE;
856
857 par->refclk = GC_DISP_REFCLK_400;
858
859 if (par->mapped_vram >= 0x2000000) {
860 /* relocate gdc registers space */
861 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
862 udelay(1); /* wait at least 20 bus cycles */
863 }
864
865 ver = inreg(host, GC_CID);
866 cn = (ver & GC_CID_CNAME_MSK) >> 8;
867 ver = ver & GC_CID_VERSION_MSK;
868 if (cn == 3) {
869 unsigned long reg;
870
871 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
872 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
873 par->pdev->revision);
874 reg = inreg(disp, GC_DCM1);
875 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
876 par->pre_init = 1;
877
878 if (!par->pre_init) {
879 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
880 udelay(200);
881 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
882 udelay(10);
883 }
884 /* Clear interrupt status */
885 outreg(host, GC_IST, 0);
886 } else {
887 return -ENODEV;
888 }
889
890 mb862xx_i2c_init(par);
891 return 0;
892 }
893
init_dram_ctrl(struct mb862xxfb_par * par)894 static int init_dram_ctrl(struct mb862xxfb_par *par)
895 {
896 unsigned long i = 0;
897
898 /*
899 * Set io mode first! Spec. says IC may be destroyed
900 * if not set to SSTL2/LVCMOS before init.
901 */
902 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
903
904 /* DRAM init */
905 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
906 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
907 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
908 GC_EVB_DCTL_REFRESH_SETTIME2);
909 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
910 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
911 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
912
913 /* DLL reset done? */
914 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
915 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
916 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
917 dev_err(par->dev, "VRAM init failed.\n");
918 return -EINVAL;
919 }
920 }
921 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
922 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
923 return 0;
924 }
925
carmine_init(struct mb862xxfb_par * par)926 static int carmine_init(struct mb862xxfb_par *par)
927 {
928 unsigned long reg;
929
930 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
931 par->i2c = par->mmio_base + MB86297_I2C_BASE;
932 par->disp = par->mmio_base + MB86297_DISP0_BASE;
933 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
934 par->cap = par->mmio_base + MB86297_CAP0_BASE;
935 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
936 par->draw = par->mmio_base + MB86297_DRAW_BASE;
937 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
938 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
939
940 par->refclk = GC_DISP_REFCLK_533;
941
942 /* warm up */
943 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
944 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
945
946 /* check for engine module revision */
947 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
948 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
949 par->pdev->revision);
950 else
951 goto err_init;
952
953 reg &= ~GC_CTRL_CLK_EN_2D3D;
954 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
955
956 /* set up vram */
957 if (init_dram_ctrl(par) < 0)
958 goto err_init;
959
960 outreg(ctrl, GC_CTRL_INT_MASK, 0);
961 return 0;
962
963 err_init:
964 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
965 return -EINVAL;
966 }
967
mb862xx_pci_gdc_init(struct mb862xxfb_par * par)968 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
969 {
970 switch (par->type) {
971 case BT_CORALP:
972 return coralp_init(par);
973 case BT_CARMINE:
974 return carmine_init(par);
975 default:
976 return -ENODEV;
977 }
978 }
979
980 #define CHIP_ID(id) \
981 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
982
983 static const struct pci_device_id mb862xx_pci_tbl[] = {
984 /* MB86295/MB86296 */
985 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
986 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
987 /* MB86297 */
988 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
989 { 0, }
990 };
991
992 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
993
mb862xx_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)994 static int mb862xx_pci_probe(struct pci_dev *pdev,
995 const struct pci_device_id *ent)
996 {
997 struct mb862xxfb_par *par;
998 struct fb_info *info;
999 struct device *dev = &pdev->dev;
1000 int ret;
1001
1002 ret = pci_enable_device(pdev);
1003 if (ret < 0) {
1004 dev_err(dev, "Cannot enable PCI device\n");
1005 goto out;
1006 }
1007
1008 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1009 if (!info) {
1010 ret = -ENOMEM;
1011 goto dis_dev;
1012 }
1013
1014 par = info->par;
1015 par->info = info;
1016 par->dev = dev;
1017 par->pdev = pdev;
1018 par->irq = pdev->irq;
1019
1020 ret = pci_request_regions(pdev, DRV_NAME);
1021 if (ret < 0) {
1022 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1023 goto rel_fb;
1024 }
1025
1026 switch (pdev->device) {
1027 case PCI_DEVICE_ID_FUJITSU_CORALP:
1028 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1029 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1030 par->mapped_vram = CORALP_MEM_SIZE;
1031 if (par->mapped_vram >= 0x2000000) {
1032 par->mmio_base_phys = par->fb_base_phys +
1033 MB862XX_MMIO_HIGH_BASE;
1034 } else {
1035 par->mmio_base_phys = par->fb_base_phys +
1036 MB862XX_MMIO_BASE;
1037 }
1038 par->mmio_len = MB862XX_MMIO_SIZE;
1039 par->type = BT_CORALP;
1040 break;
1041 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1042 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1043 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1044 par->mmio_len = pci_resource_len(par->pdev, 3);
1045 par->mapped_vram = CARMINE_MEM_SIZE;
1046 par->type = BT_CARMINE;
1047 break;
1048 default:
1049 /* should never occur */
1050 ret = -EIO;
1051 goto rel_reg;
1052 }
1053
1054 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1055 if (par->fb_base == NULL) {
1056 dev_err(dev, "Cannot map framebuffer\n");
1057 ret = -EIO;
1058 goto rel_reg;
1059 }
1060
1061 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1062 if (par->mmio_base == NULL) {
1063 dev_err(dev, "Cannot map registers\n");
1064 ret = -EIO;
1065 goto fb_unmap;
1066 }
1067
1068 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1069 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1070 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1071 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1072
1073 ret = mb862xx_pci_gdc_init(par);
1074 if (ret)
1075 goto io_unmap;
1076
1077 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1078 DRV_NAME, (void *)par);
1079 if (ret) {
1080 dev_err(dev, "Cannot request irq\n");
1081 goto io_unmap;
1082 }
1083
1084 mb862xxfb_init_fbinfo(info);
1085
1086 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1087 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1088 ret = -ENOMEM;
1089 goto free_irq;
1090 }
1091
1092 if ((info->fbops->fb_set_par)(info))
1093 dev_err(dev, "set_var() failed on initial setup?\n");
1094
1095 ret = register_framebuffer(info);
1096 if (ret < 0) {
1097 dev_err(dev, "failed to register framebuffer\n");
1098 goto rel_cmap;
1099 }
1100
1101 pci_set_drvdata(pdev, info);
1102
1103 if (device_create_file(dev, &dev_attr_dispregs))
1104 dev_err(dev, "Can't create sysfs regdump file\n");
1105
1106 if (par->type == BT_CARMINE)
1107 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1108 else
1109 outreg(host, GC_IMASK, GC_INT_EN);
1110
1111 return 0;
1112
1113 rel_cmap:
1114 fb_dealloc_cmap(&info->cmap);
1115 free_irq:
1116 free_irq(par->irq, (void *)par);
1117 io_unmap:
1118 iounmap(par->mmio_base);
1119 fb_unmap:
1120 iounmap(par->fb_base);
1121 rel_reg:
1122 pci_release_regions(pdev);
1123 rel_fb:
1124 framebuffer_release(info);
1125 dis_dev:
1126 pci_disable_device(pdev);
1127 out:
1128 return ret;
1129 }
1130
mb862xx_pci_remove(struct pci_dev * pdev)1131 static void mb862xx_pci_remove(struct pci_dev *pdev)
1132 {
1133 struct fb_info *fbi = pci_get_drvdata(pdev);
1134 struct mb862xxfb_par *par = fbi->par;
1135 unsigned long reg;
1136
1137 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1138
1139 /* display off */
1140 reg = inreg(disp, GC_DCM1);
1141 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1142 outreg(disp, GC_DCM1, reg);
1143
1144 if (par->type == BT_CARMINE) {
1145 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1146 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1147 } else {
1148 outreg(host, GC_IMASK, 0);
1149 }
1150
1151 mb862xx_i2c_exit(par);
1152
1153 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1154
1155 unregister_framebuffer(fbi);
1156 fb_dealloc_cmap(&fbi->cmap);
1157
1158 free_irq(par->irq, (void *)par);
1159 iounmap(par->mmio_base);
1160 iounmap(par->fb_base);
1161
1162 pci_release_regions(pdev);
1163 framebuffer_release(fbi);
1164 pci_disable_device(pdev);
1165 }
1166
1167 static struct pci_driver mb862xxfb_pci_driver = {
1168 .name = DRV_NAME,
1169 .id_table = mb862xx_pci_tbl,
1170 .probe = mb862xx_pci_probe,
1171 .remove = mb862xx_pci_remove,
1172 };
1173 #endif
1174
mb862xxfb_init(void)1175 static int mb862xxfb_init(void)
1176 {
1177 int ret = -ENODEV;
1178
1179 #if defined(CONFIG_FB_MB862XX_LIME)
1180 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1181 #endif
1182 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1183 ret = pci_register_driver(&mb862xxfb_pci_driver);
1184 #endif
1185 return ret;
1186 }
1187
mb862xxfb_exit(void)1188 static void __exit mb862xxfb_exit(void)
1189 {
1190 #if defined(CONFIG_FB_MB862XX_LIME)
1191 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1192 #endif
1193 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1194 pci_unregister_driver(&mb862xxfb_pci_driver);
1195 #endif
1196 }
1197
1198 module_init(mb862xxfb_init);
1199 module_exit(mb862xxfb_exit);
1200
1201 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1202 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1203 MODULE_LICENSE("GPL v2");
1204