1 /*
2  * drivers/video/asiliantfb.c
3  *  frame buffer driver for Asiliant 69000 chip
4  *  Copyright (C) 2001-2003 Saito.K & Jeanne
5  *
6  *  from driver/video/chipsfb.c and,
7  *
8  *  drivers/video/asiliantfb.c -- frame buffer device for
9  *  Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
10  *  Author: apc@agelectronics.co.uk
11  *  Copyright (C) 2000 AG Electronics
12  *  Note: the data sheets don't seem to be available from Asiliant.
13  *  They are available by searching developer.intel.com, but are not otherwise
14  *  linked to.
15  *
16  *  This driver should be portable with minimal effort to the 69000 display
17  *  chip, and to the twin-display mode of the 69030.
18  *  Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
19  *
20  *  Derived from the CT65550 driver chipsfb.c:
21  *  Copyright (C) 1998 Paul Mackerras
22  *  ...which was derived from the Powermac "chips" driver:
23  *  Copyright (C) 1997 Fabio Riccardi.
24  *  And from the frame buffer device for Open Firmware-initialized devices:
25  *  Copyright (C) 1997 Geert Uytterhoeven.
26  *
27  *  This file is subject to the terms and conditions of the GNU General Public
28  *  License. See the file COPYING in the main directory of this archive for
29  *  more details.
30  */
31 
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/fb.h>
41 #include <linux/init.h>
42 #include <linux/pci.h>
43 #include <asm/io.h>
44 
45 /* Built in clock of the 69030 */
46 static const unsigned Fref = 14318180;
47 
48 #define mmio_base (p->screen_base + 0x400000)
49 
50 #define mm_write_ind(num, val, ap, dp)	do { \
51 	writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
52 } while (0)
53 
mm_write_xr(struct fb_info * p,u8 reg,u8 data)54 static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
55 {
56 	mm_write_ind(reg, data, 0x7ac, 0x7ad);
57 }
58 #define write_xr(num, val)	mm_write_xr(p, num, val)
59 
mm_write_fr(struct fb_info * p,u8 reg,u8 data)60 static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
61 {
62 	mm_write_ind(reg, data, 0x7a0, 0x7a1);
63 }
64 #define write_fr(num, val)	mm_write_fr(p, num, val)
65 
mm_write_cr(struct fb_info * p,u8 reg,u8 data)66 static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
67 {
68 	mm_write_ind(reg, data, 0x7a8, 0x7a9);
69 }
70 #define write_cr(num, val)	mm_write_cr(p, num, val)
71 
mm_write_gr(struct fb_info * p,u8 reg,u8 data)72 static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
73 {
74 	mm_write_ind(reg, data, 0x79c, 0x79d);
75 }
76 #define write_gr(num, val)	mm_write_gr(p, num, val)
77 
mm_write_sr(struct fb_info * p,u8 reg,u8 data)78 static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
79 {
80 	mm_write_ind(reg, data, 0x788, 0x789);
81 }
82 #define write_sr(num, val)	mm_write_sr(p, num, val)
83 
mm_write_ar(struct fb_info * p,u8 reg,u8 data)84 static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
85 {
86 	readb(mmio_base + 0x7b4);
87 	mm_write_ind(reg, data, 0x780, 0x780);
88 }
89 #define write_ar(num, val)	mm_write_ar(p, num, val)
90 
91 static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
92 static int asiliantfb_check_var(struct fb_var_screeninfo *var,
93 				struct fb_info *info);
94 static int asiliantfb_set_par(struct fb_info *info);
95 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
96 				u_int transp, struct fb_info *info);
97 
98 static const struct fb_ops asiliantfb_ops = {
99 	.owner		= THIS_MODULE,
100 	.fb_check_var	= asiliantfb_check_var,
101 	.fb_set_par	= asiliantfb_set_par,
102 	.fb_setcolreg	= asiliantfb_setcolreg,
103 	.fb_fillrect	= cfb_fillrect,
104 	.fb_copyarea	= cfb_copyarea,
105 	.fb_imageblit	= cfb_imageblit,
106 };
107 
108 /* Calculate the ratios for the dot clocks without using a single long long
109  * value */
asiliant_calc_dclk2(u32 * ppixclock,u8 * dclk2_m,u8 * dclk2_n,u8 * dclk2_div)110 static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
111 {
112 	unsigned pixclock = *ppixclock;
113 	unsigned Ftarget;
114 	unsigned n;
115 	unsigned best_error = 0xffffffff;
116 	unsigned best_m = 0xffffffff,
117 	         best_n = 0xffffffff;
118 	unsigned ratio;
119 	unsigned remainder;
120 	unsigned char divisor = 0;
121 
122 	/* Calculate the frequency required. This is hard enough. */
123 	ratio = 1000000 / pixclock;
124 	remainder = 1000000 % pixclock;
125 	Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
126 
127 	while (Ftarget < 100000000) {
128 		divisor += 0x10;
129 		Ftarget <<= 1;
130 	}
131 
132 	ratio = Ftarget / Fref;
133 	remainder = Ftarget % Fref;
134 
135 	/* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
136 	 * together with 3 <= n <= 257. */
137 	for (n = 3; n <= 257; n++) {
138 		unsigned m = n * ratio + (n * remainder) / Fref;
139 
140 		/* 3 <= m <= 257 */
141 		if (m >= 3 && m <= 257) {
142 			unsigned new_error = Ftarget * n >= Fref * m ?
143 					       ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
144 			if (new_error < best_error) {
145 				best_n = n;
146 				best_m = m;
147 				best_error = new_error;
148 			}
149 		}
150 		/* But if VLD = 4, then 4m <= 1028 */
151 		else if (m <= 1028) {
152 			/* remember there are still only 8-bits of precision in m, so
153 			 * avoid over-optimistic error calculations */
154 			unsigned new_error = Ftarget * n >= Fref * (m & ~3) ?
155 					       ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
156 			if (new_error < best_error) {
157 				best_n = n;
158 				best_m = m;
159 				best_error = new_error;
160 			}
161 		}
162 	}
163 	if (best_m > 257)
164 		best_m >>= 2;	/* divide m by 4, and leave VCO loop divide at 4 */
165 	else
166 		divisor |= 4;	/* or set VCO loop divide to 1 */
167 	*dclk2_m = best_m - 2;
168 	*dclk2_n = best_n - 2;
169 	*dclk2_div = divisor;
170 	*ppixclock = pixclock;
171 	return;
172 }
173 
asiliant_set_timing(struct fb_info * p)174 static void asiliant_set_timing(struct fb_info *p)
175 {
176 	unsigned hd = p->var.xres / 8;
177 	unsigned hs = (p->var.xres + p->var.right_margin) / 8;
178        	unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
179 	unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
180 	unsigned vd = p->var.yres;
181 	unsigned vs = p->var.yres + p->var.lower_margin;
182 	unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
183 	unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
184 	unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
185 
186 	if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
187 	  write_fr(0x01, 0x02);  /* LCD */
188 	} else {
189 	  write_fr(0x01, 0x01);  /* CRT */
190 	}
191 
192 	write_cr(0x11, (ve - 1) & 0x0f);
193 	write_cr(0x00, (ht - 5) & 0xff);
194 	write_cr(0x01, hd - 1);
195 	write_cr(0x02, hd);
196 	write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
197 	write_cr(0x04, hs);
198 	write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
199 	write_cr(0x3c, (ht - 1) & 0xc0);
200 	write_cr(0x06, (vt - 2) & 0xff);
201 	write_cr(0x30, (vt - 2) >> 8);
202 	write_cr(0x07, 0x00);
203 	write_cr(0x08, 0x00);
204 	write_cr(0x09, 0x00);
205 	write_cr(0x10, (vs - 1) & 0xff);
206 	write_cr(0x32, ((vs - 1) >> 8) & 0xf);
207 	write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
208 	write_cr(0x12, (vd - 1) & 0xff);
209 	write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
210 	write_cr(0x13, wd & 0xff);
211 	write_cr(0x41, (wd & 0xf00) >> 8);
212 	write_cr(0x15, (vs - 1) & 0xff);
213 	write_cr(0x33, ((vs - 1) >> 8) & 0xf);
214 	write_cr(0x38, ((ht - 5) & 0x100) >> 8);
215 	write_cr(0x16, (vt - 1) & 0xff);
216 	write_cr(0x18, 0x00);
217 
218 	if (p->var.xres == 640) {
219 	  writeb(0xc7, mmio_base + 0x784);	/* set misc output reg */
220 	} else {
221 	  writeb(0x07, mmio_base + 0x784);	/* set misc output reg */
222 	}
223 }
224 
asiliantfb_check_var(struct fb_var_screeninfo * var,struct fb_info * p)225 static int asiliantfb_check_var(struct fb_var_screeninfo *var,
226 			     struct fb_info *p)
227 {
228 	unsigned long Ftarget, ratio, remainder;
229 
230 	if (!var->pixclock)
231 		return -EINVAL;
232 
233 	ratio = 1000000 / var->pixclock;
234 	remainder = 1000000 % var->pixclock;
235 	Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
236 
237 	/* First check the constraint that the maximum post-VCO divisor is 32,
238 	 * and the maximum Fvco is 220MHz */
239 	if (Ftarget > 220000000 || Ftarget < 3125000) {
240 		printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
241 		return -ENXIO;
242 	}
243 	var->xres_virtual = var->xres;
244 	var->yres_virtual = var->yres;
245 
246 	if (var->bits_per_pixel == 24) {
247 		var->red.offset = 16;
248 		var->green.offset = 8;
249 		var->blue.offset = 0;
250 		var->red.length = var->blue.length = var->green.length = 8;
251 	} else if (var->bits_per_pixel == 16) {
252 		switch (var->red.offset) {
253 			case 11:
254 				var->green.length = 6;
255 				break;
256 			case 10:
257 				var->green.length = 5;
258 				break;
259 			default:
260 				return -EINVAL;
261 		}
262 		var->green.offset = 5;
263 		var->blue.offset = 0;
264 		var->red.length = var->blue.length = 5;
265 	} else if (var->bits_per_pixel == 8) {
266 		var->red.offset = var->green.offset = var->blue.offset = 0;
267 		var->red.length = var->green.length = var->blue.length = 8;
268 	}
269 	return 0;
270 }
271 
asiliantfb_set_par(struct fb_info * p)272 static int asiliantfb_set_par(struct fb_info *p)
273 {
274 	u8 dclk2_m;		/* Holds m-2 value for register */
275 	u8 dclk2_n;		/* Holds n-2 value for register */
276 	u8 dclk2_div;		/* Holds divisor bitmask */
277 
278 	/* Set pixclock */
279 	asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
280 
281 	/* Set color depth */
282 	if (p->var.bits_per_pixel == 24) {
283 		write_xr(0x81, 0x16);	/* 24 bit packed color mode */
284 		write_xr(0x82, 0x00);	/* Disable palettes */
285 		write_xr(0x20, 0x20);	/* 24 bit blitter mode */
286 	} else if (p->var.bits_per_pixel == 16) {
287 		if (p->var.red.offset == 11)
288 			write_xr(0x81, 0x15);	/* 16 bit color mode */
289 		else
290 			write_xr(0x81, 0x14);	/* 15 bit color mode */
291 		write_xr(0x82, 0x00);	/* Disable palettes */
292 		write_xr(0x20, 0x10);	/* 16 bit blitter mode */
293 	} else if (p->var.bits_per_pixel == 8) {
294 		write_xr(0x0a, 0x02);	/* Linear */
295 		write_xr(0x81, 0x12);	/* 8 bit color mode */
296 		write_xr(0x82, 0x00);	/* Graphics gamma enable */
297 		write_xr(0x20, 0x00);	/* 8 bit blitter mode */
298 	}
299 	p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
300 	p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
301 	write_xr(0xc4, dclk2_m);
302 	write_xr(0xc5, dclk2_n);
303 	write_xr(0xc7, dclk2_div);
304 	/* Set up the CR registers */
305 	asiliant_set_timing(p);
306 	return 0;
307 }
308 
asiliantfb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * p)309 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
310 			     u_int transp, struct fb_info *p)
311 {
312 	if (regno > 255)
313 		return 1;
314 	red >>= 8;
315 	green >>= 8;
316 	blue >>= 8;
317 
318         /* Set hardware palete */
319 	writeb(regno, mmio_base + 0x790);
320 	udelay(1);
321 	writeb(red, mmio_base + 0x791);
322 	writeb(green, mmio_base + 0x791);
323 	writeb(blue, mmio_base + 0x791);
324 
325 	if (regno < 16) {
326 		switch(p->var.red.offset) {
327 		case 10: /* RGB 555 */
328 			((u32 *)(p->pseudo_palette))[regno] =
329 				((red & 0xf8) << 7) |
330 				((green & 0xf8) << 2) |
331 				((blue & 0xf8) >> 3);
332 			break;
333 		case 11: /* RGB 565 */
334 			((u32 *)(p->pseudo_palette))[regno] =
335 				((red & 0xf8) << 8) |
336 				((green & 0xfc) << 3) |
337 				((blue & 0xf8) >> 3);
338 			break;
339 		case 16: /* RGB 888 */
340 			((u32 *)(p->pseudo_palette))[regno] =
341 				(red << 16)  |
342 				(green << 8) |
343 				(blue);
344 			break;
345 		}
346 	}
347 
348 	return 0;
349 }
350 
351 struct chips_init_reg {
352 	unsigned char addr;
353 	unsigned char data;
354 };
355 
356 static struct chips_init_reg chips_init_sr[] =
357 {
358 	{0x00, 0x03},		/* Reset register */
359 	{0x01, 0x01},		/* Clocking mode */
360 	{0x02, 0x0f},		/* Plane mask */
361 	{0x04, 0x0e}		/* Memory mode */
362 };
363 
364 static struct chips_init_reg chips_init_gr[] =
365 {
366         {0x03, 0x00},		/* Data rotate */
367 	{0x05, 0x00},		/* Graphics mode */
368 	{0x06, 0x01},		/* Miscellaneous */
369 	{0x08, 0x00}		/* Bit mask */
370 };
371 
372 static struct chips_init_reg chips_init_ar[] =
373 {
374 	{0x10, 0x01},		/* Mode control */
375 	{0x11, 0x00},		/* Overscan */
376 	{0x12, 0x0f},		/* Memory plane enable */
377 	{0x13, 0x00}		/* Horizontal pixel panning */
378 };
379 
380 static struct chips_init_reg chips_init_cr[] =
381 {
382 	{0x0c, 0x00},		/* Start address high */
383 	{0x0d, 0x00},		/* Start address low */
384 	{0x40, 0x00},		/* Extended Start Address */
385 	{0x41, 0x00},		/* Extended Start Address */
386 	{0x14, 0x00},		/* Underline location */
387 	{0x17, 0xe3},		/* CRT mode control */
388 	{0x70, 0x00}		/* Interlace control */
389 };
390 
391 
392 static struct chips_init_reg chips_init_fr[] =
393 {
394 	{0x01, 0x02},
395 	{0x03, 0x08},
396 	{0x08, 0xcc},
397 	{0x0a, 0x08},
398 	{0x18, 0x00},
399 	{0x1e, 0x80},
400 	{0x40, 0x83},
401 	{0x41, 0x00},
402 	{0x48, 0x13},
403 	{0x4d, 0x60},
404 	{0x4e, 0x0f},
405 
406 	{0x0b, 0x01},
407 
408 	{0x21, 0x51},
409 	{0x22, 0x1d},
410 	{0x23, 0x5f},
411 	{0x20, 0x4f},
412 	{0x34, 0x00},
413 	{0x24, 0x51},
414 	{0x25, 0x00},
415 	{0x27, 0x0b},
416 	{0x26, 0x00},
417 	{0x37, 0x80},
418 	{0x33, 0x0b},
419 	{0x35, 0x11},
420 	{0x36, 0x02},
421 	{0x31, 0xea},
422 	{0x32, 0x0c},
423 	{0x30, 0xdf},
424 	{0x10, 0x0c},
425 	{0x11, 0xe0},
426 	{0x12, 0x50},
427 	{0x13, 0x00},
428 	{0x16, 0x03},
429 	{0x17, 0xbd},
430 	{0x1a, 0x00},
431 };
432 
433 
434 static struct chips_init_reg chips_init_xr[] =
435 {
436 	{0xce, 0x00},		/* set default memory clock */
437 	{0xcc, 200 },	        /* MCLK ratio M */
438 	{0xcd, 18  },	        /* MCLK ratio N */
439 	{0xce, 0x90},		/* MCLK divisor = 2 */
440 
441 	{0xc4, 209 },
442 	{0xc5, 118 },
443 	{0xc7, 32  },
444 	{0xcf, 0x06},
445 	{0x09, 0x01},		/* IO Control - CRT controller extensions */
446 	{0x0a, 0x02},		/* Frame buffer mapping */
447 	{0x0b, 0x01},		/* PCI burst write */
448 	{0x40, 0x03},		/* Memory access control */
449 	{0x80, 0x82},		/* Pixel pipeline configuration 0 */
450 	{0x81, 0x12},		/* Pixel pipeline configuration 1 */
451 	{0x82, 0x08},		/* Pixel pipeline configuration 2 */
452 
453 	{0xd0, 0x0f},
454 	{0xd1, 0x01},
455 };
456 
chips_hw_init(struct fb_info * p)457 static void chips_hw_init(struct fb_info *p)
458 {
459 	int i;
460 
461 	for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
462 		write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
463 	write_xr(0x81, 0x12);
464 	write_xr(0x82, 0x08);
465 	write_xr(0x20, 0x00);
466 	for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
467 		write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
468 	for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
469 		write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
470 	for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
471 		write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
472 	/* Enable video output in attribute index register */
473 	writeb(0x20, mmio_base + 0x780);
474 	for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
475 		write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
476 	for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
477 		write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
478 }
479 
480 static const struct fb_fix_screeninfo asiliantfb_fix = {
481 	.id =		"Asiliant 69000",
482 	.type =		FB_TYPE_PACKED_PIXELS,
483 	.visual =	FB_VISUAL_PSEUDOCOLOR,
484 	.accel =	FB_ACCEL_NONE,
485 	.line_length =	640,
486 	.smem_len =	0x200000,	/* 2MB */
487 };
488 
489 static const struct fb_var_screeninfo asiliantfb_var = {
490 	.xres 		= 640,
491 	.yres 		= 480,
492 	.xres_virtual 	= 640,
493 	.yres_virtual 	= 480,
494 	.bits_per_pixel = 8,
495 	.red 		= { .length = 8 },
496 	.green 		= { .length = 8 },
497 	.blue 		= { .length = 8 },
498 	.height 	= -1,
499 	.width 		= -1,
500 	.vmode 		= FB_VMODE_NONINTERLACED,
501 	.pixclock 	= 39722,
502 	.left_margin 	= 48,
503 	.right_margin 	= 16,
504 	.upper_margin 	= 33,
505 	.lower_margin 	= 10,
506 	.hsync_len 	= 96,
507 	.vsync_len 	= 2,
508 };
509 
init_asiliant(struct fb_info * p,unsigned long addr)510 static int init_asiliant(struct fb_info *p, unsigned long addr)
511 {
512 	int err;
513 
514 	p->fix			= asiliantfb_fix;
515 	p->fix.smem_start	= addr;
516 	p->var			= asiliantfb_var;
517 	p->fbops		= &asiliantfb_ops;
518 	p->flags		= FBINFO_DEFAULT;
519 
520 	err = fb_alloc_cmap(&p->cmap, 256, 0);
521 	if (err) {
522 		printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n");
523 		return err;
524 	}
525 
526 	err = register_framebuffer(p);
527 	if (err < 0) {
528 		printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
529 		fb_dealloc_cmap(&p->cmap);
530 		return err;
531 	}
532 
533 	fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n",
534 		p->fix.smem_len / 1024);
535 
536 	writeb(0xff, mmio_base + 0x78c);
537 	chips_hw_init(p);
538 	return 0;
539 }
540 
asiliantfb_pci_init(struct pci_dev * dp,const struct pci_device_id * ent)541 static int asiliantfb_pci_init(struct pci_dev *dp,
542 			       const struct pci_device_id *ent)
543 {
544 	unsigned long addr, size;
545 	struct fb_info *p;
546 	int err;
547 
548 	if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
549 		return -ENODEV;
550 	addr = pci_resource_start(dp, 0);
551 	size = pci_resource_len(dp, 0);
552 	if (addr == 0)
553 		return -ENODEV;
554 	if (!request_mem_region(addr, size, "asiliantfb"))
555 		return -EBUSY;
556 
557 	p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
558 	if (!p)	{
559 		release_mem_region(addr, size);
560 		return -ENOMEM;
561 	}
562 	p->pseudo_palette = p->par;
563 	p->par = NULL;
564 
565 	p->screen_base = ioremap(addr, 0x800000);
566 	if (p->screen_base == NULL) {
567 		release_mem_region(addr, size);
568 		framebuffer_release(p);
569 		return -ENOMEM;
570 	}
571 
572 	pci_write_config_dword(dp, 4, 0x02800083);
573 	writeb(3, p->screen_base + 0x400784);
574 
575 	err = init_asiliant(p, addr);
576 	if (err) {
577 		iounmap(p->screen_base);
578 		release_mem_region(addr, size);
579 		framebuffer_release(p);
580 		return err;
581 	}
582 
583 	pci_set_drvdata(dp, p);
584 	return 0;
585 }
586 
asiliantfb_remove(struct pci_dev * dp)587 static void asiliantfb_remove(struct pci_dev *dp)
588 {
589 	struct fb_info *p = pci_get_drvdata(dp);
590 
591 	unregister_framebuffer(p);
592 	fb_dealloc_cmap(&p->cmap);
593 	iounmap(p->screen_base);
594 	release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
595 	framebuffer_release(p);
596 }
597 
598 static const struct pci_device_id asiliantfb_pci_tbl[] = {
599 	{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
600 	{ 0 }
601 };
602 
603 MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
604 
605 static struct pci_driver asiliantfb_driver = {
606 	.name =		"asiliantfb",
607 	.id_table =	asiliantfb_pci_tbl,
608 	.probe =	asiliantfb_pci_init,
609 	.remove =	asiliantfb_remove,
610 };
611 
asiliantfb_init(void)612 static int __init asiliantfb_init(void)
613 {
614 	if (fb_get_options("asiliantfb", NULL))
615 		return -ENODEV;
616 
617 	return pci_register_driver(&asiliantfb_driver);
618 }
619 
620 module_init(asiliantfb_init);
621 
asiliantfb_exit(void)622 static void __exit asiliantfb_exit(void)
623 {
624 	pci_unregister_driver(&asiliantfb_driver);
625 }
626 
627 MODULE_LICENSE("GPL");
628