1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 *
5 * Copyright (C) 2004 Infineon IFAP DC COM CPE
6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
7 * Copyright (C) 2007 John Crispin <john@phrozen.org>
8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/lantiq.h>
18 #include <linux/module.h>
19 #include <linux/of_platform.h>
20 #include <linux/serial.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/sysrq.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26
27 #define PORT_LTQ_ASC 111
28 #define MAXPORTS 2
29 #define UART_DUMMY_UER_RX 1
30 #define DRVNAME "lantiq,asc"
31 #ifdef __BIG_ENDIAN
32 #define LTQ_ASC_TBUF (0x0020 + 3)
33 #define LTQ_ASC_RBUF (0x0024 + 3)
34 #else
35 #define LTQ_ASC_TBUF 0x0020
36 #define LTQ_ASC_RBUF 0x0024
37 #endif
38 #define LTQ_ASC_FSTAT 0x0048
39 #define LTQ_ASC_WHBSTATE 0x0018
40 #define LTQ_ASC_STATE 0x0014
41 #define LTQ_ASC_IRNCR 0x00F8
42 #define LTQ_ASC_CLC 0x0000
43 #define LTQ_ASC_ID 0x0008
44 #define LTQ_ASC_PISEL 0x0004
45 #define LTQ_ASC_TXFCON 0x0044
46 #define LTQ_ASC_RXFCON 0x0040
47 #define LTQ_ASC_CON 0x0010
48 #define LTQ_ASC_BG 0x0050
49 #define LTQ_ASC_IRNREN 0x00F4
50
51 #define ASC_IRNREN_TX 0x1
52 #define ASC_IRNREN_RX 0x2
53 #define ASC_IRNREN_ERR 0x4
54 #define ASC_IRNREN_TX_BUF 0x8
55 #define ASC_IRNCR_TIR 0x1
56 #define ASC_IRNCR_RIR 0x2
57 #define ASC_IRNCR_EIR 0x4
58 #define ASC_IRNCR_MASK GENMASK(2, 0)
59
60 #define ASCOPT_CSIZE 0x3
61 #define TXFIFO_FL 1
62 #define RXFIFO_FL 1
63 #define ASCCLC_DISS 0x2
64 #define ASCCLC_RMCMASK 0x0000FF00
65 #define ASCCLC_RMCOFFSET 8
66 #define ASCCON_M_8ASYNC 0x0
67 #define ASCCON_M_7ASYNC 0x2
68 #define ASCCON_ODD 0x00000020
69 #define ASCCON_STP 0x00000080
70 #define ASCCON_BRS 0x00000100
71 #define ASCCON_FDE 0x00000200
72 #define ASCCON_R 0x00008000
73 #define ASCCON_FEN 0x00020000
74 #define ASCCON_ROEN 0x00080000
75 #define ASCCON_TOEN 0x00100000
76 #define ASCSTATE_PE 0x00010000
77 #define ASCSTATE_FE 0x00020000
78 #define ASCSTATE_ROE 0x00080000
79 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
80 #define ASCWHBSTATE_CLRREN 0x00000001
81 #define ASCWHBSTATE_SETREN 0x00000002
82 #define ASCWHBSTATE_CLRPE 0x00000004
83 #define ASCWHBSTATE_CLRFE 0x00000008
84 #define ASCWHBSTATE_CLRROE 0x00000020
85 #define ASCTXFCON_TXFEN 0x0001
86 #define ASCTXFCON_TXFFLU 0x0002
87 #define ASCTXFCON_TXFITLMASK 0x3F00
88 #define ASCTXFCON_TXFITLOFF 8
89 #define ASCRXFCON_RXFEN 0x0001
90 #define ASCRXFCON_RXFFLU 0x0002
91 #define ASCRXFCON_RXFITLMASK 0x3F00
92 #define ASCRXFCON_RXFITLOFF 8
93 #define ASCFSTAT_RXFFLMASK 0x003F
94 #define ASCFSTAT_TXFFLMASK 0x3F00
95 #define ASCFSTAT_TXFREEMASK 0x3F000000
96 #define ASCFSTAT_TXFREEOFF 24
97
98 static void lqasc_tx_chars(struct uart_port *port);
99 static struct ltq_uart_port *lqasc_port[MAXPORTS];
100 static struct uart_driver lqasc_reg;
101
102 struct ltq_soc_data {
103 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
104 int (*request_irq)(struct uart_port *port);
105 void (*free_irq)(struct uart_port *port);
106 };
107
108 struct ltq_uart_port {
109 struct uart_port port;
110 /* clock used to derive divider */
111 struct clk *freqclk;
112 /* clock gating of the ASC core */
113 struct clk *clk;
114 unsigned int tx_irq;
115 unsigned int rx_irq;
116 unsigned int err_irq;
117 unsigned int common_irq;
118 spinlock_t lock; /* exclusive access for multi core */
119
120 const struct ltq_soc_data *soc;
121 };
122
asc_update_bits(u32 clear,u32 set,void __iomem * reg)123 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
124 {
125 u32 tmp = __raw_readl(reg);
126
127 __raw_writel((tmp & ~clear) | set, reg);
128 }
129
130 static inline struct
to_ltq_uart_port(struct uart_port * port)131 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
132 {
133 return container_of(port, struct ltq_uart_port, port);
134 }
135
136 static void
lqasc_stop_tx(struct uart_port * port)137 lqasc_stop_tx(struct uart_port *port)
138 {
139 return;
140 }
141
142 static void
lqasc_start_tx(struct uart_port * port)143 lqasc_start_tx(struct uart_port *port)
144 {
145 unsigned long flags;
146 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
147
148 spin_lock_irqsave(<q_port->lock, flags);
149 lqasc_tx_chars(port);
150 spin_unlock_irqrestore(<q_port->lock, flags);
151 return;
152 }
153
154 static void
lqasc_stop_rx(struct uart_port * port)155 lqasc_stop_rx(struct uart_port *port)
156 {
157 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
158 }
159
160 static int
lqasc_rx_chars(struct uart_port * port)161 lqasc_rx_chars(struct uart_port *port)
162 {
163 struct tty_port *tport = &port->state->port;
164 unsigned int ch = 0, rsr = 0, fifocnt;
165
166 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
167 ASCFSTAT_RXFFLMASK;
168 while (fifocnt--) {
169 u8 flag = TTY_NORMAL;
170 ch = readb(port->membase + LTQ_ASC_RBUF);
171 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
172 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
173 tty_flip_buffer_push(tport);
174 port->icount.rx++;
175
176 /*
177 * Note that the error handling code is
178 * out of the main execution path
179 */
180 if (rsr & ASCSTATE_ANY) {
181 if (rsr & ASCSTATE_PE) {
182 port->icount.parity++;
183 asc_update_bits(0, ASCWHBSTATE_CLRPE,
184 port->membase + LTQ_ASC_WHBSTATE);
185 } else if (rsr & ASCSTATE_FE) {
186 port->icount.frame++;
187 asc_update_bits(0, ASCWHBSTATE_CLRFE,
188 port->membase + LTQ_ASC_WHBSTATE);
189 }
190 if (rsr & ASCSTATE_ROE) {
191 port->icount.overrun++;
192 asc_update_bits(0, ASCWHBSTATE_CLRROE,
193 port->membase + LTQ_ASC_WHBSTATE);
194 }
195
196 rsr &= port->read_status_mask;
197
198 if (rsr & ASCSTATE_PE)
199 flag = TTY_PARITY;
200 else if (rsr & ASCSTATE_FE)
201 flag = TTY_FRAME;
202 }
203
204 if ((rsr & port->ignore_status_mask) == 0)
205 tty_insert_flip_char(tport, ch, flag);
206
207 if (rsr & ASCSTATE_ROE)
208 /*
209 * Overrun is special, since it's reported
210 * immediately, and doesn't affect the current
211 * character
212 */
213 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
214 }
215
216 if (ch != 0)
217 tty_flip_buffer_push(tport);
218
219 return 0;
220 }
221
222 static void
lqasc_tx_chars(struct uart_port * port)223 lqasc_tx_chars(struct uart_port *port)
224 {
225 struct circ_buf *xmit = &port->state->xmit;
226 if (uart_tx_stopped(port)) {
227 lqasc_stop_tx(port);
228 return;
229 }
230
231 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
232 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
233 if (port->x_char) {
234 writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
235 port->icount.tx++;
236 port->x_char = 0;
237 continue;
238 }
239
240 if (uart_circ_empty(xmit))
241 break;
242
243 writeb(port->state->xmit.buf[port->state->xmit.tail],
244 port->membase + LTQ_ASC_TBUF);
245 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
246 port->icount.tx++;
247 }
248
249 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
250 uart_write_wakeup(port);
251 }
252
253 static irqreturn_t
lqasc_tx_int(int irq,void * _port)254 lqasc_tx_int(int irq, void *_port)
255 {
256 unsigned long flags;
257 struct uart_port *port = (struct uart_port *)_port;
258 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
259
260 spin_lock_irqsave(<q_port->lock, flags);
261 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
262 spin_unlock_irqrestore(<q_port->lock, flags);
263 lqasc_start_tx(port);
264 return IRQ_HANDLED;
265 }
266
267 static irqreturn_t
lqasc_err_int(int irq,void * _port)268 lqasc_err_int(int irq, void *_port)
269 {
270 unsigned long flags;
271 struct uart_port *port = (struct uart_port *)_port;
272 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
273
274 spin_lock_irqsave(<q_port->lock, flags);
275 /* clear any pending interrupts */
276 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
277 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
278 spin_unlock_irqrestore(<q_port->lock, flags);
279 return IRQ_HANDLED;
280 }
281
282 static irqreturn_t
lqasc_rx_int(int irq,void * _port)283 lqasc_rx_int(int irq, void *_port)
284 {
285 unsigned long flags;
286 struct uart_port *port = (struct uart_port *)_port;
287 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
288
289 spin_lock_irqsave(<q_port->lock, flags);
290 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
291 lqasc_rx_chars(port);
292 spin_unlock_irqrestore(<q_port->lock, flags);
293 return IRQ_HANDLED;
294 }
295
lqasc_irq(int irq,void * p)296 static irqreturn_t lqasc_irq(int irq, void *p)
297 {
298 unsigned long flags;
299 u32 stat;
300 struct uart_port *port = p;
301 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
302
303 spin_lock_irqsave(<q_port->lock, flags);
304 stat = readl(port->membase + LTQ_ASC_IRNCR);
305 spin_unlock_irqrestore(<q_port->lock, flags);
306 if (!(stat & ASC_IRNCR_MASK))
307 return IRQ_NONE;
308
309 if (stat & ASC_IRNCR_TIR)
310 lqasc_tx_int(irq, p);
311
312 if (stat & ASC_IRNCR_RIR)
313 lqasc_rx_int(irq, p);
314
315 if (stat & ASC_IRNCR_EIR)
316 lqasc_err_int(irq, p);
317
318 return IRQ_HANDLED;
319 }
320
321 static unsigned int
lqasc_tx_empty(struct uart_port * port)322 lqasc_tx_empty(struct uart_port *port)
323 {
324 int status;
325 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
326 ASCFSTAT_TXFFLMASK;
327 return status ? 0 : TIOCSER_TEMT;
328 }
329
330 static unsigned int
lqasc_get_mctrl(struct uart_port * port)331 lqasc_get_mctrl(struct uart_port *port)
332 {
333 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
334 }
335
336 static void
lqasc_set_mctrl(struct uart_port * port,u_int mctrl)337 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
338 {
339 }
340
341 static void
lqasc_break_ctl(struct uart_port * port,int break_state)342 lqasc_break_ctl(struct uart_port *port, int break_state)
343 {
344 }
345
346 static int
lqasc_startup(struct uart_port * port)347 lqasc_startup(struct uart_port *port)
348 {
349 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
350 int retval;
351 unsigned long flags;
352
353 if (!IS_ERR(ltq_port->clk))
354 clk_prepare_enable(ltq_port->clk);
355 port->uartclk = clk_get_rate(ltq_port->freqclk);
356
357 spin_lock_irqsave(<q_port->lock, flags);
358 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
359 port->membase + LTQ_ASC_CLC);
360
361 __raw_writel(0, port->membase + LTQ_ASC_PISEL);
362 __raw_writel(
363 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
364 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
365 port->membase + LTQ_ASC_TXFCON);
366 __raw_writel(
367 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
368 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
369 port->membase + LTQ_ASC_RXFCON);
370 /* make sure other settings are written to hardware before
371 * setting enable bits
372 */
373 wmb();
374 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
375 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
376
377 spin_unlock_irqrestore(<q_port->lock, flags);
378
379 retval = ltq_port->soc->request_irq(port);
380 if (retval)
381 return retval;
382
383 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
384 port->membase + LTQ_ASC_IRNREN);
385 return retval;
386 }
387
388 static void
lqasc_shutdown(struct uart_port * port)389 lqasc_shutdown(struct uart_port *port)
390 {
391 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
392 unsigned long flags;
393
394 ltq_port->soc->free_irq(port);
395
396 spin_lock_irqsave(<q_port->lock, flags);
397 __raw_writel(0, port->membase + LTQ_ASC_CON);
398 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
399 port->membase + LTQ_ASC_RXFCON);
400 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
401 port->membase + LTQ_ASC_TXFCON);
402 spin_unlock_irqrestore(<q_port->lock, flags);
403 if (!IS_ERR(ltq_port->clk))
404 clk_disable_unprepare(ltq_port->clk);
405 }
406
407 static void
lqasc_set_termios(struct uart_port * port,struct ktermios * new,struct ktermios * old)408 lqasc_set_termios(struct uart_port *port,
409 struct ktermios *new, struct ktermios *old)
410 {
411 unsigned int cflag;
412 unsigned int iflag;
413 unsigned int divisor;
414 unsigned int baud;
415 unsigned int con = 0;
416 unsigned long flags;
417 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
418
419 cflag = new->c_cflag;
420 iflag = new->c_iflag;
421
422 switch (cflag & CSIZE) {
423 case CS7:
424 con = ASCCON_M_7ASYNC;
425 break;
426
427 case CS5:
428 case CS6:
429 default:
430 new->c_cflag &= ~ CSIZE;
431 new->c_cflag |= CS8;
432 con = ASCCON_M_8ASYNC;
433 break;
434 }
435
436 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
437
438 if (cflag & CSTOPB)
439 con |= ASCCON_STP;
440
441 if (cflag & PARENB) {
442 if (!(cflag & PARODD))
443 con &= ~ASCCON_ODD;
444 else
445 con |= ASCCON_ODD;
446 }
447
448 port->read_status_mask = ASCSTATE_ROE;
449 if (iflag & INPCK)
450 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
451
452 port->ignore_status_mask = 0;
453 if (iflag & IGNPAR)
454 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
455
456 if (iflag & IGNBRK) {
457 /*
458 * If we're ignoring parity and break indicators,
459 * ignore overruns too (for real raw support).
460 */
461 if (iflag & IGNPAR)
462 port->ignore_status_mask |= ASCSTATE_ROE;
463 }
464
465 if ((cflag & CREAD) == 0)
466 port->ignore_status_mask |= UART_DUMMY_UER_RX;
467
468 /* set error signals - framing, parity and overrun, enable receiver */
469 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
470
471 spin_lock_irqsave(<q_port->lock, flags);
472
473 /* set up CON */
474 asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
475
476 /* Set baud rate - take a divider of 2 into account */
477 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
478 divisor = uart_get_divisor(port, baud);
479 divisor = divisor / 2 - 1;
480
481 /* disable the baudrate generator */
482 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
483
484 /* make sure the fractional divider is off */
485 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
486
487 /* set up to use divisor of 2 */
488 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
489
490 /* now we can write the new baudrate into the register */
491 __raw_writel(divisor, port->membase + LTQ_ASC_BG);
492
493 /* turn the baudrate generator back on */
494 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
495
496 /* enable rx */
497 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
498
499 spin_unlock_irqrestore(<q_port->lock, flags);
500
501 /* Don't rewrite B0 */
502 if (tty_termios_baud_rate(new))
503 tty_termios_encode_baud_rate(new, baud, baud);
504
505 uart_update_timeout(port, cflag, baud);
506 }
507
508 static const char*
lqasc_type(struct uart_port * port)509 lqasc_type(struct uart_port *port)
510 {
511 if (port->type == PORT_LTQ_ASC)
512 return DRVNAME;
513 else
514 return NULL;
515 }
516
517 static void
lqasc_release_port(struct uart_port * port)518 lqasc_release_port(struct uart_port *port)
519 {
520 struct platform_device *pdev = to_platform_device(port->dev);
521
522 if (port->flags & UPF_IOREMAP) {
523 devm_iounmap(&pdev->dev, port->membase);
524 port->membase = NULL;
525 }
526 }
527
528 static int
lqasc_request_port(struct uart_port * port)529 lqasc_request_port(struct uart_port *port)
530 {
531 struct platform_device *pdev = to_platform_device(port->dev);
532 struct resource *res;
533 int size;
534
535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
536 if (!res) {
537 dev_err(&pdev->dev, "cannot obtain I/O memory region");
538 return -ENODEV;
539 }
540 size = resource_size(res);
541
542 res = devm_request_mem_region(&pdev->dev, res->start,
543 size, dev_name(&pdev->dev));
544 if (!res) {
545 dev_err(&pdev->dev, "cannot request I/O memory region");
546 return -EBUSY;
547 }
548
549 if (port->flags & UPF_IOREMAP) {
550 port->membase = devm_ioremap(&pdev->dev,
551 port->mapbase, size);
552 if (port->membase == NULL)
553 return -ENOMEM;
554 }
555 return 0;
556 }
557
558 static void
lqasc_config_port(struct uart_port * port,int flags)559 lqasc_config_port(struct uart_port *port, int flags)
560 {
561 if (flags & UART_CONFIG_TYPE) {
562 port->type = PORT_LTQ_ASC;
563 lqasc_request_port(port);
564 }
565 }
566
567 static int
lqasc_verify_port(struct uart_port * port,struct serial_struct * ser)568 lqasc_verify_port(struct uart_port *port,
569 struct serial_struct *ser)
570 {
571 int ret = 0;
572 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
573 ret = -EINVAL;
574 if (ser->irq < 0 || ser->irq >= NR_IRQS)
575 ret = -EINVAL;
576 if (ser->baud_base < 9600)
577 ret = -EINVAL;
578 return ret;
579 }
580
581 static const struct uart_ops lqasc_pops = {
582 .tx_empty = lqasc_tx_empty,
583 .set_mctrl = lqasc_set_mctrl,
584 .get_mctrl = lqasc_get_mctrl,
585 .stop_tx = lqasc_stop_tx,
586 .start_tx = lqasc_start_tx,
587 .stop_rx = lqasc_stop_rx,
588 .break_ctl = lqasc_break_ctl,
589 .startup = lqasc_startup,
590 .shutdown = lqasc_shutdown,
591 .set_termios = lqasc_set_termios,
592 .type = lqasc_type,
593 .release_port = lqasc_release_port,
594 .request_port = lqasc_request_port,
595 .config_port = lqasc_config_port,
596 .verify_port = lqasc_verify_port,
597 };
598
599 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
600 static void
lqasc_console_putchar(struct uart_port * port,unsigned char ch)601 lqasc_console_putchar(struct uart_port *port, unsigned char ch)
602 {
603 int fifofree;
604
605 if (!port->membase)
606 return;
607
608 do {
609 fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
610 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
611 } while (fifofree == 0);
612 writeb(ch, port->membase + LTQ_ASC_TBUF);
613 }
614
lqasc_serial_port_write(struct uart_port * port,const char * s,u_int count)615 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
616 u_int count)
617 {
618 uart_console_write(port, s, count, lqasc_console_putchar);
619 }
620
621 static void
lqasc_console_write(struct console * co,const char * s,u_int count)622 lqasc_console_write(struct console *co, const char *s, u_int count)
623 {
624 struct ltq_uart_port *ltq_port;
625 unsigned long flags;
626
627 if (co->index >= MAXPORTS)
628 return;
629
630 ltq_port = lqasc_port[co->index];
631 if (!ltq_port)
632 return;
633
634 spin_lock_irqsave(<q_port->lock, flags);
635 lqasc_serial_port_write(<q_port->port, s, count);
636 spin_unlock_irqrestore(<q_port->lock, flags);
637 }
638
639 static int __init
lqasc_console_setup(struct console * co,char * options)640 lqasc_console_setup(struct console *co, char *options)
641 {
642 struct ltq_uart_port *ltq_port;
643 struct uart_port *port;
644 int baud = 115200;
645 int bits = 8;
646 int parity = 'n';
647 int flow = 'n';
648
649 if (co->index >= MAXPORTS)
650 return -ENODEV;
651
652 ltq_port = lqasc_port[co->index];
653 if (!ltq_port)
654 return -ENODEV;
655
656 port = <q_port->port;
657
658 if (!IS_ERR(ltq_port->clk))
659 clk_prepare_enable(ltq_port->clk);
660
661 port->uartclk = clk_get_rate(ltq_port->freqclk);
662
663 if (options)
664 uart_parse_options(options, &baud, &parity, &bits, &flow);
665 return uart_set_options(port, co, baud, parity, bits, flow);
666 }
667
668 static struct console lqasc_console = {
669 .name = "ttyLTQ",
670 .write = lqasc_console_write,
671 .device = uart_console_device,
672 .setup = lqasc_console_setup,
673 .flags = CON_PRINTBUFFER,
674 .index = -1,
675 .data = &lqasc_reg,
676 };
677
678 static int __init
lqasc_console_init(void)679 lqasc_console_init(void)
680 {
681 register_console(&lqasc_console);
682 return 0;
683 }
684 console_initcall(lqasc_console_init);
685
lqasc_serial_early_console_write(struct console * co,const char * s,u_int count)686 static void lqasc_serial_early_console_write(struct console *co,
687 const char *s,
688 u_int count)
689 {
690 struct earlycon_device *dev = co->data;
691
692 lqasc_serial_port_write(&dev->port, s, count);
693 }
694
695 static int __init
lqasc_serial_early_console_setup(struct earlycon_device * device,const char * opt)696 lqasc_serial_early_console_setup(struct earlycon_device *device,
697 const char *opt)
698 {
699 if (!device->port.membase)
700 return -ENODEV;
701
702 device->con->write = lqasc_serial_early_console_write;
703 return 0;
704 }
705 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
706 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
707
708 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console)
709
710 #else
711
712 #define LANTIQ_SERIAL_CONSOLE NULL
713
714 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
715
716 static struct uart_driver lqasc_reg = {
717 .owner = THIS_MODULE,
718 .driver_name = DRVNAME,
719 .dev_name = "ttyLTQ",
720 .major = 0,
721 .minor = 0,
722 .nr = MAXPORTS,
723 .cons = LANTIQ_SERIAL_CONSOLE,
724 };
725
fetch_irq_lantiq(struct device * dev,struct ltq_uart_port * ltq_port)726 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
727 {
728 struct uart_port *port = <q_port->port;
729 struct platform_device *pdev = to_platform_device(dev);
730 int irq;
731
732 irq = platform_get_irq(pdev, 0);
733 if (irq < 0)
734 return irq;
735 ltq_port->tx_irq = irq;
736 irq = platform_get_irq(pdev, 1);
737 if (irq < 0)
738 return irq;
739 ltq_port->rx_irq = irq;
740 irq = platform_get_irq(pdev, 2);
741 if (irq < 0)
742 return irq;
743 ltq_port->err_irq = irq;
744
745 port->irq = ltq_port->tx_irq;
746
747 return 0;
748 }
749
request_irq_lantiq(struct uart_port * port)750 static int request_irq_lantiq(struct uart_port *port)
751 {
752 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
753 int retval;
754
755 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
756 0, "asc_tx", port);
757 if (retval) {
758 dev_err(port->dev, "failed to request asc_tx\n");
759 return retval;
760 }
761
762 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
763 0, "asc_rx", port);
764 if (retval) {
765 dev_err(port->dev, "failed to request asc_rx\n");
766 goto err1;
767 }
768
769 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
770 0, "asc_err", port);
771 if (retval) {
772 dev_err(port->dev, "failed to request asc_err\n");
773 goto err2;
774 }
775 return 0;
776
777 err2:
778 free_irq(ltq_port->rx_irq, port);
779 err1:
780 free_irq(ltq_port->tx_irq, port);
781 return retval;
782 }
783
free_irq_lantiq(struct uart_port * port)784 static void free_irq_lantiq(struct uart_port *port)
785 {
786 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
787
788 free_irq(ltq_port->tx_irq, port);
789 free_irq(ltq_port->rx_irq, port);
790 free_irq(ltq_port->err_irq, port);
791 }
792
fetch_irq_intel(struct device * dev,struct ltq_uart_port * ltq_port)793 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
794 {
795 struct uart_port *port = <q_port->port;
796 int ret;
797
798 ret = platform_get_irq(to_platform_device(dev), 0);
799 if (ret < 0) {
800 dev_err(dev, "failed to fetch IRQ for serial port\n");
801 return ret;
802 }
803 ltq_port->common_irq = ret;
804 port->irq = ret;
805
806 return 0;
807 }
808
request_irq_intel(struct uart_port * port)809 static int request_irq_intel(struct uart_port *port)
810 {
811 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
812 int retval;
813
814 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
815 "asc_irq", port);
816 if (retval)
817 dev_err(port->dev, "failed to request asc_irq\n");
818
819 return retval;
820 }
821
free_irq_intel(struct uart_port * port)822 static void free_irq_intel(struct uart_port *port)
823 {
824 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
825
826 free_irq(ltq_port->common_irq, port);
827 }
828
lqasc_probe(struct platform_device * pdev)829 static int lqasc_probe(struct platform_device *pdev)
830 {
831 struct device_node *node = pdev->dev.of_node;
832 struct ltq_uart_port *ltq_port;
833 struct uart_port *port;
834 struct resource *mmres;
835 int line;
836 int ret;
837
838 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
839 if (!mmres) {
840 dev_err(&pdev->dev,
841 "failed to get memory for serial port\n");
842 return -ENODEV;
843 }
844
845 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
846 GFP_KERNEL);
847 if (!ltq_port)
848 return -ENOMEM;
849
850 port = <q_port->port;
851
852 ltq_port->soc = of_device_get_match_data(&pdev->dev);
853 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
854 if (ret)
855 return ret;
856
857 /* get serial id */
858 line = of_alias_get_id(node, "serial");
859 if (line < 0) {
860 if (IS_ENABLED(CONFIG_LANTIQ)) {
861 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
862 line = 0;
863 else
864 line = 1;
865 } else {
866 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
867 line);
868 return line;
869 }
870 }
871
872 if (lqasc_port[line]) {
873 dev_err(&pdev->dev, "port %d already allocated\n", line);
874 return -EBUSY;
875 }
876
877 port->iotype = SERIAL_IO_MEM;
878 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
879 port->ops = &lqasc_pops;
880 port->fifosize = 16;
881 port->type = PORT_LTQ_ASC;
882 port->line = line;
883 port->dev = &pdev->dev;
884 /* unused, just to be backward-compatible */
885 port->mapbase = mmres->start;
886
887 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
888 ltq_port->freqclk = clk_get_fpi();
889 else
890 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
891
892
893 if (IS_ERR(ltq_port->freqclk)) {
894 pr_err("failed to get fpi clk\n");
895 return -ENOENT;
896 }
897
898 /* not all asc ports have clock gates, lets ignore the return code */
899 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
900 ltq_port->clk = clk_get(&pdev->dev, NULL);
901 else
902 ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
903
904 spin_lock_init(<q_port->lock);
905 lqasc_port[line] = ltq_port;
906 platform_set_drvdata(pdev, ltq_port);
907
908 ret = uart_add_one_port(&lqasc_reg, port);
909
910 return ret;
911 }
912
lqasc_remove(struct platform_device * pdev)913 static int lqasc_remove(struct platform_device *pdev)
914 {
915 struct uart_port *port = platform_get_drvdata(pdev);
916
917 return uart_remove_one_port(&lqasc_reg, port);
918 }
919
920 static const struct ltq_soc_data soc_data_lantiq = {
921 .fetch_irq = fetch_irq_lantiq,
922 .request_irq = request_irq_lantiq,
923 .free_irq = free_irq_lantiq,
924 };
925
926 static const struct ltq_soc_data soc_data_intel = {
927 .fetch_irq = fetch_irq_intel,
928 .request_irq = request_irq_intel,
929 .free_irq = free_irq_intel,
930 };
931
932 static const struct of_device_id ltq_asc_match[] = {
933 { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
934 { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
935 {},
936 };
937 MODULE_DEVICE_TABLE(of, ltq_asc_match);
938
939 static struct platform_driver lqasc_driver = {
940 .probe = lqasc_probe,
941 .remove = lqasc_remove,
942 .driver = {
943 .name = DRVNAME,
944 .of_match_table = ltq_asc_match,
945 },
946 };
947
948 static int __init
init_lqasc(void)949 init_lqasc(void)
950 {
951 int ret;
952
953 ret = uart_register_driver(&lqasc_reg);
954 if (ret != 0)
955 return ret;
956
957 ret = platform_driver_register(&lqasc_driver);
958 if (ret != 0)
959 uart_unregister_driver(&lqasc_reg);
960
961 return ret;
962 }
963
exit_lqasc(void)964 static void __exit exit_lqasc(void)
965 {
966 platform_driver_unregister(&lqasc_driver);
967 uart_unregister_driver(&lqasc_reg);
968 }
969
970 module_init(init_lqasc);
971 module_exit(exit_lqasc);
972
973 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
974 MODULE_LICENSE("GPL v2");
975