1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2017-2019, Linaro Ltd.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/err.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/random.h>
12 #include <linux/slab.h>
13 #include <linux/soc/qcom/smem.h>
14 #include <linux/string.h>
15 #include <linux/sys_soc.h>
16 #include <linux/types.h>
17
18 #include <asm/unaligned.h>
19
20 /*
21 * SoC version type with major number in the upper 16 bits and minor
22 * number in the lower 16 bits.
23 */
24 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
25 #define SOCINFO_MINOR(ver) ((ver) & 0xffff)
26 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
27
28 #define SMEM_SOCINFO_BUILD_ID_LENGTH 32
29 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32
30
31 /*
32 * SMEM item id, used to acquire handles to respective
33 * SMEM region.
34 */
35 #define SMEM_HW_SW_BUILD_ID 137
36
37 #ifdef CONFIG_DEBUG_FS
38 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
39 #define SMEM_IMAGE_VERSION_SIZE 4096
40 #define SMEM_IMAGE_VERSION_NAME_SIZE 75
41 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
42 #define SMEM_IMAGE_VERSION_OEM_SIZE 32
43
44 /*
45 * SMEM Image table indices
46 */
47 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0
48 #define SMEM_IMAGE_TABLE_TZ_INDEX 1
49 #define SMEM_IMAGE_TABLE_RPM_INDEX 3
50 #define SMEM_IMAGE_TABLE_APPS_INDEX 10
51 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11
52 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12
53 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13
54 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
55 #define SMEM_IMAGE_VERSION_TABLE 469
56
57 /*
58 * SMEM Image table names
59 */
60 static const char *const socinfo_image_names[] = {
61 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
62 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
63 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
64 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
65 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
66 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
67 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
68 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
69 };
70
71 static const char *const pmic_models[] = {
72 [0] = "Unknown PMIC model",
73 [1] = "PM8941",
74 [2] = "PM8841",
75 [3] = "PM8019",
76 [4] = "PM8226",
77 [5] = "PM8110",
78 [6] = "PMA8084",
79 [7] = "PMI8962",
80 [8] = "PMD9635",
81 [9] = "PM8994",
82 [10] = "PMI8994",
83 [11] = "PM8916",
84 [12] = "PM8004",
85 [13] = "PM8909/PM8058",
86 [14] = "PM8028",
87 [15] = "PM8901",
88 [16] = "PM8950/PM8027",
89 [17] = "PMI8950/ISL9519",
90 [18] = "PMK8001/PM8921",
91 [19] = "PMI8996/PM8018",
92 [20] = "PM8998/PM8015",
93 [21] = "PMI8998/PM8014",
94 [22] = "PM8821",
95 [23] = "PM8038",
96 [24] = "PM8005/PM8922",
97 [25] = "PM8917",
98 [26] = "PM660L",
99 [27] = "PM660",
100 [30] = "PM8150",
101 [31] = "PM8150L",
102 [32] = "PM8150B",
103 [33] = "PMK8002",
104 [36] = "PM8009",
105 [38] = "PM8150C",
106 [41] = "SMB2351",
107 [47] = "PMK8350",
108 [48] = "PM8350",
109 [49] = "PM8350C",
110 [50] = "PM8350B",
111 [51] = "PMR735A",
112 [52] = "PMR735B",
113 [58] = "PM8450",
114 [65] = "PM8010",
115 };
116 #endif /* CONFIG_DEBUG_FS */
117
118 /* Socinfo SMEM item structure */
119 struct socinfo {
120 __le32 fmt;
121 __le32 id;
122 __le32 ver;
123 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
124 /* Version 2 */
125 __le32 raw_id;
126 __le32 raw_ver;
127 /* Version 3 */
128 __le32 hw_plat;
129 /* Version 4 */
130 __le32 plat_ver;
131 /* Version 5 */
132 __le32 accessory_chip;
133 /* Version 6 */
134 __le32 hw_plat_subtype;
135 /* Version 7 */
136 __le32 pmic_model;
137 __le32 pmic_die_rev;
138 /* Version 8 */
139 __le32 pmic_model_1;
140 __le32 pmic_die_rev_1;
141 __le32 pmic_model_2;
142 __le32 pmic_die_rev_2;
143 /* Version 9 */
144 __le32 foundry_id;
145 /* Version 10 */
146 __le32 serial_num;
147 /* Version 11 */
148 __le32 num_pmics;
149 __le32 pmic_array_offset;
150 /* Version 12 */
151 __le32 chip_family;
152 __le32 raw_device_family;
153 __le32 raw_device_num;
154 /* Version 13 */
155 __le32 nproduct_id;
156 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
157 /* Version 14 */
158 __le32 num_clusters;
159 __le32 ncluster_array_offset;
160 __le32 num_defective_parts;
161 __le32 ndefective_parts_array_offset;
162 /* Version 15 */
163 __le32 nmodem_supported;
164 };
165
166 #ifdef CONFIG_DEBUG_FS
167 struct socinfo_params {
168 u32 raw_device_family;
169 u32 hw_plat_subtype;
170 u32 accessory_chip;
171 u32 raw_device_num;
172 u32 chip_family;
173 u32 foundry_id;
174 u32 plat_ver;
175 u32 raw_ver;
176 u32 hw_plat;
177 u32 fmt;
178 u32 nproduct_id;
179 u32 num_clusters;
180 u32 ncluster_array_offset;
181 u32 num_defective_parts;
182 u32 ndefective_parts_array_offset;
183 u32 nmodem_supported;
184 };
185
186 struct smem_image_version {
187 char name[SMEM_IMAGE_VERSION_NAME_SIZE];
188 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
189 char pad;
190 char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
191 };
192 #endif /* CONFIG_DEBUG_FS */
193
194 struct qcom_socinfo {
195 struct soc_device *soc_dev;
196 struct soc_device_attribute attr;
197 #ifdef CONFIG_DEBUG_FS
198 struct dentry *dbg_root;
199 struct socinfo_params info;
200 #endif /* CONFIG_DEBUG_FS */
201 };
202
203 struct soc_id {
204 unsigned int id;
205 const char *name;
206 };
207
208 static const struct soc_id soc_id[] = {
209 { 87, "MSM8960" },
210 { 109, "APQ8064" },
211 { 122, "MSM8660A" },
212 { 123, "MSM8260A" },
213 { 124, "APQ8060A" },
214 { 126, "MSM8974" },
215 { 130, "MPQ8064" },
216 { 138, "MSM8960AB" },
217 { 139, "APQ8060AB" },
218 { 140, "MSM8260AB" },
219 { 141, "MSM8660AB" },
220 { 145, "MSM8626" },
221 { 147, "MSM8610" },
222 { 153, "APQ8064AB" },
223 { 158, "MSM8226" },
224 { 159, "MSM8526" },
225 { 161, "MSM8110" },
226 { 162, "MSM8210" },
227 { 163, "MSM8810" },
228 { 164, "MSM8212" },
229 { 165, "MSM8612" },
230 { 166, "MSM8112" },
231 { 168, "MSM8225Q" },
232 { 169, "MSM8625Q" },
233 { 170, "MSM8125Q" },
234 { 172, "APQ8064AA" },
235 { 178, "APQ8084" },
236 { 184, "APQ8074" },
237 { 185, "MSM8274" },
238 { 186, "MSM8674" },
239 { 194, "MSM8974PRO-AC" },
240 { 198, "MSM8126" },
241 { 199, "APQ8026" },
242 { 200, "MSM8926" },
243 { 205, "MSM8326" },
244 { 206, "MSM8916" },
245 { 207, "MSM8994" },
246 { 208, "APQ8074PRO-AA" },
247 { 209, "APQ8074PRO-AB" },
248 { 210, "APQ8074PRO-AC" },
249 { 211, "MSM8274PRO-AA" },
250 { 212, "MSM8274PRO-AB" },
251 { 213, "MSM8274PRO-AC" },
252 { 214, "MSM8674PRO-AA" },
253 { 215, "MSM8674PRO-AB" },
254 { 216, "MSM8674PRO-AC" },
255 { 217, "MSM8974PRO-AA" },
256 { 218, "MSM8974PRO-AB" },
257 { 219, "APQ8028" },
258 { 220, "MSM8128" },
259 { 221, "MSM8228" },
260 { 222, "MSM8528" },
261 { 223, "MSM8628" },
262 { 224, "MSM8928" },
263 { 225, "MSM8510" },
264 { 226, "MSM8512" },
265 { 233, "MSM8936" },
266 { 239, "MSM8939" },
267 { 240, "APQ8036" },
268 { 241, "APQ8039" },
269 { 246, "MSM8996" },
270 { 247, "APQ8016" },
271 { 248, "MSM8216" },
272 { 249, "MSM8116" },
273 { 250, "MSM8616" },
274 { 251, "MSM8992" },
275 { 253, "APQ8094" },
276 { 290, "MDM9607" },
277 { 291, "APQ8096" },
278 { 292, "MSM8998" },
279 { 293, "MSM8953" },
280 { 296, "MDM8207" },
281 { 297, "MDM9207" },
282 { 298, "MDM9307" },
283 { 299, "MDM9628" },
284 { 304, "APQ8053" },
285 { 305, "MSM8996SG" },
286 { 310, "MSM8996AU" },
287 { 311, "APQ8096AU" },
288 { 312, "APQ8096SG" },
289 { 317, "SDM660" },
290 { 318, "SDM630" },
291 { 319, "APQ8098" },
292 { 321, "SDM845" },
293 { 322, "MDM9206" },
294 { 323, "IPQ8074" },
295 { 324, "SDA660" },
296 { 325, "SDM658" },
297 { 326, "SDA658" },
298 { 327, "SDA630" },
299 { 338, "SDM450" },
300 { 341, "SDA845" },
301 { 342, "IPQ8072" },
302 { 343, "IPQ8076" },
303 { 344, "IPQ8078" },
304 { 345, "SDM636" },
305 { 346, "SDA636" },
306 { 349, "SDM632" },
307 { 350, "SDA632" },
308 { 351, "SDA450" },
309 { 356, "SM8250" },
310 { 375, "IPQ8070" },
311 { 376, "IPQ8071" },
312 { 389, "IPQ8072A" },
313 { 390, "IPQ8074A" },
314 { 391, "IPQ8076A" },
315 { 392, "IPQ8078A" },
316 { 394, "SM6125" },
317 { 395, "IPQ8070A" },
318 { 396, "IPQ8071A" },
319 { 402, "IPQ6018" },
320 { 403, "IPQ6028" },
321 { 421, "IPQ6000" },
322 { 422, "IPQ6010" },
323 { 425, "SC7180" },
324 { 434, "SM6350" },
325 { 439, "SM8350" },
326 { 449, "SC8280XP" },
327 { 453, "IPQ6005" },
328 { 455, "QRB5165" },
329 { 457, "SM8450" },
330 { 459, "SM7225" },
331 { 460, "SA8295P" },
332 { 461, "SA8540P" },
333 { 480, "SM8450" },
334 { 482, "SM8450" },
335 { 487, "SC7280" },
336 };
337
socinfo_machine(struct device * dev,unsigned int id)338 static const char *socinfo_machine(struct device *dev, unsigned int id)
339 {
340 int idx;
341
342 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
343 if (soc_id[idx].id == id)
344 return soc_id[idx].name;
345 }
346
347 return NULL;
348 }
349
350 #ifdef CONFIG_DEBUG_FS
351
352 #define QCOM_OPEN(name, _func) \
353 static int qcom_open_##name(struct inode *inode, struct file *file) \
354 { \
355 return single_open(file, _func, inode->i_private); \
356 } \
357 \
358 static const struct file_operations qcom_ ##name## _ops = { \
359 .open = qcom_open_##name, \
360 .read = seq_read, \
361 .llseek = seq_lseek, \
362 .release = single_release, \
363 }
364
365 #define DEBUGFS_ADD(info, name) \
366 debugfs_create_file(__stringify(name), 0444, \
367 qcom_socinfo->dbg_root, \
368 info, &qcom_ ##name## _ops)
369
370
qcom_show_build_id(struct seq_file * seq,void * p)371 static int qcom_show_build_id(struct seq_file *seq, void *p)
372 {
373 struct socinfo *socinfo = seq->private;
374
375 seq_printf(seq, "%s\n", socinfo->build_id);
376
377 return 0;
378 }
379
qcom_show_pmic_model(struct seq_file * seq,void * p)380 static int qcom_show_pmic_model(struct seq_file *seq, void *p)
381 {
382 struct socinfo *socinfo = seq->private;
383 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
384
385 if (model < 0)
386 return -EINVAL;
387
388 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
389 seq_printf(seq, "%s\n", pmic_models[model]);
390 else
391 seq_printf(seq, "unknown (%d)\n", model);
392
393 return 0;
394 }
395
qcom_show_pmic_model_array(struct seq_file * seq,void * p)396 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
397 {
398 struct socinfo *socinfo = seq->private;
399 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
400 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
401 int i;
402 void *ptr = socinfo;
403
404 ptr += pmic_array_offset;
405
406 /* No need for bounds checking, it happened at socinfo_debugfs_init */
407 for (i = 0; i < num_pmics; i++) {
408 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
409 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
410
411 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
412 seq_printf(seq, "%s %u.%u\n", pmic_models[model],
413 SOCINFO_MAJOR(die_rev),
414 SOCINFO_MINOR(die_rev));
415 else
416 seq_printf(seq, "unknown (%d)\n", model);
417 }
418
419 return 0;
420 }
421
qcom_show_pmic_die_revision(struct seq_file * seq,void * p)422 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
423 {
424 struct socinfo *socinfo = seq->private;
425
426 seq_printf(seq, "%u.%u\n",
427 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
428 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
429
430 return 0;
431 }
432
qcom_show_chip_id(struct seq_file * seq,void * p)433 static int qcom_show_chip_id(struct seq_file *seq, void *p)
434 {
435 struct socinfo *socinfo = seq->private;
436
437 seq_printf(seq, "%s\n", socinfo->chip_id);
438
439 return 0;
440 }
441
442 QCOM_OPEN(build_id, qcom_show_build_id);
443 QCOM_OPEN(pmic_model, qcom_show_pmic_model);
444 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
445 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
446 QCOM_OPEN(chip_id, qcom_show_chip_id);
447
448 #define DEFINE_IMAGE_OPS(type) \
449 static int show_image_##type(struct seq_file *seq, void *p) \
450 { \
451 struct smem_image_version *image_version = seq->private; \
452 if (image_version->type[0] != '\0') \
453 seq_printf(seq, "%s\n", image_version->type); \
454 return 0; \
455 } \
456 static int open_image_##type(struct inode *inode, struct file *file) \
457 { \
458 return single_open(file, show_image_##type, inode->i_private); \
459 } \
460 \
461 static const struct file_operations qcom_image_##type##_ops = { \
462 .open = open_image_##type, \
463 .read = seq_read, \
464 .llseek = seq_lseek, \
465 .release = single_release, \
466 }
467
468 DEFINE_IMAGE_OPS(name);
469 DEFINE_IMAGE_OPS(variant);
470 DEFINE_IMAGE_OPS(oem);
471
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)472 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
473 struct socinfo *info, size_t info_size)
474 {
475 struct smem_image_version *versions;
476 struct dentry *dentry;
477 size_t size;
478 int i;
479 unsigned int num_pmics;
480 unsigned int pmic_array_offset;
481
482 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
483
484 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
485
486 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
487 &qcom_socinfo->info.fmt);
488
489 switch (qcom_socinfo->info.fmt) {
490 case SOCINFO_VERSION(0, 15):
491 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
492
493 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
494 &qcom_socinfo->info.nmodem_supported);
495 fallthrough;
496 case SOCINFO_VERSION(0, 14):
497 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
498 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
499 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
500 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
501
502 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
503 &qcom_socinfo->info.num_clusters);
504 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
505 &qcom_socinfo->info.ncluster_array_offset);
506 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
507 &qcom_socinfo->info.num_defective_parts);
508 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
509 &qcom_socinfo->info.ndefective_parts_array_offset);
510 fallthrough;
511 case SOCINFO_VERSION(0, 13):
512 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
513
514 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
515 &qcom_socinfo->info.nproduct_id);
516 DEBUGFS_ADD(info, chip_id);
517 fallthrough;
518 case SOCINFO_VERSION(0, 12):
519 qcom_socinfo->info.chip_family =
520 __le32_to_cpu(info->chip_family);
521 qcom_socinfo->info.raw_device_family =
522 __le32_to_cpu(info->raw_device_family);
523 qcom_socinfo->info.raw_device_num =
524 __le32_to_cpu(info->raw_device_num);
525
526 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
527 &qcom_socinfo->info.chip_family);
528 debugfs_create_x32("raw_device_family", 0444,
529 qcom_socinfo->dbg_root,
530 &qcom_socinfo->info.raw_device_family);
531 debugfs_create_x32("raw_device_number", 0444,
532 qcom_socinfo->dbg_root,
533 &qcom_socinfo->info.raw_device_num);
534 fallthrough;
535 case SOCINFO_VERSION(0, 11):
536 num_pmics = le32_to_cpu(info->num_pmics);
537 pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
538 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
539 DEBUGFS_ADD(info, pmic_model_array);
540 fallthrough;
541 case SOCINFO_VERSION(0, 10):
542 case SOCINFO_VERSION(0, 9):
543 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
544
545 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
546 &qcom_socinfo->info.foundry_id);
547 fallthrough;
548 case SOCINFO_VERSION(0, 8):
549 case SOCINFO_VERSION(0, 7):
550 DEBUGFS_ADD(info, pmic_model);
551 DEBUGFS_ADD(info, pmic_die_rev);
552 fallthrough;
553 case SOCINFO_VERSION(0, 6):
554 qcom_socinfo->info.hw_plat_subtype =
555 __le32_to_cpu(info->hw_plat_subtype);
556
557 debugfs_create_u32("hardware_platform_subtype", 0444,
558 qcom_socinfo->dbg_root,
559 &qcom_socinfo->info.hw_plat_subtype);
560 fallthrough;
561 case SOCINFO_VERSION(0, 5):
562 qcom_socinfo->info.accessory_chip =
563 __le32_to_cpu(info->accessory_chip);
564
565 debugfs_create_u32("accessory_chip", 0444,
566 qcom_socinfo->dbg_root,
567 &qcom_socinfo->info.accessory_chip);
568 fallthrough;
569 case SOCINFO_VERSION(0, 4):
570 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
571
572 debugfs_create_u32("platform_version", 0444,
573 qcom_socinfo->dbg_root,
574 &qcom_socinfo->info.plat_ver);
575 fallthrough;
576 case SOCINFO_VERSION(0, 3):
577 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
578
579 debugfs_create_u32("hardware_platform", 0444,
580 qcom_socinfo->dbg_root,
581 &qcom_socinfo->info.hw_plat);
582 fallthrough;
583 case SOCINFO_VERSION(0, 2):
584 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
585
586 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
587 &qcom_socinfo->info.raw_ver);
588 fallthrough;
589 case SOCINFO_VERSION(0, 1):
590 DEBUGFS_ADD(info, build_id);
591 break;
592 }
593
594 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
595 &size);
596
597 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
598 if (!socinfo_image_names[i])
599 continue;
600
601 dentry = debugfs_create_dir(socinfo_image_names[i],
602 qcom_socinfo->dbg_root);
603 debugfs_create_file("name", 0444, dentry, &versions[i],
604 &qcom_image_name_ops);
605 debugfs_create_file("variant", 0444, dentry, &versions[i],
606 &qcom_image_variant_ops);
607 debugfs_create_file("oem", 0444, dentry, &versions[i],
608 &qcom_image_oem_ops);
609 }
610 }
611
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)612 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
613 {
614 debugfs_remove_recursive(qcom_socinfo->dbg_root);
615 }
616 #else
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)617 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
618 struct socinfo *info, size_t info_size)
619 {
620 }
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)621 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
622 #endif /* CONFIG_DEBUG_FS */
623
qcom_socinfo_probe(struct platform_device * pdev)624 static int qcom_socinfo_probe(struct platform_device *pdev)
625 {
626 struct qcom_socinfo *qs;
627 struct socinfo *info;
628 size_t item_size;
629
630 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
631 &item_size);
632 if (IS_ERR(info)) {
633 dev_err(&pdev->dev, "Couldn't find socinfo\n");
634 return PTR_ERR(info);
635 }
636
637 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
638 if (!qs)
639 return -ENOMEM;
640
641 qs->attr.family = "Snapdragon";
642 qs->attr.machine = socinfo_machine(&pdev->dev,
643 le32_to_cpu(info->id));
644 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
645 le32_to_cpu(info->id));
646 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
647 SOCINFO_MAJOR(le32_to_cpu(info->ver)),
648 SOCINFO_MINOR(le32_to_cpu(info->ver)));
649 if (offsetof(struct socinfo, serial_num) <= item_size)
650 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
651 "%u",
652 le32_to_cpu(info->serial_num));
653
654 qs->soc_dev = soc_device_register(&qs->attr);
655 if (IS_ERR(qs->soc_dev))
656 return PTR_ERR(qs->soc_dev);
657
658 socinfo_debugfs_init(qs, info, item_size);
659
660 /* Feed the soc specific unique data into entropy pool */
661 add_device_randomness(info, item_size);
662
663 platform_set_drvdata(pdev, qs);
664
665 return 0;
666 }
667
qcom_socinfo_remove(struct platform_device * pdev)668 static int qcom_socinfo_remove(struct platform_device *pdev)
669 {
670 struct qcom_socinfo *qs = platform_get_drvdata(pdev);
671
672 soc_device_unregister(qs->soc_dev);
673
674 socinfo_debugfs_exit(qs);
675
676 return 0;
677 }
678
679 static struct platform_driver qcom_socinfo_driver = {
680 .probe = qcom_socinfo_probe,
681 .remove = qcom_socinfo_remove,
682 .driver = {
683 .name = "qcom-socinfo",
684 },
685 };
686
687 module_platform_driver(qcom_socinfo_driver);
688
689 MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
690 MODULE_LICENSE("GPL v2");
691 MODULE_ALIAS("platform:qcom-socinfo");
692