1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 Impinj, Inc
4 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
5 *
6 * Based on the code of analogus driver:
7 *
8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/sizes.h>
20 #include <dt-bindings/power/imx7-power.h>
21 #include <dt-bindings/power/imx8mq-power.h>
22 #include <dt-bindings/power/imx8mm-power.h>
23 #include <dt-bindings/power/imx8mn-power.h>
24 #include <dt-bindings/power/imx8mp-power.h>
25
26 #define GPC_LPCR_A_CORE_BSC 0x000
27
28 #define GPC_PGC_CPU_MAPPING 0x0ec
29 #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
30
31 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
32 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
33 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
34 #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
35 #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
36
37 #define IMX8M_PCIE2_A53_DOMAIN BIT(15)
38 #define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
39 #define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
40 #define IMX8M_DISP_A53_DOMAIN BIT(12)
41 #define IMX8M_HDMI_A53_DOMAIN BIT(11)
42 #define IMX8M_VPU_A53_DOMAIN BIT(10)
43 #define IMX8M_GPU_A53_DOMAIN BIT(9)
44 #define IMX8M_DDR2_A53_DOMAIN BIT(8)
45 #define IMX8M_DDR1_A53_DOMAIN BIT(7)
46 #define IMX8M_OTG2_A53_DOMAIN BIT(5)
47 #define IMX8M_OTG1_A53_DOMAIN BIT(4)
48 #define IMX8M_PCIE1_A53_DOMAIN BIT(3)
49 #define IMX8M_MIPI_A53_DOMAIN BIT(2)
50
51 #define IMX8MM_VPUH1_A53_DOMAIN BIT(15)
52 #define IMX8MM_VPUG2_A53_DOMAIN BIT(14)
53 #define IMX8MM_VPUG1_A53_DOMAIN BIT(13)
54 #define IMX8MM_DISPMIX_A53_DOMAIN BIT(12)
55 #define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
56 #define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
57 #define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11))
58 #define IMX8MM_DDR1_A53_DOMAIN BIT(7)
59 #define IMX8MM_OTG2_A53_DOMAIN BIT(5)
60 #define IMX8MM_OTG1_A53_DOMAIN BIT(4)
61 #define IMX8MM_PCIE_A53_DOMAIN BIT(3)
62 #define IMX8MM_MIPI_A53_DOMAIN BIT(2)
63
64 #define IMX8MN_DISPMIX_A53_DOMAIN BIT(12)
65 #define IMX8MN_GPUMIX_A53_DOMAIN BIT(9)
66 #define IMX8MN_DDR1_A53_DOMAIN BIT(7)
67 #define IMX8MN_OTG1_A53_DOMAIN BIT(4)
68 #define IMX8MN_MIPI_A53_DOMAIN BIT(2)
69
70 #define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
71 #define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
72 #define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
73 #define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
74 #define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
75 #define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
76 #define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
77 #define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
78 #define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
79 #define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
80 #define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
81 #define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
82 #define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
83 #define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
84 #define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
85 #define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
86 #define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
87 #define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
88 #define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
89
90 #define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
91 #define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
92
93 #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
94 #define GPC_PU_PGC_SW_PDN_REQ 0x104
95
96 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
97 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
98 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
99 #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
100 #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
101
102 #define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
103 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
104 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
105 #define IMX8M_DISP_SW_Pxx_REQ BIT(10)
106 #define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
107 #define IMX8M_VPU_SW_Pxx_REQ BIT(8)
108 #define IMX8M_GPU_SW_Pxx_REQ BIT(7)
109 #define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
110 #define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
111 #define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
112 #define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
113 #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
114 #define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
115
116 #define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13)
117 #define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12)
118 #define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11)
119 #define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10)
120 #define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8)
121 #define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7)
122 #define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9))
123 #define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
124 #define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
125 #define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
126 #define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
127 #define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
128
129 #define IMX8MN_DISPMIX_SW_Pxx_REQ BIT(10)
130 #define IMX8MN_GPUMIX_SW_Pxx_REQ BIT(7)
131 #define IMX8MN_DDR1_SW_Pxx_REQ BIT(5)
132 #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
133 #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
134
135 #define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
136 #define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
137 #define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
138 #define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
139 #define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
140 #define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
141 #define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
142 #define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
143 #define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
144 #define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
145 #define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
146 #define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
147 #define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
148 #define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
149 #define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
150 #define IMX8MP_MLMIX_Pxx_REQ BIT(4)
151 #define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
152 #define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
153 #define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
154 #define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
155
156 #define GPC_M4_PU_PDN_FLG 0x1bc
157
158 #define IMX8MP_GPC_PU_PWRHSK 0x190
159 #define GPC_PU_PWRHSK 0x1fc
160
161 #define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
162 #define IMX8M_VPU_HSK_PWRDNACKN BIT(25)
163 #define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
164 #define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
165 #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
166 #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
167
168 #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
169 #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
170 #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
171 #define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25)
172 #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
173 #define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11)
174 #define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10))
175 #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8)
176 #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7)
177 #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
178
179 #define IMX8MN_GPUMIX_HSK_PWRDNACKN (BIT(29) | BIT(27))
180 #define IMX8MN_DISPMIX_HSK_PWRDNACKN BIT(25)
181 #define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23)
182 #define IMX8MN_GPUMIX_HSK_PWRDNREQN (BIT(11) | BIT(9))
183 #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
184 #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
185
186 #define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
187 #define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
188 #define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
189 #define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
190 #define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
191 #define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
192 #define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
193 #define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
194 #define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
195 #define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
196 #define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
197 #define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
198 #define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
199 #define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
200
201 /*
202 * The PGC offset values in Reference Manual
203 * (Rev. 1, 01/2018 and the older ones) GPC chapter's
204 * GPC_PGC memory map are incorrect, below offset
205 * values are from design RTL.
206 */
207 #define IMX7_PGC_MIPI 16
208 #define IMX7_PGC_PCIE 17
209 #define IMX7_PGC_USB_HSIC 20
210
211 #define IMX8M_PGC_MIPI 16
212 #define IMX8M_PGC_PCIE1 17
213 #define IMX8M_PGC_OTG1 18
214 #define IMX8M_PGC_OTG2 19
215 #define IMX8M_PGC_DDR1 21
216 #define IMX8M_PGC_GPU 23
217 #define IMX8M_PGC_VPU 24
218 #define IMX8M_PGC_DISP 26
219 #define IMX8M_PGC_MIPI_CSI1 27
220 #define IMX8M_PGC_MIPI_CSI2 28
221 #define IMX8M_PGC_PCIE2 29
222
223 #define IMX8MM_PGC_MIPI 16
224 #define IMX8MM_PGC_PCIE 17
225 #define IMX8MM_PGC_OTG1 18
226 #define IMX8MM_PGC_OTG2 19
227 #define IMX8MM_PGC_DDR1 21
228 #define IMX8MM_PGC_GPU2D 22
229 #define IMX8MM_PGC_GPUMIX 23
230 #define IMX8MM_PGC_VPUMIX 24
231 #define IMX8MM_PGC_GPU3D 25
232 #define IMX8MM_PGC_DISPMIX 26
233 #define IMX8MM_PGC_VPUG1 27
234 #define IMX8MM_PGC_VPUG2 28
235 #define IMX8MM_PGC_VPUH1 29
236
237 #define IMX8MN_PGC_MIPI 16
238 #define IMX8MN_PGC_OTG1 18
239 #define IMX8MN_PGC_DDR1 21
240 #define IMX8MN_PGC_GPUMIX 23
241 #define IMX8MN_PGC_DISPMIX 26
242
243 #define IMX8MP_PGC_NOC 9
244 #define IMX8MP_PGC_MIPI1 12
245 #define IMX8MP_PGC_PCIE 13
246 #define IMX8MP_PGC_USB1 14
247 #define IMX8MP_PGC_USB2 15
248 #define IMX8MP_PGC_MLMIX 16
249 #define IMX8MP_PGC_AUDIOMIX 17
250 #define IMX8MP_PGC_GPU2D 18
251 #define IMX8MP_PGC_GPUMIX 19
252 #define IMX8MP_PGC_VPUMIX 20
253 #define IMX8MP_PGC_GPU3D 21
254 #define IMX8MP_PGC_MEDIAMIX 22
255 #define IMX8MP_PGC_VPU_G1 23
256 #define IMX8MP_PGC_VPU_G2 24
257 #define IMX8MP_PGC_VPU_VC8000E 25
258 #define IMX8MP_PGC_HDMIMIX 26
259 #define IMX8MP_PGC_HDMI 27
260 #define IMX8MP_PGC_MIPI2 28
261 #define IMX8MP_PGC_HSIOMIX 29
262 #define IMX8MP_PGC_MEDIA_ISP_DWP 30
263 #define IMX8MP_PGC_DDRMIX 31
264
265 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
266 #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
267
268 #define GPC_PGC_CTRL_PCR BIT(0)
269
270 struct imx_pgc_regs {
271 u16 map;
272 u16 pup;
273 u16 pdn;
274 u16 hsk;
275 };
276
277 struct imx_pgc_domain {
278 struct generic_pm_domain genpd;
279 struct regmap *regmap;
280 const struct imx_pgc_regs *regs;
281 struct regulator *regulator;
282 struct reset_control *reset;
283 struct clk_bulk_data *clks;
284 int num_clks;
285
286 unsigned long pgc;
287
288 const struct {
289 u32 pxx;
290 u32 map;
291 u32 hskreq;
292 u32 hskack;
293 } bits;
294
295 const int voltage;
296 const bool keep_clocks;
297 struct device *dev;
298
299 unsigned int pgc_sw_pup_reg;
300 unsigned int pgc_sw_pdn_reg;
301 };
302
303 struct imx_pgc_domain_data {
304 const struct imx_pgc_domain *domains;
305 size_t domains_num;
306 const struct regmap_access_table *reg_access_table;
307 const struct imx_pgc_regs *pgc_regs;
308 };
309
310 static inline struct imx_pgc_domain *
to_imx_pgc_domain(struct generic_pm_domain * genpd)311 to_imx_pgc_domain(struct generic_pm_domain *genpd)
312 {
313 return container_of(genpd, struct imx_pgc_domain, genpd);
314 }
315
imx_pgc_power_up(struct generic_pm_domain * genpd)316 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
317 {
318 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
319 u32 reg_val, pgc;
320 int ret;
321
322 ret = pm_runtime_get_sync(domain->dev);
323 if (ret < 0) {
324 pm_runtime_put_noidle(domain->dev);
325 return ret;
326 }
327
328 if (!IS_ERR(domain->regulator)) {
329 ret = regulator_enable(domain->regulator);
330 if (ret) {
331 dev_err(domain->dev, "failed to enable regulator\n");
332 goto out_put_pm;
333 }
334 }
335
336 reset_control_assert(domain->reset);
337
338 /* Enable reset clocks for all devices in the domain */
339 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
340 if (ret) {
341 dev_err(domain->dev, "failed to enable reset clocks\n");
342 goto out_regulator_disable;
343 }
344
345 /* delays for reset to propagate */
346 udelay(5);
347
348 if (domain->bits.pxx) {
349 /* request the domain to power up */
350 regmap_update_bits(domain->regmap, domain->regs->pup,
351 domain->bits.pxx, domain->bits.pxx);
352 /*
353 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
354 * for PUP_REQ/PDN_REQ bit to be cleared
355 */
356 ret = regmap_read_poll_timeout(domain->regmap,
357 domain->regs->pup, reg_val,
358 !(reg_val & domain->bits.pxx),
359 0, USEC_PER_MSEC);
360 if (ret) {
361 dev_err(domain->dev, "failed to command PGC\n");
362 goto out_clk_disable;
363 }
364
365 /* disable power control */
366 for_each_set_bit(pgc, &domain->pgc, 32) {
367 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
368 GPC_PGC_CTRL_PCR);
369 }
370 }
371
372 /* delay for reset to propagate */
373 udelay(5);
374
375 reset_control_deassert(domain->reset);
376
377 /* request the ADB400 to power up */
378 if (domain->bits.hskreq) {
379 regmap_update_bits(domain->regmap, domain->regs->hsk,
380 domain->bits.hskreq, domain->bits.hskreq);
381
382 /*
383 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
384 * (reg_val & domain->bits.hskack), 0,
385 * USEC_PER_MSEC);
386 * Technically we need the commented code to wait handshake. But that needs
387 * the BLK-CTL module BUS clk-en bit being set.
388 *
389 * There is a separate BLK-CTL module and we will have such a driver for it,
390 * that driver will set the BUS clk-en bit and handshake will be triggered
391 * automatically there. Just add a delay and suppose the handshake finish
392 * after that.
393 */
394 }
395
396 /* Disable reset clocks for all devices in the domain */
397 if (!domain->keep_clocks)
398 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
399
400 return 0;
401
402 out_clk_disable:
403 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
404 out_regulator_disable:
405 if (!IS_ERR(domain->regulator))
406 regulator_disable(domain->regulator);
407 out_put_pm:
408 pm_runtime_put(domain->dev);
409
410 return ret;
411 }
412
imx_pgc_power_down(struct generic_pm_domain * genpd)413 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
414 {
415 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
416 u32 reg_val, pgc;
417 int ret;
418
419 /* Enable reset clocks for all devices in the domain */
420 if (!domain->keep_clocks) {
421 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
422 if (ret) {
423 dev_err(domain->dev, "failed to enable reset clocks\n");
424 return ret;
425 }
426 }
427
428 /* request the ADB400 to power down */
429 if (domain->bits.hskreq) {
430 regmap_clear_bits(domain->regmap, domain->regs->hsk,
431 domain->bits.hskreq);
432
433 ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
434 reg_val,
435 !(reg_val & domain->bits.hskack),
436 0, USEC_PER_MSEC);
437 if (ret) {
438 dev_err(domain->dev, "failed to power down ADB400\n");
439 goto out_clk_disable;
440 }
441 }
442
443 if (domain->bits.pxx) {
444 /* enable power control */
445 for_each_set_bit(pgc, &domain->pgc, 32) {
446 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
447 GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
448 }
449
450 /* request the domain to power down */
451 regmap_update_bits(domain->regmap, domain->regs->pdn,
452 domain->bits.pxx, domain->bits.pxx);
453 /*
454 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
455 * for PUP_REQ/PDN_REQ bit to be cleared
456 */
457 ret = regmap_read_poll_timeout(domain->regmap,
458 domain->regs->pdn, reg_val,
459 !(reg_val & domain->bits.pxx),
460 0, USEC_PER_MSEC);
461 if (ret) {
462 dev_err(domain->dev, "failed to command PGC\n");
463 goto out_clk_disable;
464 }
465 }
466
467 /* Disable reset clocks for all devices in the domain */
468 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
469
470 if (!IS_ERR(domain->regulator)) {
471 ret = regulator_disable(domain->regulator);
472 if (ret) {
473 dev_err(domain->dev, "failed to disable regulator\n");
474 return ret;
475 }
476 }
477
478 pm_runtime_put_sync_suspend(domain->dev);
479
480 return 0;
481
482 out_clk_disable:
483 if (!domain->keep_clocks)
484 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
485
486 return ret;
487 }
488
489 static const struct imx_pgc_domain imx7_pgc_domains[] = {
490 [IMX7_POWER_DOMAIN_MIPI_PHY] = {
491 .genpd = {
492 .name = "mipi-phy",
493 },
494 .bits = {
495 .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
496 .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
497 },
498 .voltage = 1000000,
499 .pgc = BIT(IMX7_PGC_MIPI),
500 },
501
502 [IMX7_POWER_DOMAIN_PCIE_PHY] = {
503 .genpd = {
504 .name = "pcie-phy",
505 },
506 .bits = {
507 .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
508 .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
509 },
510 .voltage = 1000000,
511 .pgc = BIT(IMX7_PGC_PCIE),
512 },
513
514 [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
515 .genpd = {
516 .name = "usb-hsic-phy",
517 },
518 .bits = {
519 .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
520 .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
521 },
522 .voltage = 1200000,
523 .pgc = BIT(IMX7_PGC_USB_HSIC),
524 },
525 };
526
527 static const struct regmap_range imx7_yes_ranges[] = {
528 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
529 GPC_M4_PU_PDN_FLG),
530 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
531 GPC_PGC_SR(IMX7_PGC_MIPI)),
532 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
533 GPC_PGC_SR(IMX7_PGC_PCIE)),
534 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
535 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
536 };
537
538 static const struct regmap_access_table imx7_access_table = {
539 .yes_ranges = imx7_yes_ranges,
540 .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
541 };
542
543 static const struct imx_pgc_regs imx7_pgc_regs = {
544 .map = GPC_PGC_CPU_MAPPING,
545 .pup = GPC_PU_PGC_SW_PUP_REQ,
546 .pdn = GPC_PU_PGC_SW_PDN_REQ,
547 .hsk = GPC_PU_PWRHSK,
548 };
549
550 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
551 .domains = imx7_pgc_domains,
552 .domains_num = ARRAY_SIZE(imx7_pgc_domains),
553 .reg_access_table = &imx7_access_table,
554 .pgc_regs = &imx7_pgc_regs,
555 };
556
557 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
558 [IMX8M_POWER_DOMAIN_MIPI] = {
559 .genpd = {
560 .name = "mipi",
561 },
562 .bits = {
563 .pxx = IMX8M_MIPI_SW_Pxx_REQ,
564 .map = IMX8M_MIPI_A53_DOMAIN,
565 },
566 .pgc = BIT(IMX8M_PGC_MIPI),
567 },
568
569 [IMX8M_POWER_DOMAIN_PCIE1] = {
570 .genpd = {
571 .name = "pcie1",
572 },
573 .bits = {
574 .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
575 .map = IMX8M_PCIE1_A53_DOMAIN,
576 },
577 .pgc = BIT(IMX8M_PGC_PCIE1),
578 },
579
580 [IMX8M_POWER_DOMAIN_USB_OTG1] = {
581 .genpd = {
582 .name = "usb-otg1",
583 },
584 .bits = {
585 .pxx = IMX8M_OTG1_SW_Pxx_REQ,
586 .map = IMX8M_OTG1_A53_DOMAIN,
587 },
588 .pgc = BIT(IMX8M_PGC_OTG1),
589 },
590
591 [IMX8M_POWER_DOMAIN_USB_OTG2] = {
592 .genpd = {
593 .name = "usb-otg2",
594 },
595 .bits = {
596 .pxx = IMX8M_OTG2_SW_Pxx_REQ,
597 .map = IMX8M_OTG2_A53_DOMAIN,
598 },
599 .pgc = BIT(IMX8M_PGC_OTG2),
600 },
601
602 [IMX8M_POWER_DOMAIN_DDR1] = {
603 .genpd = {
604 .name = "ddr1",
605 },
606 .bits = {
607 .pxx = IMX8M_DDR1_SW_Pxx_REQ,
608 .map = IMX8M_DDR2_A53_DOMAIN,
609 },
610 .pgc = BIT(IMX8M_PGC_DDR1),
611 },
612
613 [IMX8M_POWER_DOMAIN_GPU] = {
614 .genpd = {
615 .name = "gpu",
616 },
617 .bits = {
618 .pxx = IMX8M_GPU_SW_Pxx_REQ,
619 .map = IMX8M_GPU_A53_DOMAIN,
620 .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
621 .hskack = IMX8M_GPU_HSK_PWRDNACKN,
622 },
623 .pgc = BIT(IMX8M_PGC_GPU),
624 },
625
626 [IMX8M_POWER_DOMAIN_VPU] = {
627 .genpd = {
628 .name = "vpu",
629 },
630 .bits = {
631 .pxx = IMX8M_VPU_SW_Pxx_REQ,
632 .map = IMX8M_VPU_A53_DOMAIN,
633 .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
634 .hskack = IMX8M_VPU_HSK_PWRDNACKN,
635 },
636 .pgc = BIT(IMX8M_PGC_VPU),
637 .keep_clocks = true,
638 },
639
640 [IMX8M_POWER_DOMAIN_DISP] = {
641 .genpd = {
642 .name = "disp",
643 },
644 .bits = {
645 .pxx = IMX8M_DISP_SW_Pxx_REQ,
646 .map = IMX8M_DISP_A53_DOMAIN,
647 .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
648 .hskack = IMX8M_DISP_HSK_PWRDNACKN,
649 },
650 .pgc = BIT(IMX8M_PGC_DISP),
651 },
652
653 [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
654 .genpd = {
655 .name = "mipi-csi1",
656 },
657 .bits = {
658 .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
659 .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
660 },
661 .pgc = BIT(IMX8M_PGC_MIPI_CSI1),
662 },
663
664 [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
665 .genpd = {
666 .name = "mipi-csi2",
667 },
668 .bits = {
669 .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
670 .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
671 },
672 .pgc = BIT(IMX8M_PGC_MIPI_CSI2),
673 },
674
675 [IMX8M_POWER_DOMAIN_PCIE2] = {
676 .genpd = {
677 .name = "pcie2",
678 },
679 .bits = {
680 .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
681 .map = IMX8M_PCIE2_A53_DOMAIN,
682 },
683 .pgc = BIT(IMX8M_PGC_PCIE2),
684 },
685 };
686
687 static const struct regmap_range imx8m_yes_ranges[] = {
688 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
689 GPC_PU_PWRHSK),
690 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
691 GPC_PGC_SR(IMX8M_PGC_MIPI)),
692 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
693 GPC_PGC_SR(IMX8M_PGC_PCIE1)),
694 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
695 GPC_PGC_SR(IMX8M_PGC_OTG1)),
696 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
697 GPC_PGC_SR(IMX8M_PGC_OTG2)),
698 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
699 GPC_PGC_SR(IMX8M_PGC_DDR1)),
700 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
701 GPC_PGC_SR(IMX8M_PGC_GPU)),
702 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
703 GPC_PGC_SR(IMX8M_PGC_VPU)),
704 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
705 GPC_PGC_SR(IMX8M_PGC_DISP)),
706 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
707 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
708 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
709 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
710 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
711 GPC_PGC_SR(IMX8M_PGC_PCIE2)),
712 };
713
714 static const struct regmap_access_table imx8m_access_table = {
715 .yes_ranges = imx8m_yes_ranges,
716 .n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
717 };
718
719 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
720 .domains = imx8m_pgc_domains,
721 .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
722 .reg_access_table = &imx8m_access_table,
723 .pgc_regs = &imx7_pgc_regs,
724 };
725
726 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
727 [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
728 .genpd = {
729 .name = "hsiomix",
730 },
731 .bits = {
732 .pxx = 0, /* no power sequence control */
733 .map = 0, /* no power sequence control */
734 .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
735 .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
736 },
737 .keep_clocks = true,
738 },
739
740 [IMX8MM_POWER_DOMAIN_PCIE] = {
741 .genpd = {
742 .name = "pcie",
743 },
744 .bits = {
745 .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
746 .map = IMX8MM_PCIE_A53_DOMAIN,
747 },
748 .pgc = BIT(IMX8MM_PGC_PCIE),
749 },
750
751 [IMX8MM_POWER_DOMAIN_OTG1] = {
752 .genpd = {
753 .name = "usb-otg1",
754 },
755 .bits = {
756 .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
757 .map = IMX8MM_OTG1_A53_DOMAIN,
758 },
759 .pgc = BIT(IMX8MM_PGC_OTG1),
760 },
761
762 [IMX8MM_POWER_DOMAIN_OTG2] = {
763 .genpd = {
764 .name = "usb-otg2",
765 },
766 .bits = {
767 .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
768 .map = IMX8MM_OTG2_A53_DOMAIN,
769 },
770 .pgc = BIT(IMX8MM_PGC_OTG2),
771 },
772
773 [IMX8MM_POWER_DOMAIN_GPUMIX] = {
774 .genpd = {
775 .name = "gpumix",
776 },
777 .bits = {
778 .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
779 .map = IMX8MM_GPUMIX_A53_DOMAIN,
780 .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
781 .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
782 },
783 .pgc = BIT(IMX8MM_PGC_GPUMIX),
784 .keep_clocks = true,
785 },
786
787 [IMX8MM_POWER_DOMAIN_GPU] = {
788 .genpd = {
789 .name = "gpu",
790 },
791 .bits = {
792 .pxx = IMX8MM_GPU_SW_Pxx_REQ,
793 .map = IMX8MM_GPU_A53_DOMAIN,
794 .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
795 .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
796 },
797 .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
798 },
799
800 [IMX8MM_POWER_DOMAIN_VPUMIX] = {
801 .genpd = {
802 .name = "vpumix",
803 },
804 .bits = {
805 .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
806 .map = IMX8MM_VPUMIX_A53_DOMAIN,
807 .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
808 .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
809 },
810 .pgc = BIT(IMX8MM_PGC_VPUMIX),
811 .keep_clocks = true,
812 },
813
814 [IMX8MM_POWER_DOMAIN_VPUG1] = {
815 .genpd = {
816 .name = "vpu-g1",
817 },
818 .bits = {
819 .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
820 .map = IMX8MM_VPUG1_A53_DOMAIN,
821 },
822 .pgc = BIT(IMX8MM_PGC_VPUG1),
823 },
824
825 [IMX8MM_POWER_DOMAIN_VPUG2] = {
826 .genpd = {
827 .name = "vpu-g2",
828 },
829 .bits = {
830 .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
831 .map = IMX8MM_VPUG2_A53_DOMAIN,
832 },
833 .pgc = BIT(IMX8MM_PGC_VPUG2),
834 },
835
836 [IMX8MM_POWER_DOMAIN_VPUH1] = {
837 .genpd = {
838 .name = "vpu-h1",
839 },
840 .bits = {
841 .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
842 .map = IMX8MM_VPUH1_A53_DOMAIN,
843 },
844 .pgc = BIT(IMX8MM_PGC_VPUH1),
845 .keep_clocks = true,
846 },
847
848 [IMX8MM_POWER_DOMAIN_DISPMIX] = {
849 .genpd = {
850 .name = "dispmix",
851 },
852 .bits = {
853 .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
854 .map = IMX8MM_DISPMIX_A53_DOMAIN,
855 .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
856 .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
857 },
858 .pgc = BIT(IMX8MM_PGC_DISPMIX),
859 .keep_clocks = true,
860 },
861
862 [IMX8MM_POWER_DOMAIN_MIPI] = {
863 .genpd = {
864 .name = "mipi",
865 },
866 .bits = {
867 .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
868 .map = IMX8MM_MIPI_A53_DOMAIN,
869 },
870 .pgc = BIT(IMX8MM_PGC_MIPI),
871 },
872 };
873
874 static const struct regmap_range imx8mm_yes_ranges[] = {
875 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
876 GPC_PU_PWRHSK),
877 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
878 GPC_PGC_SR(IMX8MM_PGC_MIPI)),
879 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
880 GPC_PGC_SR(IMX8MM_PGC_PCIE)),
881 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
882 GPC_PGC_SR(IMX8MM_PGC_OTG1)),
883 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
884 GPC_PGC_SR(IMX8MM_PGC_OTG2)),
885 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
886 GPC_PGC_SR(IMX8MM_PGC_DDR1)),
887 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
888 GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
889 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
890 GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
891 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
892 GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
893 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
894 GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
895 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
896 GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
897 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
898 GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
899 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
900 GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
901 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
902 GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
903 };
904
905 static const struct regmap_access_table imx8mm_access_table = {
906 .yes_ranges = imx8mm_yes_ranges,
907 .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
908 };
909
910 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
911 .domains = imx8mm_pgc_domains,
912 .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
913 .reg_access_table = &imx8mm_access_table,
914 .pgc_regs = &imx7_pgc_regs,
915 };
916
917 static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
918 [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
919 .genpd = {
920 .name = "mipi-phy1",
921 },
922 .bits = {
923 .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
924 .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
925 },
926 .pgc = BIT(IMX8MP_PGC_MIPI1),
927 },
928
929 [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
930 .genpd = {
931 .name = "pcie-phy1",
932 },
933 .bits = {
934 .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
935 .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
936 },
937 .pgc = BIT(IMX8MP_PGC_PCIE),
938 },
939
940 [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
941 .genpd = {
942 .name = "usb-otg1",
943 },
944 .bits = {
945 .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
946 .map = IMX8MP_USB1_PHY_A53_DOMAIN,
947 },
948 .pgc = BIT(IMX8MP_PGC_USB1),
949 },
950
951 [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
952 .genpd = {
953 .name = "usb-otg2",
954 },
955 .bits = {
956 .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
957 .map = IMX8MP_USB2_PHY_A53_DOMAIN,
958 },
959 .pgc = BIT(IMX8MP_PGC_USB2),
960 },
961
962 [IMX8MP_POWER_DOMAIN_MLMIX] = {
963 .genpd = {
964 .name = "mlmix",
965 },
966 .bits = {
967 .pxx = IMX8MP_MLMIX_Pxx_REQ,
968 .map = IMX8MP_MLMIX_A53_DOMAIN,
969 .hskreq = IMX8MP_MLMIX_PWRDNREQN,
970 .hskack = IMX8MP_MLMIX_PWRDNACKN,
971 },
972 .pgc = BIT(IMX8MP_PGC_MLMIX),
973 .keep_clocks = true,
974 },
975
976 [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
977 .genpd = {
978 .name = "audiomix",
979 },
980 .bits = {
981 .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
982 .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
983 .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
984 .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
985 },
986 .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
987 .keep_clocks = true,
988 },
989
990 [IMX8MP_POWER_DOMAIN_GPU2D] = {
991 .genpd = {
992 .name = "gpu2d",
993 },
994 .bits = {
995 .pxx = IMX8MP_GPU_2D_Pxx_REQ,
996 .map = IMX8MP_GPU2D_A53_DOMAIN,
997 },
998 .pgc = BIT(IMX8MP_PGC_GPU2D),
999 },
1000
1001 [IMX8MP_POWER_DOMAIN_GPUMIX] = {
1002 .genpd = {
1003 .name = "gpumix",
1004 },
1005 .bits = {
1006 .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
1007 .map = IMX8MP_GPUMIX_A53_DOMAIN,
1008 .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
1009 .hskack = IMX8MP_GPUMIX_PWRDNACKN,
1010 },
1011 .pgc = BIT(IMX8MP_PGC_GPUMIX),
1012 .keep_clocks = true,
1013 },
1014
1015 [IMX8MP_POWER_DOMAIN_VPUMIX] = {
1016 .genpd = {
1017 .name = "vpumix",
1018 },
1019 .bits = {
1020 .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
1021 .map = IMX8MP_VPUMIX_A53_DOMAIN,
1022 .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
1023 .hskack = IMX8MP_VPUMIX_PWRDNACKN,
1024 },
1025 .pgc = BIT(IMX8MP_PGC_VPUMIX),
1026 .keep_clocks = true,
1027 },
1028
1029 [IMX8MP_POWER_DOMAIN_GPU3D] = {
1030 .genpd = {
1031 .name = "gpu3d",
1032 },
1033 .bits = {
1034 .pxx = IMX8MP_GPU_3D_Pxx_REQ,
1035 .map = IMX8MP_GPU3D_A53_DOMAIN,
1036 },
1037 .pgc = BIT(IMX8MP_PGC_GPU3D),
1038 },
1039
1040 [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
1041 .genpd = {
1042 .name = "mediamix",
1043 },
1044 .bits = {
1045 .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
1046 .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
1047 .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
1048 .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
1049 },
1050 .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
1051 .keep_clocks = true,
1052 },
1053
1054 [IMX8MP_POWER_DOMAIN_VPU_G1] = {
1055 .genpd = {
1056 .name = "vpu-g1",
1057 },
1058 .bits = {
1059 .pxx = IMX8MP_VPU_G1_Pxx_REQ,
1060 .map = IMX8MP_VPU_G1_A53_DOMAIN,
1061 },
1062 .pgc = BIT(IMX8MP_PGC_VPU_G1),
1063 },
1064
1065 [IMX8MP_POWER_DOMAIN_VPU_G2] = {
1066 .genpd = {
1067 .name = "vpu-g2",
1068 },
1069 .bits = {
1070 .pxx = IMX8MP_VPU_G2_Pxx_REQ,
1071 .map = IMX8MP_VPU_G2_A53_DOMAIN
1072 },
1073 .pgc = BIT(IMX8MP_PGC_VPU_G2),
1074 },
1075
1076 [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
1077 .genpd = {
1078 .name = "vpu-h1",
1079 },
1080 .bits = {
1081 .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
1082 .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
1083 },
1084 .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
1085 },
1086
1087 [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
1088 .genpd = {
1089 .name = "hdmimix",
1090 },
1091 .bits = {
1092 .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
1093 .map = IMX8MP_HDMIMIX_A53_DOMAIN,
1094 .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
1095 .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
1096 },
1097 .pgc = BIT(IMX8MP_PGC_HDMIMIX),
1098 .keep_clocks = true,
1099 },
1100
1101 [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
1102 .genpd = {
1103 .name = "hdmi-phy",
1104 },
1105 .bits = {
1106 .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
1107 .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
1108 },
1109 .pgc = BIT(IMX8MP_PGC_HDMI),
1110 },
1111
1112 [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
1113 .genpd = {
1114 .name = "mipi-phy2",
1115 },
1116 .bits = {
1117 .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
1118 .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
1119 },
1120 .pgc = BIT(IMX8MP_PGC_MIPI2),
1121 },
1122
1123 [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
1124 .genpd = {
1125 .name = "hsiomix",
1126 },
1127 .bits = {
1128 .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
1129 .map = IMX8MP_HSIOMIX_A53_DOMAIN,
1130 .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
1131 .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
1132 },
1133 .pgc = BIT(IMX8MP_PGC_HSIOMIX),
1134 .keep_clocks = true,
1135 },
1136
1137 [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
1138 .genpd = {
1139 .name = "mediamix-isp-dwp",
1140 },
1141 .bits = {
1142 .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
1143 .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
1144 },
1145 .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
1146 },
1147 };
1148
1149 static const struct regmap_range imx8mp_yes_ranges[] = {
1150 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1151 IMX8MP_GPC_PGC_CPU_MAPPING),
1152 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
1153 GPC_PGC_SR(IMX8MP_PGC_NOC)),
1154 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
1155 GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
1156 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
1157 GPC_PGC_SR(IMX8MP_PGC_PCIE)),
1158 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
1159 GPC_PGC_SR(IMX8MP_PGC_USB1)),
1160 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
1161 GPC_PGC_SR(IMX8MP_PGC_USB2)),
1162 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
1163 GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
1164 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
1165 GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
1166 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
1167 GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
1168 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
1169 GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
1170 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
1171 GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
1172 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
1173 GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
1174 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
1175 GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
1176 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
1177 GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
1178 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
1179 GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
1180 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
1181 GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
1182 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
1183 GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
1184 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
1185 GPC_PGC_SR(IMX8MP_PGC_HDMI)),
1186 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
1187 GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
1188 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
1189 GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
1190 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
1191 GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
1192 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
1193 GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
1194 };
1195
1196 static const struct regmap_access_table imx8mp_access_table = {
1197 .yes_ranges = imx8mp_yes_ranges,
1198 .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
1199 };
1200
1201 static const struct imx_pgc_regs imx8mp_pgc_regs = {
1202 .map = IMX8MP_GPC_PGC_CPU_MAPPING,
1203 .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
1204 .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
1205 .hsk = IMX8MP_GPC_PU_PWRHSK,
1206 };
1207 static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
1208 .domains = imx8mp_pgc_domains,
1209 .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
1210 .reg_access_table = &imx8mp_access_table,
1211 .pgc_regs = &imx8mp_pgc_regs,
1212 };
1213
1214 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
1215 [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
1216 .genpd = {
1217 .name = "hsiomix",
1218 },
1219 .bits = {
1220 .pxx = 0, /* no power sequence control */
1221 .map = 0, /* no power sequence control */
1222 .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
1223 .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
1224 },
1225 .keep_clocks = true,
1226 },
1227
1228 [IMX8MN_POWER_DOMAIN_OTG1] = {
1229 .genpd = {
1230 .name = "usb-otg1",
1231 },
1232 .bits = {
1233 .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
1234 .map = IMX8MN_OTG1_A53_DOMAIN,
1235 },
1236 .pgc = BIT(IMX8MN_PGC_OTG1),
1237 },
1238
1239 [IMX8MN_POWER_DOMAIN_GPUMIX] = {
1240 .genpd = {
1241 .name = "gpumix",
1242 },
1243 .bits = {
1244 .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
1245 .map = IMX8MN_GPUMIX_A53_DOMAIN,
1246 .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
1247 .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
1248 },
1249 .pgc = BIT(IMX8MN_PGC_GPUMIX),
1250 .keep_clocks = true,
1251 },
1252
1253 [IMX8MN_POWER_DOMAIN_DISPMIX] = {
1254 .genpd = {
1255 .name = "dispmix",
1256 },
1257 .bits = {
1258 .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
1259 .map = IMX8MN_DISPMIX_A53_DOMAIN,
1260 .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
1261 .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
1262 },
1263 .pgc = BIT(IMX8MN_PGC_DISPMIX),
1264 .keep_clocks = true,
1265 },
1266
1267 [IMX8MN_POWER_DOMAIN_MIPI] = {
1268 .genpd = {
1269 .name = "mipi",
1270 },
1271 .bits = {
1272 .pxx = IMX8MN_MIPI_SW_Pxx_REQ,
1273 .map = IMX8MN_MIPI_A53_DOMAIN,
1274 },
1275 .pgc = BIT(IMX8MN_PGC_MIPI),
1276 },
1277 };
1278
1279 static const struct regmap_range imx8mn_yes_ranges[] = {
1280 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1281 GPC_PU_PWRHSK),
1282 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
1283 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
1284 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
1285 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
1286 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
1287 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
1288 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
1289 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
1290 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
1291 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
1292 };
1293
1294 static const struct regmap_access_table imx8mn_access_table = {
1295 .yes_ranges = imx8mn_yes_ranges,
1296 .n_yes_ranges = ARRAY_SIZE(imx8mn_yes_ranges),
1297 };
1298
1299 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
1300 .domains = imx8mn_pgc_domains,
1301 .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
1302 .reg_access_table = &imx8mn_access_table,
1303 .pgc_regs = &imx7_pgc_regs,
1304 };
1305
imx_pgc_domain_probe(struct platform_device * pdev)1306 static int imx_pgc_domain_probe(struct platform_device *pdev)
1307 {
1308 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1309 int ret;
1310
1311 domain->dev = &pdev->dev;
1312
1313 domain->regulator = devm_regulator_get_optional(domain->dev, "power");
1314 if (IS_ERR(domain->regulator)) {
1315 if (PTR_ERR(domain->regulator) != -ENODEV)
1316 return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
1317 "Failed to get domain's regulator\n");
1318 } else if (domain->voltage) {
1319 regulator_set_voltage(domain->regulator,
1320 domain->voltage, domain->voltage);
1321 }
1322
1323 domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
1324 if (domain->num_clks < 0)
1325 return dev_err_probe(domain->dev, domain->num_clks,
1326 "Failed to get domain's clocks\n");
1327
1328 domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
1329 if (IS_ERR(domain->reset))
1330 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
1331 "Failed to get domain's resets\n");
1332
1333 pm_runtime_enable(domain->dev);
1334
1335 if (domain->bits.map)
1336 regmap_update_bits(domain->regmap, domain->regs->map,
1337 domain->bits.map, domain->bits.map);
1338
1339 ret = pm_genpd_init(&domain->genpd, NULL, true);
1340 if (ret) {
1341 dev_err(domain->dev, "Failed to init power domain\n");
1342 goto out_domain_unmap;
1343 }
1344
1345 if (IS_ENABLED(CONFIG_LOCKDEP) &&
1346 of_property_read_bool(domain->dev->of_node, "power-domains"))
1347 lockdep_set_subclass(&domain->genpd.mlock, 1);
1348
1349 ret = of_genpd_add_provider_simple(domain->dev->of_node,
1350 &domain->genpd);
1351 if (ret) {
1352 dev_err(domain->dev, "Failed to add genpd provider\n");
1353 goto out_genpd_remove;
1354 }
1355
1356 return 0;
1357
1358 out_genpd_remove:
1359 pm_genpd_remove(&domain->genpd);
1360 out_domain_unmap:
1361 if (domain->bits.map)
1362 regmap_update_bits(domain->regmap, domain->regs->map,
1363 domain->bits.map, 0);
1364 pm_runtime_disable(domain->dev);
1365
1366 return ret;
1367 }
1368
imx_pgc_domain_remove(struct platform_device * pdev)1369 static int imx_pgc_domain_remove(struct platform_device *pdev)
1370 {
1371 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1372
1373 of_genpd_del_provider(domain->dev->of_node);
1374 pm_genpd_remove(&domain->genpd);
1375
1376 if (domain->bits.map)
1377 regmap_update_bits(domain->regmap, domain->regs->map,
1378 domain->bits.map, 0);
1379
1380 pm_runtime_disable(domain->dev);
1381
1382 return 0;
1383 }
1384
1385 #ifdef CONFIG_PM_SLEEP
imx_pgc_domain_suspend(struct device * dev)1386 static int imx_pgc_domain_suspend(struct device *dev)
1387 {
1388 int ret;
1389
1390 /*
1391 * This may look strange, but is done so the generic PM_SLEEP code
1392 * can power down our domain and more importantly power it up again
1393 * after resume, without tripping over our usage of runtime PM to
1394 * power up/down the nested domains.
1395 */
1396 ret = pm_runtime_get_sync(dev);
1397 if (ret < 0) {
1398 pm_runtime_put_noidle(dev);
1399 return ret;
1400 }
1401
1402 return 0;
1403 }
1404
imx_pgc_domain_resume(struct device * dev)1405 static int imx_pgc_domain_resume(struct device *dev)
1406 {
1407 return pm_runtime_put(dev);
1408 }
1409 #endif
1410
1411 static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
1412 SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
1413 };
1414
1415 static const struct platform_device_id imx_pgc_domain_id[] = {
1416 { "imx-pgc-domain", },
1417 { },
1418 };
1419
1420 static struct platform_driver imx_pgc_domain_driver = {
1421 .driver = {
1422 .name = "imx-pgc",
1423 .pm = &imx_pgc_domain_pm_ops,
1424 },
1425 .probe = imx_pgc_domain_probe,
1426 .remove = imx_pgc_domain_remove,
1427 .id_table = imx_pgc_domain_id,
1428 };
builtin_platform_driver(imx_pgc_domain_driver)1429 builtin_platform_driver(imx_pgc_domain_driver)
1430
1431 static int imx_gpcv2_probe(struct platform_device *pdev)
1432 {
1433 const struct imx_pgc_domain_data *domain_data =
1434 of_device_get_match_data(&pdev->dev);
1435
1436 struct regmap_config regmap_config = {
1437 .reg_bits = 32,
1438 .val_bits = 32,
1439 .reg_stride = 4,
1440 .rd_table = domain_data->reg_access_table,
1441 .wr_table = domain_data->reg_access_table,
1442 .max_register = SZ_4K,
1443 };
1444 struct device *dev = &pdev->dev;
1445 struct device_node *pgc_np, *np;
1446 struct regmap *regmap;
1447 void __iomem *base;
1448 int ret;
1449
1450 pgc_np = of_get_child_by_name(dev->of_node, "pgc");
1451 if (!pgc_np) {
1452 dev_err(dev, "No power domains specified in DT\n");
1453 return -EINVAL;
1454 }
1455
1456 base = devm_platform_ioremap_resource(pdev, 0);
1457 if (IS_ERR(base))
1458 return PTR_ERR(base);
1459
1460 regmap = devm_regmap_init_mmio(dev, base, ®map_config);
1461 if (IS_ERR(regmap)) {
1462 ret = PTR_ERR(regmap);
1463 dev_err(dev, "failed to init regmap (%d)\n", ret);
1464 return ret;
1465 }
1466
1467 for_each_child_of_node(pgc_np, np) {
1468 struct platform_device *pd_pdev;
1469 struct imx_pgc_domain *domain;
1470 u32 domain_index;
1471
1472 if (!of_device_is_available(np))
1473 continue;
1474
1475 ret = of_property_read_u32(np, "reg", &domain_index);
1476 if (ret) {
1477 dev_err(dev, "Failed to read 'reg' property\n");
1478 of_node_put(np);
1479 return ret;
1480 }
1481
1482 if (domain_index >= domain_data->domains_num) {
1483 dev_warn(dev,
1484 "Domain index %d is out of bounds\n",
1485 domain_index);
1486 continue;
1487 }
1488
1489 pd_pdev = platform_device_alloc("imx-pgc-domain",
1490 domain_index);
1491 if (!pd_pdev) {
1492 dev_err(dev, "Failed to allocate platform device\n");
1493 of_node_put(np);
1494 return -ENOMEM;
1495 }
1496
1497 ret = platform_device_add_data(pd_pdev,
1498 &domain_data->domains[domain_index],
1499 sizeof(domain_data->domains[domain_index]));
1500 if (ret) {
1501 platform_device_put(pd_pdev);
1502 of_node_put(np);
1503 return ret;
1504 }
1505
1506 domain = pd_pdev->dev.platform_data;
1507 domain->regmap = regmap;
1508 domain->regs = domain_data->pgc_regs;
1509
1510 domain->genpd.power_on = imx_pgc_power_up;
1511 domain->genpd.power_off = imx_pgc_power_down;
1512
1513 pd_pdev->dev.parent = dev;
1514 pd_pdev->dev.of_node = np;
1515
1516 ret = platform_device_add(pd_pdev);
1517 if (ret) {
1518 platform_device_put(pd_pdev);
1519 of_node_put(np);
1520 return ret;
1521 }
1522 }
1523
1524 return 0;
1525 }
1526
1527 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1528 { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1529 { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1530 { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1531 { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
1532 { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1533 { }
1534 };
1535
1536 static struct platform_driver imx_gpc_driver = {
1537 .driver = {
1538 .name = "imx-gpcv2",
1539 .of_match_table = imx_gpcv2_dt_ids,
1540 },
1541 .probe = imx_gpcv2_probe,
1542 };
1543 builtin_platform_driver(imx_gpc_driver)
1544