1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
57
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
60
61 /*
62 * chip info structure to identify chip key functionality as
63 * encryption available/not, no of ports, hw specific function ref
64 */
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
77 };
78 static int pm8001_id;
79
80 LIST_HEAD(hba_list);
81
82 struct workqueue_struct *pm8001_wq;
83
84 /*
85 * The main structure which LLDD must register for scsi core.
86 */
87 static struct scsi_host_template pm8001_sht = {
88 .module = THIS_MODULE,
89 .name = DRV_NAME,
90 .queuecommand = sas_queuecommand,
91 .dma_need_drain = ata_scsi_dma_need_drain,
92 .target_alloc = sas_target_alloc,
93 .slave_configure = sas_slave_configure,
94 .scan_finished = pm8001_scan_finished,
95 .scan_start = pm8001_scan_start,
96 .change_queue_depth = sas_change_queue_depth,
97 .bios_param = sas_bios_param,
98 .can_queue = 1,
99 .this_id = -1,
100 .sg_tablesize = PM8001_MAX_DMA_SG,
101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
102 .eh_device_reset_handler = sas_eh_device_reset_handler,
103 .eh_target_reset_handler = sas_eh_target_reset_handler,
104 .slave_alloc = sas_slave_alloc,
105 .target_destroy = sas_target_destroy,
106 .ioctl = sas_ioctl,
107 #ifdef CONFIG_COMPAT
108 .compat_ioctl = sas_ioctl,
109 #endif
110 .shost_groups = pm8001_host_groups,
111 .track_queue_depth = 1,
112 };
113
114 /*
115 * Sas layer call this function to execute specific task.
116 */
117 static struct sas_domain_function_template pm8001_transport_ops = {
118 .lldd_dev_found = pm8001_dev_found,
119 .lldd_dev_gone = pm8001_dev_gone,
120
121 .lldd_execute_task = pm8001_queue_command,
122 .lldd_control_phy = pm8001_phy_control,
123
124 .lldd_abort_task = pm8001_abort_task,
125 .lldd_abort_task_set = sas_abort_task_set,
126 .lldd_clear_task_set = pm8001_clear_task_set,
127 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
128 .lldd_lu_reset = pm8001_lu_reset,
129 .lldd_query_task = pm8001_query_task,
130 .lldd_port_formed = pm8001_port_formed,
131 .lldd_tmf_exec_complete = pm8001_setds_completion,
132 .lldd_tmf_aborted = pm8001_tmf_aborted,
133 };
134
135 /**
136 * pm8001_phy_init - initiate our adapter phys
137 * @pm8001_ha: our hba structure.
138 * @phy_id: phy id.
139 */
pm8001_phy_init(struct pm8001_hba_info * pm8001_ha,int phy_id)140 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
141 {
142 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
143 struct asd_sas_phy *sas_phy = &phy->sas_phy;
144 phy->phy_state = PHY_LINK_DISABLE;
145 phy->pm8001_ha = pm8001_ha;
146 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
147 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
148 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
149 sas_phy->class = SAS;
150 sas_phy->iproto = SAS_PROTOCOL_ALL;
151 sas_phy->tproto = 0;
152 sas_phy->type = PHY_TYPE_PHYSICAL;
153 sas_phy->role = PHY_ROLE_INITIATOR;
154 sas_phy->oob_mode = OOB_NOT_CONNECTED;
155 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
156 sas_phy->id = phy_id;
157 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
158 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
159 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
160 sas_phy->lldd_phy = phy;
161 }
162
163 /**
164 * pm8001_free - free hba
165 * @pm8001_ha: our hba structure.
166 */
pm8001_free(struct pm8001_hba_info * pm8001_ha)167 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
168 {
169 int i;
170
171 if (!pm8001_ha)
172 return;
173
174 for (i = 0; i < USI_MAX_MEMCNT; i++) {
175 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
176 dma_free_coherent(&pm8001_ha->pdev->dev,
177 (pm8001_ha->memoryMap.region[i].total_len +
178 pm8001_ha->memoryMap.region[i].alignment),
179 pm8001_ha->memoryMap.region[i].virt_ptr,
180 pm8001_ha->memoryMap.region[i].phys_addr);
181 }
182 }
183 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
184 flush_workqueue(pm8001_wq);
185 bitmap_free(pm8001_ha->tags);
186 kfree(pm8001_ha);
187 }
188
189 #ifdef PM8001_USE_TASKLET
190
191 /**
192 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
193 * @opaque: the passed general host adapter struct
194 * Note: pm8001_tasklet is common for pm8001 & pm80xx
195 */
pm8001_tasklet(unsigned long opaque)196 static void pm8001_tasklet(unsigned long opaque)
197 {
198 struct pm8001_hba_info *pm8001_ha;
199 struct isr_param *irq_vector;
200
201 irq_vector = (struct isr_param *)opaque;
202 pm8001_ha = irq_vector->drv_inst;
203 if (unlikely(!pm8001_ha))
204 BUG_ON(1);
205 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
206 }
207 #endif
208
209 /**
210 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
211 * It obtains the vector number and calls the equivalent bottom
212 * half or services directly.
213 * @irq: interrupt number
214 * @opaque: the passed outbound queue/vector. Host structure is
215 * retrieved from the same.
216 */
pm8001_interrupt_handler_msix(int irq,void * opaque)217 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
218 {
219 struct isr_param *irq_vector;
220 struct pm8001_hba_info *pm8001_ha;
221 irqreturn_t ret = IRQ_HANDLED;
222 irq_vector = (struct isr_param *)opaque;
223 pm8001_ha = irq_vector->drv_inst;
224
225 if (unlikely(!pm8001_ha))
226 return IRQ_NONE;
227 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
228 return IRQ_NONE;
229 #ifdef PM8001_USE_TASKLET
230 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
231 #else
232 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
233 #endif
234 return ret;
235 }
236
237 /**
238 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
239 * @irq: interrupt number
240 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
241 */
242
pm8001_interrupt_handler_intx(int irq,void * dev_id)243 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
244 {
245 struct pm8001_hba_info *pm8001_ha;
246 irqreturn_t ret = IRQ_HANDLED;
247 struct sas_ha_struct *sha = dev_id;
248 pm8001_ha = sha->lldd_ha;
249 if (unlikely(!pm8001_ha))
250 return IRQ_NONE;
251 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
252 return IRQ_NONE;
253
254 #ifdef PM8001_USE_TASKLET
255 tasklet_schedule(&pm8001_ha->tasklet[0]);
256 #else
257 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
258 #endif
259 return ret;
260 }
261
262 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
263 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
264
265 /**
266 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
267 * @pm8001_ha: our hba structure.
268 * @ent: PCI device ID structure to match on
269 */
pm8001_alloc(struct pm8001_hba_info * pm8001_ha,const struct pci_device_id * ent)270 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
271 const struct pci_device_id *ent)
272 {
273 int i, count = 0, rc = 0;
274 u32 ci_offset, ib_offset, ob_offset, pi_offset;
275 struct inbound_queue_table *ibq;
276 struct outbound_queue_table *obq;
277
278 spin_lock_init(&pm8001_ha->lock);
279 spin_lock_init(&pm8001_ha->bitmap_lock);
280 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
281 pm8001_ha->chip->n_phy);
282
283 /* Setup Interrupt */
284 rc = pm8001_setup_irq(pm8001_ha);
285 if (rc) {
286 pm8001_dbg(pm8001_ha, FAIL,
287 "pm8001_setup_irq failed [ret: %d]\n", rc);
288 goto err_out;
289 }
290 /* Request Interrupt */
291 rc = pm8001_request_irq(pm8001_ha);
292 if (rc)
293 goto err_out;
294
295 count = pm8001_ha->max_q_num;
296 /* Queues are chosen based on the number of cores/msix availability */
297 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
298 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
299 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
300 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
301 pm8001_ha->max_memcnt = pi_offset + count;
302
303 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
304 pm8001_phy_init(pm8001_ha, i);
305 pm8001_ha->port[i].wide_port_phymap = 0;
306 pm8001_ha->port[i].port_attached = 0;
307 pm8001_ha->port[i].port_state = 0;
308 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
309 }
310
311 /* MPI Memory region 1 for AAP Event Log for fw */
312 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
313 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
314 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
315 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
316
317 /* MPI Memory region 2 for IOP Event Log for fw */
318 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
319 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
320 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
321 pm8001_ha->memoryMap.region[IOP].alignment = 32;
322
323 for (i = 0; i < count; i++) {
324 ibq = &pm8001_ha->inbnd_q_tbl[i];
325 spin_lock_init(&ibq->iq_lock);
326 /* MPI Memory region 3 for consumer Index of inbound queues */
327 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
328 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
329 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
330 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
331
332 if ((ent->driver_data) != chip_8001) {
333 /* MPI Memory region 5 inbound queues */
334 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
335 PM8001_MPI_QUEUE;
336 pm8001_ha->memoryMap.region[ib_offset+i].element_size
337 = 128;
338 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
339 PM8001_MPI_QUEUE * 128;
340 pm8001_ha->memoryMap.region[ib_offset+i].alignment
341 = 128;
342 } else {
343 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
344 PM8001_MPI_QUEUE;
345 pm8001_ha->memoryMap.region[ib_offset+i].element_size
346 = 64;
347 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
348 PM8001_MPI_QUEUE * 64;
349 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
350 }
351 }
352
353 for (i = 0; i < count; i++) {
354 obq = &pm8001_ha->outbnd_q_tbl[i];
355 spin_lock_init(&obq->oq_lock);
356 /* MPI Memory region 4 for producer Index of outbound queues */
357 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
358 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
359 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
360 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
361
362 if (ent->driver_data != chip_8001) {
363 /* MPI Memory region 6 Outbound queues */
364 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
365 PM8001_MPI_QUEUE;
366 pm8001_ha->memoryMap.region[ob_offset+i].element_size
367 = 128;
368 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
369 PM8001_MPI_QUEUE * 128;
370 pm8001_ha->memoryMap.region[ob_offset+i].alignment
371 = 128;
372 } else {
373 /* MPI Memory region 6 Outbound queues */
374 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
375 PM8001_MPI_QUEUE;
376 pm8001_ha->memoryMap.region[ob_offset+i].element_size
377 = 64;
378 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
379 PM8001_MPI_QUEUE * 64;
380 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
381 }
382
383 }
384 /* Memory region write DMA*/
385 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
386 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
387 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
388
389 /* Memory region for fw flash */
390 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
391
392 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
393 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
394 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
395 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
396 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
397 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
398
399 if (pm8001_mem_alloc(pm8001_ha->pdev,
400 ®ion->virt_ptr,
401 ®ion->phys_addr,
402 ®ion->phys_addr_hi,
403 ®ion->phys_addr_lo,
404 region->total_len,
405 region->alignment) != 0) {
406 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
407 goto err_out;
408 }
409 }
410
411 /* Memory region for devices*/
412 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
413 * sizeof(struct pm8001_device), GFP_KERNEL);
414 if (!pm8001_ha->devices) {
415 rc = -ENOMEM;
416 goto err_out_nodev;
417 }
418 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
419 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
420 pm8001_ha->devices[i].id = i;
421 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
422 atomic_set(&pm8001_ha->devices[i].running_req, 0);
423 }
424 pm8001_ha->flags = PM8001F_INIT_TIME;
425 /* Initialize tags */
426 pm8001_tag_init(pm8001_ha);
427 return 0;
428
429 err_out_nodev:
430 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
431 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
432 dma_free_coherent(&pm8001_ha->pdev->dev,
433 (pm8001_ha->memoryMap.region[i].total_len +
434 pm8001_ha->memoryMap.region[i].alignment),
435 pm8001_ha->memoryMap.region[i].virt_ptr,
436 pm8001_ha->memoryMap.region[i].phys_addr);
437 }
438 }
439 err_out:
440 return 1;
441 }
442
443 /**
444 * pm8001_ioremap - remap the pci high physical address to kernel virtual
445 * address so that we can access them.
446 * @pm8001_ha: our hba structure.
447 */
pm8001_ioremap(struct pm8001_hba_info * pm8001_ha)448 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
449 {
450 u32 bar;
451 u32 logicalBar = 0;
452 struct pci_dev *pdev;
453
454 pdev = pm8001_ha->pdev;
455 /* map pci mem (PMC pci base 0-3)*/
456 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
457 /*
458 ** logical BARs for SPC:
459 ** bar 0 and 1 - logical BAR0
460 ** bar 2 and 3 - logical BAR1
461 ** bar4 - logical BAR2
462 ** bar5 - logical BAR3
463 ** Skip the appropriate assignments:
464 */
465 if ((bar == 1) || (bar == 3))
466 continue;
467 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
468 pm8001_ha->io_mem[logicalBar].membase =
469 pci_resource_start(pdev, bar);
470 pm8001_ha->io_mem[logicalBar].memsize =
471 pci_resource_len(pdev, bar);
472 pm8001_ha->io_mem[logicalBar].memvirtaddr =
473 ioremap(pm8001_ha->io_mem[logicalBar].membase,
474 pm8001_ha->io_mem[logicalBar].memsize);
475 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
476 pm8001_dbg(pm8001_ha, INIT,
477 "Failed to ioremap bar %d, logicalBar %d",
478 bar, logicalBar);
479 return -ENOMEM;
480 }
481 pm8001_dbg(pm8001_ha, INIT,
482 "base addr %llx virt_addr=%llx len=%d\n",
483 (u64)pm8001_ha->io_mem[logicalBar].membase,
484 (u64)(unsigned long)
485 pm8001_ha->io_mem[logicalBar].memvirtaddr,
486 pm8001_ha->io_mem[logicalBar].memsize);
487 } else {
488 pm8001_ha->io_mem[logicalBar].membase = 0;
489 pm8001_ha->io_mem[logicalBar].memsize = 0;
490 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
491 }
492 logicalBar++;
493 }
494 return 0;
495 }
496
497 /**
498 * pm8001_pci_alloc - initialize our ha card structure
499 * @pdev: pci device.
500 * @ent: ent
501 * @shost: scsi host struct which has been initialized before.
502 */
pm8001_pci_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,struct Scsi_Host * shost)503 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
504 const struct pci_device_id *ent,
505 struct Scsi_Host *shost)
506
507 {
508 struct pm8001_hba_info *pm8001_ha;
509 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
510 int j;
511
512 pm8001_ha = sha->lldd_ha;
513 if (!pm8001_ha)
514 return NULL;
515
516 pm8001_ha->pdev = pdev;
517 pm8001_ha->dev = &pdev->dev;
518 pm8001_ha->chip_id = ent->driver_data;
519 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
520 pm8001_ha->irq = pdev->irq;
521 pm8001_ha->sas = sha;
522 pm8001_ha->shost = shost;
523 pm8001_ha->id = pm8001_id++;
524 pm8001_ha->logging_level = logging_level;
525 pm8001_ha->non_fatal_count = 0;
526 if (link_rate >= 1 && link_rate <= 15)
527 pm8001_ha->link_rate = (link_rate << 8);
528 else {
529 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
530 LINKRATE_60 | LINKRATE_120;
531 pm8001_dbg(pm8001_ha, FAIL,
532 "Setting link rate to default value\n");
533 }
534 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
535 /* IOMB size is 128 for 8088/89 controllers */
536 if (pm8001_ha->chip_id != chip_8001)
537 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
538 else
539 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
540
541 #ifdef PM8001_USE_TASKLET
542 /* Tasklet for non msi-x interrupt handler */
543 if ((!pdev->msix_cap || !pci_msi_enabled())
544 || (pm8001_ha->chip_id == chip_8001))
545 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
546 (unsigned long)&(pm8001_ha->irq_vector[0]));
547 else
548 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
549 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
550 (unsigned long)&(pm8001_ha->irq_vector[j]));
551 #endif
552 if (pm8001_ioremap(pm8001_ha))
553 goto failed_pci_alloc;
554 if (!pm8001_alloc(pm8001_ha, ent))
555 return pm8001_ha;
556 failed_pci_alloc:
557 pm8001_free(pm8001_ha);
558 return NULL;
559 }
560
561 /**
562 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
563 * @pdev: pci device.
564 */
pci_go_44(struct pci_dev * pdev)565 static int pci_go_44(struct pci_dev *pdev)
566 {
567 int rc;
568
569 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
570 if (rc) {
571 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
572 if (rc)
573 dev_printk(KERN_ERR, &pdev->dev,
574 "32-bit DMA enable failed\n");
575 }
576 return rc;
577 }
578
579 /**
580 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
581 * @shost: scsi host which has been allocated outside.
582 * @chip_info: our ha struct.
583 */
pm8001_prep_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)584 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
585 const struct pm8001_chip_info *chip_info)
586 {
587 int phy_nr, port_nr;
588 struct asd_sas_phy **arr_phy;
589 struct asd_sas_port **arr_port;
590 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591
592 phy_nr = chip_info->n_phy;
593 port_nr = phy_nr;
594 memset(sha, 0x00, sizeof(*sha));
595 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
596 if (!arr_phy)
597 goto exit;
598 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
599 if (!arr_port)
600 goto exit_free2;
601
602 sha->sas_phy = arr_phy;
603 sha->sas_port = arr_port;
604 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
605 if (!sha->lldd_ha)
606 goto exit_free1;
607
608 shost->transportt = pm8001_stt;
609 shost->max_id = PM8001_MAX_DEVICES;
610 shost->max_lun = 8;
611 shost->max_channel = 0;
612 shost->unique_id = pm8001_id;
613 shost->max_cmd_len = 16;
614 shost->can_queue = PM8001_CAN_QUEUE;
615 shost->cmd_per_lun = 32;
616 return 0;
617 exit_free1:
618 kfree(arr_port);
619 exit_free2:
620 kfree(arr_phy);
621 exit:
622 return -1;
623 }
624
625 /**
626 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
627 * @shost: scsi host which has been allocated outside
628 * @chip_info: our ha struct.
629 */
pm8001_post_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)630 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
631 const struct pm8001_chip_info *chip_info)
632 {
633 int i = 0;
634 struct pm8001_hba_info *pm8001_ha;
635 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
636
637 pm8001_ha = sha->lldd_ha;
638 for (i = 0; i < chip_info->n_phy; i++) {
639 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
640 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
641 sha->sas_phy[i]->sas_addr =
642 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
643 }
644 sha->sas_ha_name = DRV_NAME;
645 sha->dev = pm8001_ha->dev;
646 sha->strict_wide_ports = 1;
647 sha->lldd_module = THIS_MODULE;
648 sha->sas_addr = &pm8001_ha->sas_addr[0];
649 sha->num_phys = chip_info->n_phy;
650 sha->core.shost = shost;
651 }
652
653 /**
654 * pm8001_init_sas_add - initialize sas address
655 * @pm8001_ha: our ha struct.
656 *
657 * Currently we just set the fixed SAS address to our HBA, for manufacture,
658 * it should read from the EEPROM
659 */
pm8001_init_sas_add(struct pm8001_hba_info * pm8001_ha)660 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
661 {
662 u8 i, j;
663 u8 sas_add[8];
664 #ifdef PM8001_READ_VPD
665 /* For new SPC controllers WWN is stored in flash vpd
666 * For SPC/SPCve controllers WWN is stored in EEPROM
667 * For Older SPC WWN is stored in NVMD
668 */
669 DECLARE_COMPLETION_ONSTACK(completion);
670 struct pm8001_ioctl_payload payload;
671 u16 deviceid;
672 int rc;
673
674 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
675 pm8001_ha->nvmd_completion = &completion;
676
677 if (pm8001_ha->chip_id == chip_8001) {
678 if (deviceid == 0x8081 || deviceid == 0x0042) {
679 payload.minor_function = 4;
680 payload.rd_length = 4096;
681 } else {
682 payload.minor_function = 0;
683 payload.rd_length = 128;
684 }
685 } else if ((pm8001_ha->chip_id == chip_8070 ||
686 pm8001_ha->chip_id == chip_8072) &&
687 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
688 payload.minor_function = 4;
689 payload.rd_length = 4096;
690 } else {
691 payload.minor_function = 1;
692 payload.rd_length = 4096;
693 }
694 payload.offset = 0;
695 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
696 if (!payload.func_specific) {
697 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
698 return;
699 }
700 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
701 if (rc) {
702 kfree(payload.func_specific);
703 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
704 return;
705 }
706 wait_for_completion(&completion);
707
708 for (i = 0, j = 0; i <= 7; i++, j++) {
709 if (pm8001_ha->chip_id == chip_8001) {
710 if (deviceid == 0x8081)
711 pm8001_ha->sas_addr[j] =
712 payload.func_specific[0x704 + i];
713 else if (deviceid == 0x0042)
714 pm8001_ha->sas_addr[j] =
715 payload.func_specific[0x010 + i];
716 } else if ((pm8001_ha->chip_id == chip_8070 ||
717 pm8001_ha->chip_id == chip_8072) &&
718 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
719 pm8001_ha->sas_addr[j] =
720 payload.func_specific[0x010 + i];
721 } else
722 pm8001_ha->sas_addr[j] =
723 payload.func_specific[0x804 + i];
724 }
725 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
726 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
727 if (i && ((i % 4) == 0))
728 sas_add[7] = sas_add[7] + 4;
729 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
730 sas_add, SAS_ADDR_SIZE);
731 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
732 pm8001_ha->phy[i].dev_sas_addr);
733 }
734 kfree(payload.func_specific);
735 #else
736 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
737 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
738 pm8001_ha->phy[i].dev_sas_addr =
739 cpu_to_be64((u64)
740 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
741 }
742 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
743 SAS_ADDR_SIZE);
744 #endif
745 }
746
747 /*
748 * pm8001_get_phy_settings_info : Read phy setting values.
749 * @pm8001_ha : our hba.
750 */
pm8001_get_phy_settings_info(struct pm8001_hba_info * pm8001_ha)751 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
752 {
753
754 #ifdef PM8001_READ_VPD
755 /*OPTION ROM FLASH read for the SPC cards */
756 DECLARE_COMPLETION_ONSTACK(completion);
757 struct pm8001_ioctl_payload payload;
758 int rc;
759
760 pm8001_ha->nvmd_completion = &completion;
761 /* SAS ADDRESS read from flash / EEPROM */
762 payload.minor_function = 6;
763 payload.offset = 0;
764 payload.rd_length = 4096;
765 payload.func_specific = kzalloc(4096, GFP_KERNEL);
766 if (!payload.func_specific)
767 return -ENOMEM;
768 /* Read phy setting values from flash */
769 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
770 if (rc) {
771 kfree(payload.func_specific);
772 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
773 return -ENOMEM;
774 }
775 wait_for_completion(&completion);
776 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
777 kfree(payload.func_specific);
778 #endif
779 return 0;
780 }
781
782 struct pm8001_mpi3_phy_pg_trx_config {
783 u32 LaneLosCfg;
784 u32 LanePgaCfg1;
785 u32 LanePisoCfg1;
786 u32 LanePisoCfg2;
787 u32 LanePisoCfg3;
788 u32 LanePisoCfg4;
789 u32 LanePisoCfg5;
790 u32 LanePisoCfg6;
791 u32 LaneBctCtrl;
792 };
793
794 /**
795 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
796 * @pm8001_ha : our adapter
797 * @phycfg : PHY config page to populate
798 */
799 static
pm8001_get_internal_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)800 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
801 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
802 {
803 phycfg->LaneLosCfg = 0x00000132;
804 phycfg->LanePgaCfg1 = 0x00203949;
805 phycfg->LanePisoCfg1 = 0x000000FF;
806 phycfg->LanePisoCfg2 = 0xFF000001;
807 phycfg->LanePisoCfg3 = 0xE7011300;
808 phycfg->LanePisoCfg4 = 0x631C40C0;
809 phycfg->LanePisoCfg5 = 0xF8102036;
810 phycfg->LanePisoCfg6 = 0xF74A1000;
811 phycfg->LaneBctCtrl = 0x00FB33F8;
812 }
813
814 /**
815 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
816 * @pm8001_ha : our adapter
817 * @phycfg : PHY config page to populate
818 */
819 static
pm8001_get_external_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)820 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
821 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
822 {
823 phycfg->LaneLosCfg = 0x00000132;
824 phycfg->LanePgaCfg1 = 0x00203949;
825 phycfg->LanePisoCfg1 = 0x000000FF;
826 phycfg->LanePisoCfg2 = 0xFF000001;
827 phycfg->LanePisoCfg3 = 0xE7011300;
828 phycfg->LanePisoCfg4 = 0x63349140;
829 phycfg->LanePisoCfg5 = 0xF8102036;
830 phycfg->LanePisoCfg6 = 0xF80D9300;
831 phycfg->LaneBctCtrl = 0x00FB33F8;
832 }
833
834 /**
835 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
836 * @pm8001_ha : our adapter
837 * @phymask : The PHY mask
838 */
839 static
pm8001_get_phy_mask(struct pm8001_hba_info * pm8001_ha,int * phymask)840 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
841 {
842 switch (pm8001_ha->pdev->subsystem_device) {
843 case 0x0070: /* H1280 - 8 external 0 internal */
844 case 0x0072: /* H12F0 - 16 external 0 internal */
845 *phymask = 0x0000;
846 break;
847
848 case 0x0071: /* H1208 - 0 external 8 internal */
849 case 0x0073: /* H120F - 0 external 16 internal */
850 *phymask = 0xFFFF;
851 break;
852
853 case 0x0080: /* H1244 - 4 external 4 internal */
854 *phymask = 0x00F0;
855 break;
856
857 case 0x0081: /* H1248 - 4 external 8 internal */
858 *phymask = 0x0FF0;
859 break;
860
861 case 0x0082: /* H1288 - 8 external 8 internal */
862 *phymask = 0xFF00;
863 break;
864
865 default:
866 pm8001_dbg(pm8001_ha, INIT,
867 "Unknown subsystem device=0x%.04x\n",
868 pm8001_ha->pdev->subsystem_device);
869 }
870 }
871
872 /**
873 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
874 * @pm8001_ha : our adapter
875 */
876 static
pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info * pm8001_ha)877 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
878 {
879 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
880 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
881 int phymask = 0;
882 int i = 0;
883
884 memset(&phycfg_int, 0, sizeof(phycfg_int));
885 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
886
887 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
888 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
889 pm8001_get_phy_mask(pm8001_ha, &phymask);
890
891 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
892 if (phymask & (1 << i)) {/* Internal PHY */
893 pm8001_set_phy_profile_single(pm8001_ha, i,
894 sizeof(phycfg_int) / sizeof(u32),
895 (u32 *)&phycfg_int);
896
897 } else { /* External PHY */
898 pm8001_set_phy_profile_single(pm8001_ha, i,
899 sizeof(phycfg_ext) / sizeof(u32),
900 (u32 *)&phycfg_ext);
901 }
902 }
903
904 return 0;
905 }
906
907 /**
908 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
909 * @pm8001_ha : our hba.
910 */
pm8001_configure_phy_settings(struct pm8001_hba_info * pm8001_ha)911 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
912 {
913 switch (pm8001_ha->pdev->subsystem_vendor) {
914 case PCI_VENDOR_ID_ATTO:
915 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
916 return 0;
917 else
918 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
919
920 case PCI_VENDOR_ID_ADAPTEC2:
921 case 0:
922 return 0;
923
924 default:
925 return pm8001_get_phy_settings_info(pm8001_ha);
926 }
927 }
928
929 #ifdef PM8001_USE_MSIX
930 /**
931 * pm8001_setup_msix - enable MSI-X interrupt
932 * @pm8001_ha: our ha struct.
933 */
pm8001_setup_msix(struct pm8001_hba_info * pm8001_ha)934 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
935 {
936 u32 number_of_intr;
937 int rc, cpu_online_count;
938 unsigned int allocated_irq_vectors;
939
940 /* SPCv controllers supports 64 msi-x */
941 if (pm8001_ha->chip_id == chip_8001) {
942 number_of_intr = 1;
943 } else {
944 number_of_intr = PM8001_MAX_MSIX_VEC;
945 }
946
947 cpu_online_count = num_online_cpus();
948 number_of_intr = min_t(int, cpu_online_count, number_of_intr);
949 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
950 number_of_intr, PCI_IRQ_MSIX);
951 allocated_irq_vectors = rc;
952 if (rc < 0)
953 return rc;
954
955 /* Assigns the number of interrupts */
956 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
957 pm8001_ha->number_of_intr = number_of_intr;
958
959 /* Maximum queue number updating in HBA structure */
960 pm8001_ha->max_q_num = number_of_intr;
961
962 pm8001_dbg(pm8001_ha, INIT,
963 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
964 rc, pm8001_ha->number_of_intr);
965 return 0;
966 }
967
pm8001_request_msix(struct pm8001_hba_info * pm8001_ha)968 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
969 {
970 u32 i = 0, j = 0;
971 int flag = 0, rc = 0;
972 int nr_irqs = pm8001_ha->number_of_intr;
973
974 if (pm8001_ha->chip_id != chip_8001)
975 flag &= ~IRQF_SHARED;
976
977 pm8001_dbg(pm8001_ha, INIT,
978 "pci_enable_msix request number of intr %d\n",
979 pm8001_ha->number_of_intr);
980
981 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
982 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
983
984 for (i = 0; i < nr_irqs; i++) {
985 snprintf(pm8001_ha->intr_drvname[i],
986 sizeof(pm8001_ha->intr_drvname[0]),
987 "%s-%d", pm8001_ha->name, i);
988 pm8001_ha->irq_vector[i].irq_id = i;
989 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
990
991 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
992 pm8001_interrupt_handler_msix, flag,
993 pm8001_ha->intr_drvname[i],
994 &(pm8001_ha->irq_vector[i]));
995 if (rc) {
996 for (j = 0; j < i; j++) {
997 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
998 &(pm8001_ha->irq_vector[i]));
999 }
1000 pci_free_irq_vectors(pm8001_ha->pdev);
1001 break;
1002 }
1003 }
1004
1005 return rc;
1006 }
1007 #endif
1008
pm8001_setup_irq(struct pm8001_hba_info * pm8001_ha)1009 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1010 {
1011 struct pci_dev *pdev;
1012
1013 pdev = pm8001_ha->pdev;
1014
1015 #ifdef PM8001_USE_MSIX
1016 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1017 return pm8001_setup_msix(pm8001_ha);
1018 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1019 #endif
1020 return 0;
1021 }
1022
1023 /**
1024 * pm8001_request_irq - register interrupt
1025 * @pm8001_ha: our ha struct.
1026 */
pm8001_request_irq(struct pm8001_hba_info * pm8001_ha)1027 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1028 {
1029 struct pci_dev *pdev;
1030 int rc;
1031
1032 pdev = pm8001_ha->pdev;
1033
1034 #ifdef PM8001_USE_MSIX
1035 if (pdev->msix_cap && pci_msi_enabled())
1036 return pm8001_request_msix(pm8001_ha);
1037 else {
1038 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1039 goto intx;
1040 }
1041 #endif
1042
1043 intx:
1044 /* initialize the INT-X interrupt */
1045 pm8001_ha->irq_vector[0].irq_id = 0;
1046 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1047 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1048 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1049 return rc;
1050 }
1051
1052 /**
1053 * pm8001_pci_probe - probe supported device
1054 * @pdev: pci device which kernel has been prepared for.
1055 * @ent: pci device id
1056 *
1057 * This function is the main initialization function, when register a new
1058 * pci driver it is invoked, all struct and hardware initialization should be
1059 * done here, also, register interrupt.
1060 */
pm8001_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1061 static int pm8001_pci_probe(struct pci_dev *pdev,
1062 const struct pci_device_id *ent)
1063 {
1064 unsigned int rc;
1065 u32 pci_reg;
1066 u8 i = 0;
1067 struct pm8001_hba_info *pm8001_ha;
1068 struct Scsi_Host *shost = NULL;
1069 const struct pm8001_chip_info *chip;
1070 struct sas_ha_struct *sha;
1071
1072 dev_printk(KERN_INFO, &pdev->dev,
1073 "pm80xx: driver version %s\n", DRV_VERSION);
1074 rc = pci_enable_device(pdev);
1075 if (rc)
1076 goto err_out_enable;
1077 pci_set_master(pdev);
1078 /*
1079 * Enable pci slot busmaster by setting pci command register.
1080 * This is required by FW for Cyclone card.
1081 */
1082
1083 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1084 pci_reg |= 0x157;
1085 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1086 rc = pci_request_regions(pdev, DRV_NAME);
1087 if (rc)
1088 goto err_out_disable;
1089 rc = pci_go_44(pdev);
1090 if (rc)
1091 goto err_out_regions;
1092
1093 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1094 if (!shost) {
1095 rc = -ENOMEM;
1096 goto err_out_regions;
1097 }
1098 chip = &pm8001_chips[ent->driver_data];
1099 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1100 if (!sha) {
1101 rc = -ENOMEM;
1102 goto err_out_free_host;
1103 }
1104 SHOST_TO_SAS_HA(shost) = sha;
1105
1106 rc = pm8001_prep_sas_ha_init(shost, chip);
1107 if (rc) {
1108 rc = -ENOMEM;
1109 goto err_out_free;
1110 }
1111 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1112 /* ent->driver variable is used to differentiate between controllers */
1113 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1114 if (!pm8001_ha) {
1115 rc = -ENOMEM;
1116 goto err_out_free;
1117 }
1118
1119 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1120 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1121 if (rc) {
1122 pm8001_dbg(pm8001_ha, FAIL,
1123 "chip_init failed [ret: %d]\n", rc);
1124 goto err_out_ha_free;
1125 }
1126
1127 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1128 if (rc)
1129 goto err_out_enable;
1130
1131 rc = scsi_add_host(shost, &pdev->dev);
1132 if (rc)
1133 goto err_out_ha_free;
1134
1135 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1136 if (pm8001_ha->chip_id != chip_8001) {
1137 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1138 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1139 /* setup thermal configuration. */
1140 pm80xx_set_thermal_config(pm8001_ha);
1141 }
1142
1143 pm8001_init_sas_add(pm8001_ha);
1144 /* phy setting support for motherboard controller */
1145 rc = pm8001_configure_phy_settings(pm8001_ha);
1146 if (rc)
1147 goto err_out_shost;
1148
1149 pm8001_post_sas_ha_init(shost, chip);
1150 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1151 if (rc) {
1152 pm8001_dbg(pm8001_ha, FAIL,
1153 "sas_register_ha failed [ret: %d]\n", rc);
1154 goto err_out_shost;
1155 }
1156 list_add_tail(&pm8001_ha->list, &hba_list);
1157 pm8001_ha->flags = PM8001F_RUN_TIME;
1158 scsi_scan_host(pm8001_ha->shost);
1159 return 0;
1160
1161 err_out_shost:
1162 scsi_remove_host(pm8001_ha->shost);
1163 err_out_ha_free:
1164 pm8001_free(pm8001_ha);
1165 err_out_free:
1166 kfree(sha);
1167 err_out_free_host:
1168 scsi_host_put(shost);
1169 err_out_regions:
1170 pci_release_regions(pdev);
1171 err_out_disable:
1172 pci_disable_device(pdev);
1173 err_out_enable:
1174 return rc;
1175 }
1176
1177 /**
1178 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1179 * @pm8001_ha: our hba card information.
1180 * @shost: scsi host which has been allocated outside.
1181 * @pdev: pci device.
1182 */
1183 static int
pm8001_init_ccb_tag(struct pm8001_hba_info * pm8001_ha,struct Scsi_Host * shost,struct pci_dev * pdev)1184 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1185 struct pci_dev *pdev)
1186 {
1187 int i = 0;
1188 u32 max_out_io, ccb_count;
1189 u32 can_queue;
1190
1191 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1192 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1193
1194 /* Update to the scsi host*/
1195 can_queue = ccb_count - PM8001_RESERVE_SLOT;
1196 shost->can_queue = can_queue;
1197
1198 pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL);
1199 if (!pm8001_ha->tags)
1200 goto err_out;
1201
1202 /* Memory region for ccb_info*/
1203 pm8001_ha->ccb_count = ccb_count;
1204 pm8001_ha->ccb_info =
1205 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1206 if (!pm8001_ha->ccb_info) {
1207 pm8001_dbg(pm8001_ha, FAIL,
1208 "Unable to allocate memory for ccb\n");
1209 goto err_out_noccb;
1210 }
1211 for (i = 0; i < ccb_count; i++) {
1212 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1213 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1214 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1215 GFP_KERNEL);
1216 if (!pm8001_ha->ccb_info[i].buf_prd) {
1217 pm8001_dbg(pm8001_ha, FAIL,
1218 "ccb prd memory allocation error\n");
1219 goto err_out;
1220 }
1221 pm8001_ha->ccb_info[i].task = NULL;
1222 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1223 pm8001_ha->ccb_info[i].device = NULL;
1224 ++pm8001_ha->tags_num;
1225 }
1226
1227 return 0;
1228
1229 err_out_noccb:
1230 kfree(pm8001_ha->devices);
1231 err_out:
1232 return -ENOMEM;
1233 }
1234
pm8001_pci_remove(struct pci_dev * pdev)1235 static void pm8001_pci_remove(struct pci_dev *pdev)
1236 {
1237 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1238 struct pm8001_hba_info *pm8001_ha;
1239 int i, j;
1240 pm8001_ha = sha->lldd_ha;
1241 sas_unregister_ha(sha);
1242 sas_remove_host(pm8001_ha->shost);
1243 list_del(&pm8001_ha->list);
1244 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1245 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1246
1247 #ifdef PM8001_USE_MSIX
1248 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1249 synchronize_irq(pci_irq_vector(pdev, i));
1250 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1251 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1252 pci_free_irq_vectors(pdev);
1253 #else
1254 free_irq(pm8001_ha->irq, sha);
1255 #endif
1256 #ifdef PM8001_USE_TASKLET
1257 /* For non-msix and msix interrupts */
1258 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1259 (pm8001_ha->chip_id == chip_8001))
1260 tasklet_kill(&pm8001_ha->tasklet[0]);
1261 else
1262 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1263 tasklet_kill(&pm8001_ha->tasklet[j]);
1264 #endif
1265 scsi_host_put(pm8001_ha->shost);
1266
1267 for (i = 0; i < pm8001_ha->ccb_count; i++) {
1268 dma_free_coherent(&pm8001_ha->pdev->dev,
1269 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1270 pm8001_ha->ccb_info[i].buf_prd,
1271 pm8001_ha->ccb_info[i].ccb_dma_handle);
1272 }
1273 kfree(pm8001_ha->ccb_info);
1274 kfree(pm8001_ha->devices);
1275
1276 pm8001_free(pm8001_ha);
1277 kfree(sha->sas_phy);
1278 kfree(sha->sas_port);
1279 kfree(sha);
1280 pci_release_regions(pdev);
1281 pci_disable_device(pdev);
1282 }
1283
1284 /**
1285 * pm8001_pci_suspend - power management suspend main entry point
1286 * @dev: Device struct
1287 *
1288 * Return: 0 on success, anything else on error.
1289 */
pm8001_pci_suspend(struct device * dev)1290 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1291 {
1292 struct pci_dev *pdev = to_pci_dev(dev);
1293 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1294 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1295 int i, j;
1296 sas_suspend_ha(sha);
1297 flush_workqueue(pm8001_wq);
1298 scsi_block_requests(pm8001_ha->shost);
1299 if (!pdev->pm_cap) {
1300 dev_err(dev, " PCI PM not supported\n");
1301 return -ENODEV;
1302 }
1303 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1304 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1305 #ifdef PM8001_USE_MSIX
1306 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1307 synchronize_irq(pci_irq_vector(pdev, i));
1308 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1309 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1310 pci_free_irq_vectors(pdev);
1311 #else
1312 free_irq(pm8001_ha->irq, sha);
1313 #endif
1314 #ifdef PM8001_USE_TASKLET
1315 /* For non-msix and msix interrupts */
1316 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1317 (pm8001_ha->chip_id == chip_8001))
1318 tasklet_kill(&pm8001_ha->tasklet[0]);
1319 else
1320 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1321 tasklet_kill(&pm8001_ha->tasklet[j]);
1322 #endif
1323 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1324 "suspended state\n", pdev,
1325 pm8001_ha->name);
1326 return 0;
1327 }
1328
1329 /**
1330 * pm8001_pci_resume - power management resume main entry point
1331 * @dev: Device struct
1332 *
1333 * Return: 0 on success, anything else on error.
1334 */
pm8001_pci_resume(struct device * dev)1335 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1336 {
1337 struct pci_dev *pdev = to_pci_dev(dev);
1338 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1339 struct pm8001_hba_info *pm8001_ha;
1340 int rc;
1341 u8 i = 0, j;
1342 DECLARE_COMPLETION_ONSTACK(completion);
1343
1344 pm8001_ha = sha->lldd_ha;
1345
1346 pm8001_info(pm8001_ha,
1347 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1348 pdev, pm8001_ha->name, pdev->current_state);
1349
1350 rc = pci_go_44(pdev);
1351 if (rc)
1352 goto err_out_disable;
1353 sas_prep_resume_ha(sha);
1354 /* chip soft rst only for spc */
1355 if (pm8001_ha->chip_id == chip_8001) {
1356 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1357 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1358 }
1359 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1360 if (rc)
1361 goto err_out_disable;
1362
1363 /* disable all the interrupt bits */
1364 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1365
1366 rc = pm8001_request_irq(pm8001_ha);
1367 if (rc)
1368 goto err_out_disable;
1369 #ifdef PM8001_USE_TASKLET
1370 /* Tasklet for non msi-x interrupt handler */
1371 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1372 (pm8001_ha->chip_id == chip_8001))
1373 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1374 (unsigned long)&(pm8001_ha->irq_vector[0]));
1375 else
1376 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1377 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1378 (unsigned long)&(pm8001_ha->irq_vector[j]));
1379 #endif
1380 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1381 if (pm8001_ha->chip_id != chip_8001) {
1382 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1383 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1384 }
1385
1386 /* Chip documentation for the 8070 and 8072 SPCv */
1387 /* states that a 500ms minimum delay is required */
1388 /* before issuing commands. Otherwise, the firmware */
1389 /* will enter an unrecoverable state. */
1390
1391 if (pm8001_ha->chip_id == chip_8070 ||
1392 pm8001_ha->chip_id == chip_8072) {
1393 mdelay(500);
1394 }
1395
1396 /* Spin up the PHYs */
1397
1398 pm8001_ha->flags = PM8001F_RUN_TIME;
1399 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1400 pm8001_ha->phy[i].enable_completion = &completion;
1401 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1402 wait_for_completion(&completion);
1403 }
1404 sas_resume_ha(sha);
1405 return 0;
1406
1407 err_out_disable:
1408 scsi_remove_host(pm8001_ha->shost);
1409
1410 return rc;
1411 }
1412
1413 /* update of pci device, vendor id and driver data with
1414 * unique value for each of the controller
1415 */
1416 static struct pci_device_id pm8001_pci_table[] = {
1417 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1418 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1419 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1420 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1421 /* Support for SPC/SPCv/SPCve controllers */
1422 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1423 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1424 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1425 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1426 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1427 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1428 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1429 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1430 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1431 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1432 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1433 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1434 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1435 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1436 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1438 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1440 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1442 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1444 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1445 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1446 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1447 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1448 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1449 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1450 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1451 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1452 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1453 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1454 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1455 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1456 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1458 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1460 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1462 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1464 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1466 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1468 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1470 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1472 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1474 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1475 { PCI_VENDOR_ID_ATTO, 0x8070,
1476 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1477 { PCI_VENDOR_ID_ATTO, 0x8070,
1478 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1479 { PCI_VENDOR_ID_ATTO, 0x8072,
1480 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1481 { PCI_VENDOR_ID_ATTO, 0x8072,
1482 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1483 { PCI_VENDOR_ID_ATTO, 0x8070,
1484 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1485 { PCI_VENDOR_ID_ATTO, 0x8072,
1486 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1487 { PCI_VENDOR_ID_ATTO, 0x8072,
1488 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1489 {} /* terminate list */
1490 };
1491
1492 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1493 pm8001_pci_suspend,
1494 pm8001_pci_resume);
1495
1496 static struct pci_driver pm8001_pci_driver = {
1497 .name = DRV_NAME,
1498 .id_table = pm8001_pci_table,
1499 .probe = pm8001_pci_probe,
1500 .remove = pm8001_pci_remove,
1501 .driver.pm = &pm8001_pci_pm_ops,
1502 };
1503
1504 /**
1505 * pm8001_init - initialize scsi transport template
1506 */
pm8001_init(void)1507 static int __init pm8001_init(void)
1508 {
1509 int rc = -ENOMEM;
1510
1511 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1512 if (!pm8001_wq)
1513 goto err;
1514
1515 pm8001_id = 0;
1516 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1517 if (!pm8001_stt)
1518 goto err_wq;
1519 rc = pci_register_driver(&pm8001_pci_driver);
1520 if (rc)
1521 goto err_tp;
1522 return 0;
1523
1524 err_tp:
1525 sas_release_transport(pm8001_stt);
1526 err_wq:
1527 destroy_workqueue(pm8001_wq);
1528 err:
1529 return rc;
1530 }
1531
pm8001_exit(void)1532 static void __exit pm8001_exit(void)
1533 {
1534 pci_unregister_driver(&pm8001_pci_driver);
1535 sas_release_transport(pm8001_stt);
1536 destroy_workqueue(pm8001_wq);
1537 }
1538
1539 module_init(pm8001_init);
1540 module_exit(pm8001_exit);
1541
1542 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1543 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1544 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1545 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1546 MODULE_DESCRIPTION(
1547 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1548 "SAS/SATA controller driver");
1549 MODULE_VERSION(DRV_VERSION);
1550 MODULE_LICENSE("GPL");
1551 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1552
1553