1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Pinctrl data for the NVIDIA Tegra194 pinmux
4 *
5 * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17 #include <linux/init.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22
23 #include "pinctrl-tegra.h"
24
25 /* Define unique ID for each pins */
26 enum pin_id {
27 TEGRA_PIN_DAP6_SCLK_PA0,
28 TEGRA_PIN_DAP6_DOUT_PA1,
29 TEGRA_PIN_DAP6_DIN_PA2,
30 TEGRA_PIN_DAP6_FS_PA3,
31 TEGRA_PIN_DAP4_SCLK_PA4,
32 TEGRA_PIN_DAP4_DOUT_PA5,
33 TEGRA_PIN_DAP4_DIN_PA6,
34 TEGRA_PIN_DAP4_FS_PA7,
35 TEGRA_PIN_CPU_PWR_REQ_0_PB0,
36 TEGRA_PIN_CPU_PWR_REQ_1_PB1,
37 TEGRA_PIN_QSPI0_SCK_PC0,
38 TEGRA_PIN_QSPI0_CS_N_PC1,
39 TEGRA_PIN_QSPI0_IO0_PC2,
40 TEGRA_PIN_QSPI0_IO1_PC3,
41 TEGRA_PIN_QSPI0_IO2_PC4,
42 TEGRA_PIN_QSPI0_IO3_PC5,
43 TEGRA_PIN_QSPI1_SCK_PC6,
44 TEGRA_PIN_QSPI1_CS_N_PC7,
45 TEGRA_PIN_QSPI1_IO0_PD0,
46 TEGRA_PIN_QSPI1_IO1_PD1,
47 TEGRA_PIN_QSPI1_IO2_PD2,
48 TEGRA_PIN_QSPI1_IO3_PD3,
49 TEGRA_PIN_EQOS_TXC_PE0,
50 TEGRA_PIN_EQOS_TD0_PE1,
51 TEGRA_PIN_EQOS_TD1_PE2,
52 TEGRA_PIN_EQOS_TD2_PE3,
53 TEGRA_PIN_EQOS_TD3_PE4,
54 TEGRA_PIN_EQOS_TX_CTL_PE5,
55 TEGRA_PIN_EQOS_RD0_PE6,
56 TEGRA_PIN_EQOS_RD1_PE7,
57 TEGRA_PIN_EQOS_RD2_PF0,
58 TEGRA_PIN_EQOS_RD3_PF1,
59 TEGRA_PIN_EQOS_RX_CTL_PF2,
60 TEGRA_PIN_EQOS_RXC_PF3,
61 TEGRA_PIN_EQOS_SMA_MDIO_PF4,
62 TEGRA_PIN_EQOS_SMA_MDC_PF5,
63 TEGRA_PIN_SOC_GPIO00_PG0,
64 TEGRA_PIN_SOC_GPIO01_PG1,
65 TEGRA_PIN_SOC_GPIO02_PG2,
66 TEGRA_PIN_SOC_GPIO03_PG3,
67 TEGRA_PIN_SOC_GPIO08_PG4,
68 TEGRA_PIN_SOC_GPIO09_PG5,
69 TEGRA_PIN_SOC_GPIO10_PG6,
70 TEGRA_PIN_SOC_GPIO11_PG7,
71 TEGRA_PIN_SOC_GPIO12_PH0,
72 TEGRA_PIN_SOC_GPIO13_PH1,
73 TEGRA_PIN_SOC_GPIO14_PH2,
74 TEGRA_PIN_UART4_TX_PH3,
75 TEGRA_PIN_UART4_RX_PH4,
76 TEGRA_PIN_UART4_RTS_PH5,
77 TEGRA_PIN_UART4_CTS_PH6,
78 TEGRA_PIN_DAP2_SCLK_PH7,
79 TEGRA_PIN_DAP2_DOUT_PI0,
80 TEGRA_PIN_DAP2_DIN_PI1,
81 TEGRA_PIN_DAP2_FS_PI2,
82 TEGRA_PIN_GEN1_I2C_SCL_PI3,
83 TEGRA_PIN_GEN1_I2C_SDA_PI4,
84 TEGRA_PIN_SDMMC1_CLK_PJ0,
85 TEGRA_PIN_SDMMC1_CMD_PJ1,
86 TEGRA_PIN_SDMMC1_DAT0_PJ2,
87 TEGRA_PIN_SDMMC1_DAT1_PJ3,
88 TEGRA_PIN_SDMMC1_DAT2_PJ4,
89 TEGRA_PIN_SDMMC1_DAT3_PJ5,
90 TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
91 TEGRA_PIN_PEX_L0_RST_N_PK1,
92 TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
93 TEGRA_PIN_PEX_L1_RST_N_PK3,
94 TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
95 TEGRA_PIN_PEX_L2_RST_N_PK5,
96 TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
97 TEGRA_PIN_PEX_L3_RST_N_PK7,
98 TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
99 TEGRA_PIN_PEX_L4_RST_N_PL1,
100 TEGRA_PIN_PEX_WAKE_N_PL2,
101 TEGRA_PIN_SATA_DEV_SLP_PL3,
102 TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
103 TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
104 TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
105 TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
106 TEGRA_PIN_HDMI_CEC_PM4,
107 TEGRA_PIN_SOC_GPIO50_PM5,
108 TEGRA_PIN_SOC_GPIO51_PM6,
109 TEGRA_PIN_SOC_GPIO52_PM7,
110 TEGRA_PIN_SOC_GPIO53_PN0,
111 TEGRA_PIN_SOC_GPIO54_PN1,
112 TEGRA_PIN_SOC_GPIO55_PN2,
113 TEGRA_PIN_SDMMC3_CLK_PO0,
114 TEGRA_PIN_SDMMC3_CMD_PO1,
115 TEGRA_PIN_SDMMC3_DAT0_PO2,
116 TEGRA_PIN_SDMMC3_DAT1_PO3,
117 TEGRA_PIN_SDMMC3_DAT2_PO4,
118 TEGRA_PIN_SDMMC3_DAT3_PO5,
119 TEGRA_PIN_EXTPERIPH1_CLK_PP0,
120 TEGRA_PIN_EXTPERIPH2_CLK_PP1,
121 TEGRA_PIN_CAM_I2C_SCL_PP2,
122 TEGRA_PIN_CAM_I2C_SDA_PP3,
123 TEGRA_PIN_SOC_GPIO04_PP4,
124 TEGRA_PIN_SOC_GPIO05_PP5,
125 TEGRA_PIN_SOC_GPIO06_PP6,
126 TEGRA_PIN_SOC_GPIO07_PP7,
127 TEGRA_PIN_SOC_GPIO20_PQ0,
128 TEGRA_PIN_SOC_GPIO21_PQ1,
129 TEGRA_PIN_SOC_GPIO22_PQ2,
130 TEGRA_PIN_SOC_GPIO23_PQ3,
131 TEGRA_PIN_SOC_GPIO40_PQ4,
132 TEGRA_PIN_SOC_GPIO41_PQ5,
133 TEGRA_PIN_SOC_GPIO42_PQ6,
134 TEGRA_PIN_SOC_GPIO43_PQ7,
135 TEGRA_PIN_SOC_GPIO44_PR0,
136 TEGRA_PIN_SOC_GPIO45_PR1,
137 TEGRA_PIN_UART1_TX_PR2,
138 TEGRA_PIN_UART1_RX_PR3,
139 TEGRA_PIN_UART1_RTS_PR4,
140 TEGRA_PIN_UART1_CTS_PR5,
141 TEGRA_PIN_DAP1_SCLK_PS0,
142 TEGRA_PIN_DAP1_DOUT_PS1,
143 TEGRA_PIN_DAP1_DIN_PS2,
144 TEGRA_PIN_DAP1_FS_PS3,
145 TEGRA_PIN_AUD_MCLK_PS4,
146 TEGRA_PIN_SOC_GPIO30_PS5,
147 TEGRA_PIN_SOC_GPIO31_PS6,
148 TEGRA_PIN_SOC_GPIO32_PS7,
149 TEGRA_PIN_SOC_GPIO33_PT0,
150 TEGRA_PIN_DAP3_SCLK_PT1,
151 TEGRA_PIN_DAP3_DOUT_PT2,
152 TEGRA_PIN_DAP3_DIN_PT3,
153 TEGRA_PIN_DAP3_FS_PT4,
154 TEGRA_PIN_DAP5_SCLK_PT5,
155 TEGRA_PIN_DAP5_DOUT_PT6,
156 TEGRA_PIN_DAP5_DIN_PT7,
157 TEGRA_PIN_DAP5_FS_PU0,
158 TEGRA_PIN_DIRECTDC1_CLK_PV0,
159 TEGRA_PIN_DIRECTDC1_IN_PV1,
160 TEGRA_PIN_DIRECTDC1_OUT0_PV2,
161 TEGRA_PIN_DIRECTDC1_OUT1_PV3,
162 TEGRA_PIN_DIRECTDC1_OUT2_PV4,
163 TEGRA_PIN_DIRECTDC1_OUT3_PV5,
164 TEGRA_PIN_DIRECTDC1_OUT4_PV6,
165 TEGRA_PIN_DIRECTDC1_OUT5_PV7,
166 TEGRA_PIN_DIRECTDC1_OUT6_PW0,
167 TEGRA_PIN_DIRECTDC1_OUT7_PW1,
168 TEGRA_PIN_GPU_PWR_REQ_PX0,
169 TEGRA_PIN_CV_PWR_REQ_PX1,
170 TEGRA_PIN_GP_PWM2_PX2,
171 TEGRA_PIN_GP_PWM3_PX3,
172 TEGRA_PIN_UART2_TX_PX4,
173 TEGRA_PIN_UART2_RX_PX5,
174 TEGRA_PIN_UART2_RTS_PX6,
175 TEGRA_PIN_UART2_CTS_PX7,
176 TEGRA_PIN_SPI3_SCK_PY0,
177 TEGRA_PIN_SPI3_MISO_PY1,
178 TEGRA_PIN_SPI3_MOSI_PY2,
179 TEGRA_PIN_SPI3_CS0_PY3,
180 TEGRA_PIN_SPI3_CS1_PY4,
181 TEGRA_PIN_UART5_TX_PY5,
182 TEGRA_PIN_UART5_RX_PY6,
183 TEGRA_PIN_UART5_RTS_PY7,
184 TEGRA_PIN_UART5_CTS_PZ0,
185 TEGRA_PIN_USB_VBUS_EN0_PZ1,
186 TEGRA_PIN_USB_VBUS_EN1_PZ2,
187 TEGRA_PIN_SPI1_SCK_PZ3,
188 TEGRA_PIN_SPI1_MISO_PZ4,
189 TEGRA_PIN_SPI1_MOSI_PZ5,
190 TEGRA_PIN_SPI1_CS0_PZ6,
191 TEGRA_PIN_SPI1_CS1_PZ7,
192 TEGRA_PIN_CAN1_DOUT_PAA0,
193 TEGRA_PIN_CAN1_DIN_PAA1,
194 TEGRA_PIN_CAN0_DOUT_PAA2,
195 TEGRA_PIN_CAN0_DIN_PAA3,
196 TEGRA_PIN_CAN0_STB_PAA4,
197 TEGRA_PIN_CAN0_EN_PAA5,
198 TEGRA_PIN_CAN0_WAKE_PAA6,
199 TEGRA_PIN_CAN0_ERR_PAA7,
200 TEGRA_PIN_CAN1_STB_PBB0,
201 TEGRA_PIN_CAN1_EN_PBB1,
202 TEGRA_PIN_CAN1_WAKE_PBB2,
203 TEGRA_PIN_CAN1_ERR_PBB3,
204 TEGRA_PIN_SPI2_SCK_PCC0,
205 TEGRA_PIN_SPI2_MISO_PCC1,
206 TEGRA_PIN_SPI2_MOSI_PCC2,
207 TEGRA_PIN_SPI2_CS0_PCC3,
208 TEGRA_PIN_TOUCH_CLK_PCC4,
209 TEGRA_PIN_UART3_TX_PCC5,
210 TEGRA_PIN_UART3_RX_PCC6,
211 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
212 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
213 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
214 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
215 TEGRA_PIN_SAFE_STATE_PEE0,
216 TEGRA_PIN_VCOMP_ALERT_PEE1,
217 TEGRA_PIN_AO_RETENTION_N_PEE2,
218 TEGRA_PIN_BATT_OC_PEE3,
219 TEGRA_PIN_POWER_ON_PEE4,
220 TEGRA_PIN_PWR_I2C_SCL_PEE5,
221 TEGRA_PIN_PWR_I2C_SDA_PEE6,
222 TEGRA_PIN_UFS0_REF_CLK_PFF0,
223 TEGRA_PIN_UFS0_RST_PFF1,
224 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
225 TEGRA_PIN_PEX_L5_RST_N_PGG1,
226 TEGRA_PIN_DIRECTDC_COMP,
227 TEGRA_PIN_SDMMC4_CLK,
228 TEGRA_PIN_SDMMC4_CMD,
229 TEGRA_PIN_SDMMC4_DQS,
230 TEGRA_PIN_SDMMC4_DAT7,
231 TEGRA_PIN_SDMMC4_DAT6,
232 TEGRA_PIN_SDMMC4_DAT5,
233 TEGRA_PIN_SDMMC4_DAT4,
234 TEGRA_PIN_SDMMC4_DAT3,
235 TEGRA_PIN_SDMMC4_DAT2,
236 TEGRA_PIN_SDMMC4_DAT1,
237 TEGRA_PIN_SDMMC4_DAT0,
238 TEGRA_PIN_SDMMC1_COMP,
239 TEGRA_PIN_SDMMC1_HV_TRIM,
240 TEGRA_PIN_SDMMC3_COMP,
241 TEGRA_PIN_SDMMC3_HV_TRIM,
242 TEGRA_PIN_EQOS_COMP,
243 TEGRA_PIN_QSPI_COMP,
244 TEGRA_PIN_SYS_RESET_N,
245 TEGRA_PIN_SHUTDOWN_N,
246 TEGRA_PIN_PMU_INT_N,
247 TEGRA_PIN_SOC_PWR_REQ,
248 TEGRA_PIN_CLK_32K_IN,
249 };
250
251 /* Table for pin descriptor */
252 static const struct pinctrl_pin_desc tegra194_pins[] = {
253 PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),
254 PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),
255 PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),
256 PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),
257 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),
258 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),
259 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),
260 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),
261 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_0_PB0, "CPU_PWR_REQ_0_PB0"),
262 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_1_PB1, "CPU_PWR_REQ_1_PB1"),
263 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),
264 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),
265 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),
266 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),
267 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),
268 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),
269 PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),
270 PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),
271 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),
272 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),
273 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),
274 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),
275 PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
276 PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
277 PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
278 PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
279 PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
280 PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
281 PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
282 PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
283 PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
284 PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
285 PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
286 PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
287 PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),
288 PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),
289 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PG0, "SOC_GPIO00_PG0"),
290 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO01_PG1, "SOC_GPIO01_PG1"),
291 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO02_PG2, "SOC_GPIO02_PG2"),
292 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO03_PG3, "SOC_GPIO03_PG3"),
293 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PG4, "SOC_GPIO08_PG4"),
294 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PG5, "SOC_GPIO09_PG5"),
295 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO10_PG6, "SOC_GPIO10_PG6"),
296 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO11_PG7, "SOC_GPIO11_PG7"),
297 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO12_PH0, "SOC_GPIO12_PH0"),
298 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PH1, "SOC_GPIO13_PH1"),
299 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PH2, "SOC_GPIO14_PH2"),
300 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),
301 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),
302 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),
303 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),
304 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PH7, "DAP2_SCLK_PH7"),
305 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PI0, "DAP2_DOUT_PI0"),
306 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PI1, "DAP2_DIN_PI1"),
307 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PI2, "DAP2_FS_PI2"),
308 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),
309 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),
310 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),
311 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),
312 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),
313 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),
314 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),
315 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),
316 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),
317 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),
318 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),
319 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),
320 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),
321 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),
322 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),
323 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),
324 PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),
325 PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),
326 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),
327 PINCTRL_PIN(TEGRA_PIN_SATA_DEV_SLP_PL3, "SATA_DEV_SLP_PL3"),
328 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),
329 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),
330 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),
331 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),
332 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PM4, "HDMI_CEC_PM4"),
333 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PM5, "SOC_GPIO50_PM5"),
334 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO51_PM6, "SOC_GPIO51_PM6"),
335 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO52_PM7, "SOC_GPIO52_PM7"),
336 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PN0, "SOC_GPIO53_PN0"),
337 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO54_PN1, "SOC_GPIO54_PN1"),
338 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PN2, "SOC_GPIO55_PN2"),
339 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PO0, "SDMMC3_CLK_PO0"),
340 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PO1, "SDMMC3_CMD_PO1"),
341 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PO2, "SDMMC3_DAT0_PO2"),
342 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PO3, "SDMMC3_DAT1_PO3"),
343 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PO4, "SDMMC3_DAT2_PO4"),
344 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PO5, "SDMMC3_DAT3_PO5"),
345 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),
346 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),
347 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),
348 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),
349 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PP4, "SOC_GPIO04_PP4"),
350 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO05_PP5, "SOC_GPIO05_PP5"),
351 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PP6, "SOC_GPIO06_PP6"),
352 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PP7, "SOC_GPIO07_PP7"),
353 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PQ0, "SOC_GPIO20_PQ0"),
354 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PQ1, "SOC_GPIO21_PQ1"),
355 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PQ2, "SOC_GPIO22_PQ2"),
356 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PQ3, "SOC_GPIO23_PQ3"),
357 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PQ4, "SOC_GPIO40_PQ4"),
358 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PQ5, "SOC_GPIO41_PQ5"),
359 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PQ6, "SOC_GPIO42_PQ6"),
360 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PQ7, "SOC_GPIO43_PQ7"),
361 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PR0, "SOC_GPIO44_PR0"),
362 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PR1, "SOC_GPIO45_PR1"),
363 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),
364 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),
365 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),
366 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),
367 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PS0, "DAP1_SCLK_PS0"),
368 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PS1, "DAP1_DOUT_PS1"),
369 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PS2, "DAP1_DIN_PS2"),
370 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PS3, "DAP1_FS_PS3"),
371 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PS4, "AUD_MCLK_PS4"),
372 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PS5, "SOC_GPIO30_PS5"),
373 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PS6, "SOC_GPIO31_PS6"),
374 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PS7, "SOC_GPIO32_PS7"),
375 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PT0, "SOC_GPIO33_PT0"),
376 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PT1, "DAP3_SCLK_PT1"),
377 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PT2, "DAP3_DOUT_PT2"),
378 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PT3, "DAP3_DIN_PT3"),
379 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PT4, "DAP3_FS_PT4"),
380 PINCTRL_PIN(TEGRA_PIN_DAP5_SCLK_PT5, "DAP5_SCLK_PT5"),
381 PINCTRL_PIN(TEGRA_PIN_DAP5_DOUT_PT6, "DAP5_DOUT_PT6"),
382 PINCTRL_PIN(TEGRA_PIN_DAP5_DIN_PT7, "DAP5_DIN_PT7"),
383 PINCTRL_PIN(TEGRA_PIN_DAP5_FS_PU0, "DAP5_FS_PU0"),
384 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PV0, "DIRECTDC1_CLK_PV0"),
385 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PV1, "DIRECTDC1_IN_PV1"),
386 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PV2, "DIRECTDC1_OUT0_PV2"),
387 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PV3, "DIRECTDC1_OUT1_PV3"),
388 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PV4, "DIRECTDC1_OUT2_PV4"),
389 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PV5, "DIRECTDC1_OUT3_PV5"),
390 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT4_PV6, "DIRECTDC1_OUT4_PV6"),
391 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT5_PV7, "DIRECTDC1_OUT5_PV7"),
392 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT6_PW0, "DIRECTDC1_OUT6_PW0"),
393 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT7_PW1, "DIRECTDC1_OUT7_PW1"),
394 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),
395 PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),
396 PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),
397 PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),
398 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),
399 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),
400 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),
401 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),
402 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),
403 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),
404 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),
405 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),
406 PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),
407 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),
408 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),
409 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),
410 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),
411 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),
412 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),
413 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),
414 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),
415 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
416 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
417 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
418 PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
419 PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
420 PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
421 PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
422 PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
423 PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
424 PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
425 PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
426 PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
427 PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
428 PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
429 PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
430 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
431 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
432 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
433 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
434 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
435 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
436 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
437 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
438 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
439 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
440 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
441 PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
442 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
443 PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
444 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
445 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
446 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
447 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
448 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),
449 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),
450 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
451 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
452 PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
453 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK, "SDMMC4_CLK"),
454 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD, "SDMMC4_CMD"),
455 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DQS, "SDMMC4_DQS"),
456 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7, "SDMMC4_DAT7"),
457 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6, "SDMMC4_DAT6"),
458 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5, "SDMMC4_DAT5"),
459 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4, "SDMMC4_DAT4"),
460 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3, "SDMMC4_DAT3"),
461 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2, "SDMMC4_DAT2"),
462 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1, "SDMMC4_DAT1"),
463 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0, "SDMMC4_DAT0"),
464 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
465 PINCTRL_PIN(TEGRA_PIN_SDMMC1_HV_TRIM, "SDMMC1_HV_TRIM"),
466 PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
467 PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),
468 PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
469 PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
470 PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
471 PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
472 PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
473 PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
474 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
475 };
476
477 static const unsigned int dap6_sclk_pa0_pins[] = {
478 TEGRA_PIN_DAP6_SCLK_PA0,
479 };
480 static const unsigned int dap6_dout_pa1_pins[] = {
481 TEGRA_PIN_DAP6_DOUT_PA1,
482 };
483 static const unsigned int dap6_din_pa2_pins[] = {
484 TEGRA_PIN_DAP6_DIN_PA2,
485 };
486 static const unsigned int dap6_fs_pa3_pins[] = {
487 TEGRA_PIN_DAP6_FS_PA3,
488 };
489 static const unsigned int dap4_sclk_pa4_pins[] = {
490 TEGRA_PIN_DAP4_SCLK_PA4,
491 };
492 static const unsigned int dap4_dout_pa5_pins[] = {
493 TEGRA_PIN_DAP4_DOUT_PA5,
494 };
495 static const unsigned int dap4_din_pa6_pins[] = {
496 TEGRA_PIN_DAP4_DIN_PA6,
497 };
498 static const unsigned int dap4_fs_pa7_pins[] = {
499 TEGRA_PIN_DAP4_FS_PA7,
500 };
501 static const unsigned int cpu_pwr_req_0_pb0_pins[] = {
502 TEGRA_PIN_CPU_PWR_REQ_0_PB0,
503 };
504 static const unsigned int cpu_pwr_req_1_pb1_pins[] = {
505 TEGRA_PIN_CPU_PWR_REQ_1_PB1,
506 };
507 static const unsigned int qspi0_sck_pc0_pins[] = {
508 TEGRA_PIN_QSPI0_SCK_PC0,
509 };
510 static const unsigned int qspi0_cs_n_pc1_pins[] = {
511 TEGRA_PIN_QSPI0_CS_N_PC1,
512 };
513 static const unsigned int qspi0_io0_pc2_pins[] = {
514 TEGRA_PIN_QSPI0_IO0_PC2,
515 };
516 static const unsigned int qspi0_io1_pc3_pins[] = {
517 TEGRA_PIN_QSPI0_IO1_PC3,
518 };
519 static const unsigned int qspi0_io2_pc4_pins[] = {
520 TEGRA_PIN_QSPI0_IO2_PC4,
521 };
522 static const unsigned int qspi0_io3_pc5_pins[] = {
523 TEGRA_PIN_QSPI0_IO3_PC5,
524 };
525 static const unsigned int qspi1_sck_pc6_pins[] = {
526 TEGRA_PIN_QSPI1_SCK_PC6,
527 };
528 static const unsigned int qspi1_cs_n_pc7_pins[] = {
529 TEGRA_PIN_QSPI1_CS_N_PC7,
530 };
531 static const unsigned int qspi1_io0_pd0_pins[] = {
532 TEGRA_PIN_QSPI1_IO0_PD0,
533 };
534 static const unsigned int qspi1_io1_pd1_pins[] = {
535 TEGRA_PIN_QSPI1_IO1_PD1,
536 };
537 static const unsigned int qspi1_io2_pd2_pins[] = {
538 TEGRA_PIN_QSPI1_IO2_PD2,
539 };
540 static const unsigned int qspi1_io3_pd3_pins[] = {
541 TEGRA_PIN_QSPI1_IO3_PD3,
542 };
543 static const unsigned int eqos_txc_pe0_pins[] = {
544 TEGRA_PIN_EQOS_TXC_PE0,
545 };
546 static const unsigned int eqos_td0_pe1_pins[] = {
547 TEGRA_PIN_EQOS_TD0_PE1,
548 };
549 static const unsigned int eqos_td1_pe2_pins[] = {
550 TEGRA_PIN_EQOS_TD1_PE2,
551 };
552 static const unsigned int eqos_td2_pe3_pins[] = {
553 TEGRA_PIN_EQOS_TD2_PE3,
554 };
555 static const unsigned int eqos_td3_pe4_pins[] = {
556 TEGRA_PIN_EQOS_TD3_PE4,
557 };
558 static const unsigned int eqos_tx_ctl_pe5_pins[] = {
559 TEGRA_PIN_EQOS_TX_CTL_PE5,
560 };
561 static const unsigned int eqos_rd0_pe6_pins[] = {
562 TEGRA_PIN_EQOS_RD0_PE6,
563 };
564 static const unsigned int eqos_rd1_pe7_pins[] = {
565 TEGRA_PIN_EQOS_RD1_PE7,
566 };
567 static const unsigned int eqos_rd2_pf0_pins[] = {
568 TEGRA_PIN_EQOS_RD2_PF0,
569 };
570 static const unsigned int eqos_rd3_pf1_pins[] = {
571 TEGRA_PIN_EQOS_RD3_PF1,
572 };
573 static const unsigned int eqos_rx_ctl_pf2_pins[] = {
574 TEGRA_PIN_EQOS_RX_CTL_PF2,
575 };
576 static const unsigned int eqos_rxc_pf3_pins[] = {
577 TEGRA_PIN_EQOS_RXC_PF3,
578 };
579 static const unsigned int eqos_sma_mdio_pf4_pins[] = {
580 TEGRA_PIN_EQOS_SMA_MDIO_PF4,
581 };
582 static const unsigned int eqos_sma_mdc_pf5_pins[] = {
583 TEGRA_PIN_EQOS_SMA_MDC_PF5,
584 };
585 static const unsigned int soc_gpio00_pg0_pins[] = {
586 TEGRA_PIN_SOC_GPIO00_PG0,
587 };
588 static const unsigned int soc_gpio01_pg1_pins[] = {
589 TEGRA_PIN_SOC_GPIO01_PG1,
590 };
591 static const unsigned int soc_gpio02_pg2_pins[] = {
592 TEGRA_PIN_SOC_GPIO02_PG2,
593 };
594 static const unsigned int soc_gpio03_pg3_pins[] = {
595 TEGRA_PIN_SOC_GPIO03_PG3,
596 };
597 static const unsigned int soc_gpio08_pg4_pins[] = {
598 TEGRA_PIN_SOC_GPIO08_PG4,
599 };
600 static const unsigned int soc_gpio09_pg5_pins[] = {
601 TEGRA_PIN_SOC_GPIO09_PG5,
602 };
603 static const unsigned int soc_gpio10_pg6_pins[] = {
604 TEGRA_PIN_SOC_GPIO10_PG6,
605 };
606 static const unsigned int soc_gpio11_pg7_pins[] = {
607 TEGRA_PIN_SOC_GPIO11_PG7,
608 };
609 static const unsigned int soc_gpio12_ph0_pins[] = {
610 TEGRA_PIN_SOC_GPIO12_PH0,
611 };
612 static const unsigned int soc_gpio13_ph1_pins[] = {
613 TEGRA_PIN_SOC_GPIO13_PH1,
614 };
615 static const unsigned int soc_gpio14_ph2_pins[] = {
616 TEGRA_PIN_SOC_GPIO14_PH2,
617 };
618 static const unsigned int uart4_tx_ph3_pins[] = {
619 TEGRA_PIN_UART4_TX_PH3,
620 };
621 static const unsigned int uart4_rx_ph4_pins[] = {
622 TEGRA_PIN_UART4_RX_PH4,
623 };
624 static const unsigned int uart4_rts_ph5_pins[] = {
625 TEGRA_PIN_UART4_RTS_PH5,
626 };
627 static const unsigned int uart4_cts_ph6_pins[] = {
628 TEGRA_PIN_UART4_CTS_PH6,
629 };
630 static const unsigned int dap2_sclk_ph7_pins[] = {
631 TEGRA_PIN_DAP2_SCLK_PH7,
632 };
633 static const unsigned int dap2_dout_pi0_pins[] = {
634 TEGRA_PIN_DAP2_DOUT_PI0,
635 };
636 static const unsigned int dap2_din_pi1_pins[] = {
637 TEGRA_PIN_DAP2_DIN_PI1,
638 };
639 static const unsigned int dap2_fs_pi2_pins[] = {
640 TEGRA_PIN_DAP2_FS_PI2,
641 };
642 static const unsigned int gen1_i2c_scl_pi3_pins[] = {
643 TEGRA_PIN_GEN1_I2C_SCL_PI3,
644 };
645 static const unsigned int gen1_i2c_sda_pi4_pins[] = {
646 TEGRA_PIN_GEN1_I2C_SDA_PI4,
647 };
648 static const unsigned int sdmmc1_clk_pj0_pins[] = {
649 TEGRA_PIN_SDMMC1_CLK_PJ0,
650 };
651 static const unsigned int sdmmc1_cmd_pj1_pins[] = {
652 TEGRA_PIN_SDMMC1_CMD_PJ1,
653 };
654 static const unsigned int sdmmc1_dat0_pj2_pins[] = {
655 TEGRA_PIN_SDMMC1_DAT0_PJ2,
656 };
657 static const unsigned int sdmmc1_dat1_pj3_pins[] = {
658 TEGRA_PIN_SDMMC1_DAT1_PJ3,
659 };
660 static const unsigned int sdmmc1_dat2_pj4_pins[] = {
661 TEGRA_PIN_SDMMC1_DAT2_PJ4,
662 };
663 static const unsigned int sdmmc1_dat3_pj5_pins[] = {
664 TEGRA_PIN_SDMMC1_DAT3_PJ5,
665 };
666 static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {
667 TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
668 };
669 static const unsigned int pex_l0_rst_n_pk1_pins[] = {
670 TEGRA_PIN_PEX_L0_RST_N_PK1,
671 };
672 static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {
673 TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
674 };
675 static const unsigned int pex_l1_rst_n_pk3_pins[] = {
676 TEGRA_PIN_PEX_L1_RST_N_PK3,
677 };
678 static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {
679 TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
680 };
681 static const unsigned int pex_l2_rst_n_pk5_pins[] = {
682 TEGRA_PIN_PEX_L2_RST_N_PK5,
683 };
684 static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {
685 TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
686 };
687 static const unsigned int pex_l3_rst_n_pk7_pins[] = {
688 TEGRA_PIN_PEX_L3_RST_N_PK7,
689 };
690 static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {
691 TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
692 };
693 static const unsigned int pex_l4_rst_n_pl1_pins[] = {
694 TEGRA_PIN_PEX_L4_RST_N_PL1,
695 };
696 static const unsigned int pex_wake_n_pl2_pins[] = {
697 TEGRA_PIN_PEX_WAKE_N_PL2,
698 };
699 static const unsigned int sata_dev_slp_pl3_pins[] = {
700 TEGRA_PIN_SATA_DEV_SLP_PL3,
701 };
702 static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {
703 TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
704 };
705 static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {
706 TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
707 };
708 static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {
709 TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
710 };
711 static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {
712 TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
713 };
714 static const unsigned int hdmi_cec_pm4_pins[] = {
715 TEGRA_PIN_HDMI_CEC_PM4,
716 };
717 static const unsigned int soc_gpio50_pm5_pins[] = {
718 TEGRA_PIN_SOC_GPIO50_PM5,
719 };
720 static const unsigned int soc_gpio51_pm6_pins[] = {
721 TEGRA_PIN_SOC_GPIO51_PM6,
722 };
723 static const unsigned int soc_gpio52_pm7_pins[] = {
724 TEGRA_PIN_SOC_GPIO52_PM7,
725 };
726 static const unsigned int soc_gpio53_pn0_pins[] = {
727 TEGRA_PIN_SOC_GPIO53_PN0,
728 };
729 static const unsigned int soc_gpio54_pn1_pins[] = {
730 TEGRA_PIN_SOC_GPIO54_PN1,
731 };
732 static const unsigned int soc_gpio55_pn2_pins[] = {
733 TEGRA_PIN_SOC_GPIO55_PN2,
734 };
735 static const unsigned int sdmmc3_clk_po0_pins[] = {
736 TEGRA_PIN_SDMMC3_CLK_PO0,
737 };
738 static const unsigned int sdmmc3_cmd_po1_pins[] = {
739 TEGRA_PIN_SDMMC3_CMD_PO1,
740 };
741 static const unsigned int sdmmc3_dat0_po2_pins[] = {
742 TEGRA_PIN_SDMMC3_DAT0_PO2,
743 };
744 static const unsigned int sdmmc3_dat1_po3_pins[] = {
745 TEGRA_PIN_SDMMC3_DAT1_PO3,
746 };
747 static const unsigned int sdmmc3_dat2_po4_pins[] = {
748 TEGRA_PIN_SDMMC3_DAT2_PO4,
749 };
750 static const unsigned int sdmmc3_dat3_po5_pins[] = {
751 TEGRA_PIN_SDMMC3_DAT3_PO5,
752 };
753 static const unsigned int extperiph1_clk_pp0_pins[] = {
754 TEGRA_PIN_EXTPERIPH1_CLK_PP0,
755 };
756 static const unsigned int extperiph2_clk_pp1_pins[] = {
757 TEGRA_PIN_EXTPERIPH2_CLK_PP1,
758 };
759 static const unsigned int cam_i2c_scl_pp2_pins[] = {
760 TEGRA_PIN_CAM_I2C_SCL_PP2,
761 };
762 static const unsigned int cam_i2c_sda_pp3_pins[] = {
763 TEGRA_PIN_CAM_I2C_SDA_PP3,
764 };
765 static const unsigned int soc_gpio04_pp4_pins[] = {
766 TEGRA_PIN_SOC_GPIO04_PP4,
767 };
768 static const unsigned int soc_gpio05_pp5_pins[] = {
769 TEGRA_PIN_SOC_GPIO05_PP5,
770 };
771 static const unsigned int soc_gpio06_pp6_pins[] = {
772 TEGRA_PIN_SOC_GPIO06_PP6,
773 };
774 static const unsigned int soc_gpio07_pp7_pins[] = {
775 TEGRA_PIN_SOC_GPIO07_PP7,
776 };
777 static const unsigned int soc_gpio20_pq0_pins[] = {
778 TEGRA_PIN_SOC_GPIO20_PQ0,
779 };
780 static const unsigned int soc_gpio21_pq1_pins[] = {
781 TEGRA_PIN_SOC_GPIO21_PQ1,
782 };
783 static const unsigned int soc_gpio22_pq2_pins[] = {
784 TEGRA_PIN_SOC_GPIO22_PQ2,
785 };
786 static const unsigned int soc_gpio23_pq3_pins[] = {
787 TEGRA_PIN_SOC_GPIO23_PQ3,
788 };
789 static const unsigned int soc_gpio40_pq4_pins[] = {
790 TEGRA_PIN_SOC_GPIO40_PQ4,
791 };
792 static const unsigned int soc_gpio41_pq5_pins[] = {
793 TEGRA_PIN_SOC_GPIO41_PQ5,
794 };
795 static const unsigned int soc_gpio42_pq6_pins[] = {
796 TEGRA_PIN_SOC_GPIO42_PQ6,
797 };
798 static const unsigned int soc_gpio43_pq7_pins[] = {
799 TEGRA_PIN_SOC_GPIO43_PQ7,
800 };
801 static const unsigned int soc_gpio44_pr0_pins[] = {
802 TEGRA_PIN_SOC_GPIO44_PR0,
803 };
804 static const unsigned int soc_gpio45_pr1_pins[] = {
805 TEGRA_PIN_SOC_GPIO45_PR1,
806 };
807 static const unsigned int uart1_tx_pr2_pins[] = {
808 TEGRA_PIN_UART1_TX_PR2,
809 };
810 static const unsigned int uart1_rx_pr3_pins[] = {
811 TEGRA_PIN_UART1_RX_PR3,
812 };
813 static const unsigned int uart1_rts_pr4_pins[] = {
814 TEGRA_PIN_UART1_RTS_PR4,
815 };
816 static const unsigned int uart1_cts_pr5_pins[] = {
817 TEGRA_PIN_UART1_CTS_PR5,
818 };
819 static const unsigned int dap1_sclk_ps0_pins[] = {
820 TEGRA_PIN_DAP1_SCLK_PS0,
821 };
822 static const unsigned int dap1_dout_ps1_pins[] = {
823 TEGRA_PIN_DAP1_DOUT_PS1,
824 };
825 static const unsigned int dap1_din_ps2_pins[] = {
826 TEGRA_PIN_DAP1_DIN_PS2,
827 };
828 static const unsigned int dap1_fs_ps3_pins[] = {
829 TEGRA_PIN_DAP1_FS_PS3,
830 };
831 static const unsigned int aud_mclk_ps4_pins[] = {
832 TEGRA_PIN_AUD_MCLK_PS4,
833 };
834 static const unsigned int soc_gpio30_ps5_pins[] = {
835 TEGRA_PIN_SOC_GPIO30_PS5,
836 };
837 static const unsigned int soc_gpio31_ps6_pins[] = {
838 TEGRA_PIN_SOC_GPIO31_PS6,
839 };
840 static const unsigned int soc_gpio32_ps7_pins[] = {
841 TEGRA_PIN_SOC_GPIO32_PS7,
842 };
843 static const unsigned int soc_gpio33_pt0_pins[] = {
844 TEGRA_PIN_SOC_GPIO33_PT0,
845 };
846 static const unsigned int dap3_sclk_pt1_pins[] = {
847 TEGRA_PIN_DAP3_SCLK_PT1,
848 };
849 static const unsigned int dap3_dout_pt2_pins[] = {
850 TEGRA_PIN_DAP3_DOUT_PT2,
851 };
852 static const unsigned int dap3_din_pt3_pins[] = {
853 TEGRA_PIN_DAP3_DIN_PT3,
854 };
855 static const unsigned int dap3_fs_pt4_pins[] = {
856 TEGRA_PIN_DAP3_FS_PT4,
857 };
858 static const unsigned int dap5_sclk_pt5_pins[] = {
859 TEGRA_PIN_DAP5_SCLK_PT5,
860 };
861 static const unsigned int dap5_dout_pt6_pins[] = {
862 TEGRA_PIN_DAP5_DOUT_PT6,
863 };
864 static const unsigned int dap5_din_pt7_pins[] = {
865 TEGRA_PIN_DAP5_DIN_PT7,
866 };
867 static const unsigned int dap5_fs_pu0_pins[] = {
868 TEGRA_PIN_DAP5_FS_PU0,
869 };
870 static const unsigned int directdc1_clk_pv0_pins[] = {
871 TEGRA_PIN_DIRECTDC1_CLK_PV0,
872 };
873 static const unsigned int directdc1_in_pv1_pins[] = {
874 TEGRA_PIN_DIRECTDC1_IN_PV1,
875 };
876 static const unsigned int directdc1_out0_pv2_pins[] = {
877 TEGRA_PIN_DIRECTDC1_OUT0_PV2,
878 };
879 static const unsigned int directdc1_out1_pv3_pins[] = {
880 TEGRA_PIN_DIRECTDC1_OUT1_PV3,
881 };
882 static const unsigned int directdc1_out2_pv4_pins[] = {
883 TEGRA_PIN_DIRECTDC1_OUT2_PV4,
884 };
885 static const unsigned int directdc1_out3_pv5_pins[] = {
886 TEGRA_PIN_DIRECTDC1_OUT3_PV5,
887 };
888 static const unsigned int directdc1_out4_pv6_pins[] = {
889 TEGRA_PIN_DIRECTDC1_OUT4_PV6,
890 };
891 static const unsigned int directdc1_out5_pv7_pins[] = {
892 TEGRA_PIN_DIRECTDC1_OUT5_PV7,
893 };
894 static const unsigned int directdc1_out6_pw0_pins[] = {
895 TEGRA_PIN_DIRECTDC1_OUT6_PW0,
896 };
897 static const unsigned int directdc1_out7_pw1_pins[] = {
898 TEGRA_PIN_DIRECTDC1_OUT7_PW1,
899 };
900 static const unsigned int gpu_pwr_req_px0_pins[] = {
901 TEGRA_PIN_GPU_PWR_REQ_PX0,
902 };
903 static const unsigned int cv_pwr_req_px1_pins[] = {
904 TEGRA_PIN_CV_PWR_REQ_PX1,
905 };
906 static const unsigned int gp_pwm2_px2_pins[] = {
907 TEGRA_PIN_GP_PWM2_PX2,
908 };
909 static const unsigned int gp_pwm3_px3_pins[] = {
910 TEGRA_PIN_GP_PWM3_PX3,
911 };
912 static const unsigned int uart2_tx_px4_pins[] = {
913 TEGRA_PIN_UART2_TX_PX4,
914 };
915 static const unsigned int uart2_rx_px5_pins[] = {
916 TEGRA_PIN_UART2_RX_PX5,
917 };
918 static const unsigned int uart2_rts_px6_pins[] = {
919 TEGRA_PIN_UART2_RTS_PX6,
920 };
921 static const unsigned int uart2_cts_px7_pins[] = {
922 TEGRA_PIN_UART2_CTS_PX7,
923 };
924 static const unsigned int spi3_sck_py0_pins[] = {
925 TEGRA_PIN_SPI3_SCK_PY0,
926 };
927 static const unsigned int spi3_miso_py1_pins[] = {
928 TEGRA_PIN_SPI3_MISO_PY1,
929 };
930 static const unsigned int spi3_mosi_py2_pins[] = {
931 TEGRA_PIN_SPI3_MOSI_PY2,
932 };
933 static const unsigned int spi3_cs0_py3_pins[] = {
934 TEGRA_PIN_SPI3_CS0_PY3,
935 };
936 static const unsigned int spi3_cs1_py4_pins[] = {
937 TEGRA_PIN_SPI3_CS1_PY4,
938 };
939 static const unsigned int uart5_tx_py5_pins[] = {
940 TEGRA_PIN_UART5_TX_PY5,
941 };
942 static const unsigned int uart5_rx_py6_pins[] = {
943 TEGRA_PIN_UART5_RX_PY6,
944 };
945 static const unsigned int uart5_rts_py7_pins[] = {
946 TEGRA_PIN_UART5_RTS_PY7,
947 };
948 static const unsigned int uart5_cts_pz0_pins[] = {
949 TEGRA_PIN_UART5_CTS_PZ0,
950 };
951 static const unsigned int usb_vbus_en0_pz1_pins[] = {
952 TEGRA_PIN_USB_VBUS_EN0_PZ1,
953 };
954 static const unsigned int usb_vbus_en1_pz2_pins[] = {
955 TEGRA_PIN_USB_VBUS_EN1_PZ2,
956 };
957 static const unsigned int spi1_sck_pz3_pins[] = {
958 TEGRA_PIN_SPI1_SCK_PZ3,
959 };
960 static const unsigned int spi1_miso_pz4_pins[] = {
961 TEGRA_PIN_SPI1_MISO_PZ4,
962 };
963 static const unsigned int spi1_mosi_pz5_pins[] = {
964 TEGRA_PIN_SPI1_MOSI_PZ5,
965 };
966 static const unsigned int spi1_cs0_pz6_pins[] = {
967 TEGRA_PIN_SPI1_CS0_PZ6,
968 };
969 static const unsigned int spi1_cs1_pz7_pins[] = {
970 TEGRA_PIN_SPI1_CS1_PZ7,
971 };
972 static const unsigned int can1_dout_paa0_pins[] = {
973 TEGRA_PIN_CAN1_DOUT_PAA0,
974 };
975 static const unsigned int can1_din_paa1_pins[] = {
976 TEGRA_PIN_CAN1_DIN_PAA1,
977 };
978 static const unsigned int can0_dout_paa2_pins[] = {
979 TEGRA_PIN_CAN0_DOUT_PAA2,
980 };
981 static const unsigned int can0_din_paa3_pins[] = {
982 TEGRA_PIN_CAN0_DIN_PAA3,
983 };
984 static const unsigned int can0_stb_paa4_pins[] = {
985 TEGRA_PIN_CAN0_STB_PAA4,
986 };
987 static const unsigned int can0_en_paa5_pins[] = {
988 TEGRA_PIN_CAN0_EN_PAA5,
989 };
990 static const unsigned int can0_wake_paa6_pins[] = {
991 TEGRA_PIN_CAN0_WAKE_PAA6,
992 };
993 static const unsigned int can0_err_paa7_pins[] = {
994 TEGRA_PIN_CAN0_ERR_PAA7,
995 };
996 static const unsigned int can1_stb_pbb0_pins[] = {
997 TEGRA_PIN_CAN1_STB_PBB0,
998 };
999 static const unsigned int can1_en_pbb1_pins[] = {
1000 TEGRA_PIN_CAN1_EN_PBB1,
1001 };
1002 static const unsigned int can1_wake_pbb2_pins[] = {
1003 TEGRA_PIN_CAN1_WAKE_PBB2,
1004 };
1005 static const unsigned int can1_err_pbb3_pins[] = {
1006 TEGRA_PIN_CAN1_ERR_PBB3,
1007 };
1008 static const unsigned int spi2_sck_pcc0_pins[] = {
1009 TEGRA_PIN_SPI2_SCK_PCC0,
1010 };
1011 static const unsigned int spi2_miso_pcc1_pins[] = {
1012 TEGRA_PIN_SPI2_MISO_PCC1,
1013 };
1014 static const unsigned int spi2_mosi_pcc2_pins[] = {
1015 TEGRA_PIN_SPI2_MOSI_PCC2,
1016 };
1017 static const unsigned int spi2_cs0_pcc3_pins[] = {
1018 TEGRA_PIN_SPI2_CS0_PCC3,
1019 };
1020 static const unsigned int touch_clk_pcc4_pins[] = {
1021 TEGRA_PIN_TOUCH_CLK_PCC4,
1022 };
1023 static const unsigned int uart3_tx_pcc5_pins[] = {
1024 TEGRA_PIN_UART3_TX_PCC5,
1025 };
1026 static const unsigned int uart3_rx_pcc6_pins[] = {
1027 TEGRA_PIN_UART3_RX_PCC6,
1028 };
1029 static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
1030 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
1031 };
1032 static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
1033 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
1034 };
1035 static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
1036 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
1037 };
1038 static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
1039 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
1040 };
1041 static const unsigned int safe_state_pee0_pins[] = {
1042 TEGRA_PIN_SAFE_STATE_PEE0,
1043 };
1044 static const unsigned int vcomp_alert_pee1_pins[] = {
1045 TEGRA_PIN_VCOMP_ALERT_PEE1,
1046 };
1047 static const unsigned int ao_retention_n_pee2_pins[] = {
1048 TEGRA_PIN_AO_RETENTION_N_PEE2,
1049 };
1050 static const unsigned int batt_oc_pee3_pins[] = {
1051 TEGRA_PIN_BATT_OC_PEE3,
1052 };
1053 static const unsigned int power_on_pee4_pins[] = {
1054 TEGRA_PIN_POWER_ON_PEE4,
1055 };
1056 static const unsigned int pwr_i2c_scl_pee5_pins[] = {
1057 TEGRA_PIN_PWR_I2C_SCL_PEE5,
1058 };
1059 static const unsigned int pwr_i2c_sda_pee6_pins[] = {
1060 TEGRA_PIN_PWR_I2C_SDA_PEE6,
1061 };
1062 static const unsigned int ufs0_ref_clk_pff0_pins[] = {
1063 TEGRA_PIN_UFS0_REF_CLK_PFF0,
1064 };
1065 static const unsigned int ufs0_rst_pff1_pins[] = {
1066 TEGRA_PIN_UFS0_RST_PFF1,
1067 };
1068 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
1069 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
1070 };
1071 static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
1072 TEGRA_PIN_PEX_L5_RST_N_PGG1,
1073 };
1074 static const unsigned int directdc_comp_pins[] = {
1075 TEGRA_PIN_DIRECTDC_COMP,
1076 };
1077 static const unsigned int sdmmc4_clk_pins[] = {
1078 TEGRA_PIN_SDMMC4_CLK,
1079 };
1080 static const unsigned int sdmmc4_cmd_pins[] = {
1081 TEGRA_PIN_SDMMC4_CMD,
1082 };
1083 static const unsigned int sdmmc4_dqs_pins[] = {
1084 TEGRA_PIN_SDMMC4_DQS,
1085 };
1086 static const unsigned int sdmmc4_dat7_pins[] = {
1087 TEGRA_PIN_SDMMC4_DAT7,
1088 };
1089 static const unsigned int sdmmc4_dat6_pins[] = {
1090 TEGRA_PIN_SDMMC4_DAT6,
1091 };
1092 static const unsigned int sdmmc4_dat5_pins[] = {
1093 TEGRA_PIN_SDMMC4_DAT5,
1094 };
1095 static const unsigned int sdmmc4_dat4_pins[] = {
1096 TEGRA_PIN_SDMMC4_DAT4,
1097 };
1098 static const unsigned int sdmmc4_dat3_pins[] = {
1099 TEGRA_PIN_SDMMC4_DAT3,
1100 };
1101 static const unsigned int sdmmc4_dat2_pins[] = {
1102 TEGRA_PIN_SDMMC4_DAT2,
1103 };
1104 static const unsigned int sdmmc4_dat1_pins[] = {
1105 TEGRA_PIN_SDMMC4_DAT1,
1106 };
1107 static const unsigned int sdmmc4_dat0_pins[] = {
1108 TEGRA_PIN_SDMMC4_DAT0,
1109 };
1110 static const unsigned int sdmmc1_comp_pins[] = {
1111 TEGRA_PIN_SDMMC1_COMP,
1112 };
1113 static const unsigned int sdmmc3_comp_pins[] = {
1114 TEGRA_PIN_SDMMC3_COMP,
1115 };
1116 static const unsigned int eqos_comp_pins[] = {
1117 TEGRA_PIN_EQOS_COMP,
1118 };
1119 static const unsigned int qspi_comp_pins[] = {
1120 TEGRA_PIN_QSPI_COMP,
1121 };
1122 static const unsigned int shutdown_n_pins[] = {
1123 TEGRA_PIN_SHUTDOWN_N,
1124 };
1125 static const unsigned int pmu_int_n_pins[] = {
1126 TEGRA_PIN_PMU_INT_N,
1127 };
1128 static const unsigned int soc_pwr_req_pins[] = {
1129 TEGRA_PIN_SOC_PWR_REQ,
1130 };
1131 static const unsigned int clk_32k_in_pins[] = {
1132 TEGRA_PIN_CLK_32K_IN,
1133 };
1134
1135 /* Define unique ID for each function */
1136 enum tegra_mux_dt {
1137 TEGRA_MUX_RSVD0,
1138 TEGRA_MUX_RSVD1,
1139 TEGRA_MUX_RSVD2,
1140 TEGRA_MUX_RSVD3,
1141 TEGRA_MUX_TOUCH,
1142 TEGRA_MUX_UARTC,
1143 TEGRA_MUX_I2C8,
1144 TEGRA_MUX_UARTG,
1145 TEGRA_MUX_SPI2,
1146 TEGRA_MUX_GP,
1147 TEGRA_MUX_DCA,
1148 TEGRA_MUX_WDT,
1149 TEGRA_MUX_I2C2,
1150 TEGRA_MUX_CAN1,
1151 TEGRA_MUX_CAN0,
1152 TEGRA_MUX_DMIC3,
1153 TEGRA_MUX_DMIC5,
1154 TEGRA_MUX_GPIO,
1155 TEGRA_MUX_DSPK1,
1156 TEGRA_MUX_DSPK0,
1157 TEGRA_MUX_SPDIF,
1158 TEGRA_MUX_AUD,
1159 TEGRA_MUX_I2S1,
1160 TEGRA_MUX_DMIC1,
1161 TEGRA_MUX_DMIC2,
1162 TEGRA_MUX_I2S3,
1163 TEGRA_MUX_DMIC4,
1164 TEGRA_MUX_I2S4,
1165 TEGRA_MUX_EXTPERIPH2,
1166 TEGRA_MUX_EXTPERIPH1,
1167 TEGRA_MUX_I2C3,
1168 TEGRA_MUX_VGP1,
1169 TEGRA_MUX_VGP2,
1170 TEGRA_MUX_VGP3,
1171 TEGRA_MUX_VGP4,
1172 TEGRA_MUX_VGP5,
1173 TEGRA_MUX_VGP6,
1174 TEGRA_MUX_SLVS,
1175 TEGRA_MUX_EXTPERIPH3,
1176 TEGRA_MUX_EXTPERIPH4,
1177 TEGRA_MUX_I2S2,
1178 TEGRA_MUX_UARTD,
1179 TEGRA_MUX_I2C1,
1180 TEGRA_MUX_UARTA,
1181 TEGRA_MUX_DIRECTDC1,
1182 TEGRA_MUX_DIRECTDC,
1183 TEGRA_MUX_IQC1,
1184 TEGRA_MUX_IQC2,
1185 TEGRA_MUX_I2S6,
1186 TEGRA_MUX_SDMMC3,
1187 TEGRA_MUX_SDMMC1,
1188 TEGRA_MUX_DP,
1189 TEGRA_MUX_HDMI,
1190 TEGRA_MUX_PE2,
1191 TEGRA_MUX_IGPU,
1192 TEGRA_MUX_SATA,
1193 TEGRA_MUX_PE1,
1194 TEGRA_MUX_PE0,
1195 TEGRA_MUX_PE3,
1196 TEGRA_MUX_PE4,
1197 TEGRA_MUX_PE5,
1198 TEGRA_MUX_SOC,
1199 TEGRA_MUX_EQOS,
1200 TEGRA_MUX_QSPI,
1201 TEGRA_MUX_QSPI0,
1202 TEGRA_MUX_QSPI1,
1203 TEGRA_MUX_MIPI,
1204 TEGRA_MUX_SCE,
1205 TEGRA_MUX_I2C5,
1206 TEGRA_MUX_DISPLAYA,
1207 TEGRA_MUX_DISPLAYB,
1208 TEGRA_MUX_DCB,
1209 TEGRA_MUX_SPI1,
1210 TEGRA_MUX_UARTB,
1211 TEGRA_MUX_UARTE,
1212 TEGRA_MUX_SPI3,
1213 TEGRA_MUX_NV,
1214 TEGRA_MUX_CCLA,
1215 TEGRA_MUX_I2S5,
1216 TEGRA_MUX_USB,
1217 TEGRA_MUX_UFS0,
1218 TEGRA_MUX_DGPU,
1219 TEGRA_MUX_SDMMC4,
1220 };
1221
1222 /* Make list of each function name */
1223 #define TEGRA_PIN_FUNCTION(lid) \
1224 { \
1225 .name = #lid, \
1226 }
1227
1228 static struct tegra_function tegra194_functions[] = {
1229 TEGRA_PIN_FUNCTION(rsvd0),
1230 TEGRA_PIN_FUNCTION(rsvd1),
1231 TEGRA_PIN_FUNCTION(rsvd2),
1232 TEGRA_PIN_FUNCTION(rsvd3),
1233 TEGRA_PIN_FUNCTION(touch),
1234 TEGRA_PIN_FUNCTION(uartc),
1235 TEGRA_PIN_FUNCTION(i2c8),
1236 TEGRA_PIN_FUNCTION(uartg),
1237 TEGRA_PIN_FUNCTION(spi2),
1238 TEGRA_PIN_FUNCTION(gp),
1239 TEGRA_PIN_FUNCTION(dca),
1240 TEGRA_PIN_FUNCTION(wdt),
1241 TEGRA_PIN_FUNCTION(i2c2),
1242 TEGRA_PIN_FUNCTION(can1),
1243 TEGRA_PIN_FUNCTION(can0),
1244 TEGRA_PIN_FUNCTION(dmic3),
1245 TEGRA_PIN_FUNCTION(dmic5),
1246 TEGRA_PIN_FUNCTION(gpio),
1247 TEGRA_PIN_FUNCTION(dspk1),
1248 TEGRA_PIN_FUNCTION(dspk0),
1249 TEGRA_PIN_FUNCTION(spdif),
1250 TEGRA_PIN_FUNCTION(aud),
1251 TEGRA_PIN_FUNCTION(i2s1),
1252 TEGRA_PIN_FUNCTION(dmic1),
1253 TEGRA_PIN_FUNCTION(dmic2),
1254 TEGRA_PIN_FUNCTION(i2s3),
1255 TEGRA_PIN_FUNCTION(dmic4),
1256 TEGRA_PIN_FUNCTION(i2s4),
1257 TEGRA_PIN_FUNCTION(extperiph2),
1258 TEGRA_PIN_FUNCTION(extperiph1),
1259 TEGRA_PIN_FUNCTION(i2c3),
1260 TEGRA_PIN_FUNCTION(vgp1),
1261 TEGRA_PIN_FUNCTION(vgp2),
1262 TEGRA_PIN_FUNCTION(vgp3),
1263 TEGRA_PIN_FUNCTION(vgp4),
1264 TEGRA_PIN_FUNCTION(vgp5),
1265 TEGRA_PIN_FUNCTION(vgp6),
1266 TEGRA_PIN_FUNCTION(slvs),
1267 TEGRA_PIN_FUNCTION(extperiph3),
1268 TEGRA_PIN_FUNCTION(extperiph4),
1269 TEGRA_PIN_FUNCTION(i2s2),
1270 TEGRA_PIN_FUNCTION(uartd),
1271 TEGRA_PIN_FUNCTION(i2c1),
1272 TEGRA_PIN_FUNCTION(uarta),
1273 TEGRA_PIN_FUNCTION(directdc1),
1274 TEGRA_PIN_FUNCTION(directdc),
1275 TEGRA_PIN_FUNCTION(iqc1),
1276 TEGRA_PIN_FUNCTION(iqc2),
1277 TEGRA_PIN_FUNCTION(i2s6),
1278 TEGRA_PIN_FUNCTION(sdmmc3),
1279 TEGRA_PIN_FUNCTION(sdmmc1),
1280 TEGRA_PIN_FUNCTION(dp),
1281 TEGRA_PIN_FUNCTION(hdmi),
1282 TEGRA_PIN_FUNCTION(pe2),
1283 TEGRA_PIN_FUNCTION(igpu),
1284 TEGRA_PIN_FUNCTION(sata),
1285 TEGRA_PIN_FUNCTION(pe1),
1286 TEGRA_PIN_FUNCTION(pe0),
1287 TEGRA_PIN_FUNCTION(pe3),
1288 TEGRA_PIN_FUNCTION(pe4),
1289 TEGRA_PIN_FUNCTION(pe5),
1290 TEGRA_PIN_FUNCTION(soc),
1291 TEGRA_PIN_FUNCTION(eqos),
1292 TEGRA_PIN_FUNCTION(qspi),
1293 TEGRA_PIN_FUNCTION(qspi0),
1294 TEGRA_PIN_FUNCTION(qspi1),
1295 TEGRA_PIN_FUNCTION(mipi),
1296 TEGRA_PIN_FUNCTION(sce),
1297 TEGRA_PIN_FUNCTION(i2c5),
1298 TEGRA_PIN_FUNCTION(displaya),
1299 TEGRA_PIN_FUNCTION(displayb),
1300 TEGRA_PIN_FUNCTION(dcb),
1301 TEGRA_PIN_FUNCTION(spi1),
1302 TEGRA_PIN_FUNCTION(uartb),
1303 TEGRA_PIN_FUNCTION(uarte),
1304 TEGRA_PIN_FUNCTION(spi3),
1305 TEGRA_PIN_FUNCTION(nv),
1306 TEGRA_PIN_FUNCTION(ccla),
1307 TEGRA_PIN_FUNCTION(i2s5),
1308 TEGRA_PIN_FUNCTION(usb),
1309 TEGRA_PIN_FUNCTION(ufs0),
1310 TEGRA_PIN_FUNCTION(dgpu),
1311 TEGRA_PIN_FUNCTION(sdmmc4),
1312
1313 };
1314
1315 #define PINGROUP_REG_Y(r) ((r))
1316 #define PINGROUP_REG_N(r) -1
1317
1318 #define DRV_PINGROUP_Y(r) ((r))
1319 #define DRV_PINGROUP_N(r) -1
1320
1321 #define DRV_PINGROUP_ENTRY_N(pg_name) \
1322 .drv_reg = -1, \
1323 .drv_bank = -1, \
1324 .drvdn_bit = -1, \
1325 .drvup_bit = -1, \
1326 .slwr_bit = -1, \
1327 .slwf_bit = -1
1328
1329 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1330 drvup_w, slwr_b, slwr_w, slwf_b, \
1331 slwf_w, bank) \
1332 .drv_reg = ((r)), \
1333 .drv_bank = bank, \
1334 .drvdn_bit = drvdn_b, \
1335 .drvdn_width = drvdn_w, \
1336 .drvup_bit = drvup_b, \
1337 .drvup_width = drvup_w, \
1338 .slwr_bit = slwr_b, \
1339 .slwr_width = slwr_w, \
1340 .slwf_bit = slwf_b, \
1341 .slwf_width = slwf_w
1342
1343 #define PIN_PINGROUP_ENTRY_N(pg_name) \
1344 .mux_reg = -1, \
1345 .pupd_reg = -1, \
1346 .tri_reg = -1, \
1347 .einput_bit = -1, \
1348 .e_io_hv_bit = -1, \
1349 .odrain_bit = -1, \
1350 .lock_bit = -1, \
1351 .parked_bit = -1, \
1352 .lpmd_bit = -1, \
1353 .drvtype_bit = -1, \
1354 .lpdr_bit = -1, \
1355 .pbias_buf_bit = -1, \
1356 .preemp_bit = -1, \
1357 .rfu_in_bit = -1
1358
1359 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1360 e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1361 e_od, schmitt_b, drvtype, epreemp, \
1362 io_reset, rfu_in, io_rail) \
1363 .mux_reg = PINGROUP_REG_Y(r), \
1364 .lpmd_bit = -1, \
1365 .lock_bit = -1, \
1366 .hsm_bit = -1, \
1367 .mux_bank = bank, \
1368 .mux_bit = 0, \
1369 .pupd_reg = PINGROUP_REG_##pupd(r), \
1370 .pupd_bank = bank, \
1371 .pupd_bit = 2, \
1372 .tri_reg = PINGROUP_REG_Y(r), \
1373 .tri_bank = bank, \
1374 .tri_bit = 4, \
1375 .einput_bit = e_input, \
1376 .sfsel_bit = gpio_sfio_sel, \
1377 .odrain_bit = e_od, \
1378 .schmitt_bit = schmitt_b, \
1379 .drvtype_bit = 13, \
1380 .lpdr_bit = e_lpdr, \
1381
1382 #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1383 #define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1384 #define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1385 #define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1386 #define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1387 #define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1388 #define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1389 #define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1390 #define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1391 #define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1392 #define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1393 #define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1394 #define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1395 #define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1396 #define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1397 #define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1398 #define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1399 #define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1400 #define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1401 #define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1402 #define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1403 #define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1404 #define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1405 #define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1406 #define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1407 #define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1408 #define drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1409 #define drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1410 #define drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1411 #define drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1412 #define drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1413 #define drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1414 #define drive_dap3_fs_pt4 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1415 #define drive_dap3_din_pt3 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1416 #define drive_dap3_dout_pt2 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1417 #define drive_dap3_sclk_pt1 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1418 #define drive_dap5_fs_pu0 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1419 #define drive_dap5_din_pt7 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1420 #define drive_dap5_dout_pt6 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1421 #define drive_dap5_sclk_pt5 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1422 #define drive_dap6_fs_pa3 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1423 #define drive_dap6_din_pa2 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1424 #define drive_dap6_dout_pa1 DRV_PINGROUP_ENTRY_Y(0x2014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1425 #define drive_dap6_sclk_pa0 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1426 #define drive_dap4_fs_pa7 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1427 #define drive_dap4_din_pa6 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1428 #define drive_dap4_dout_pa5 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1429 #define drive_dap4_sclk_pa4 DRV_PINGROUP_ENTRY_Y(0x203c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1430 #define drive_extperiph2_clk_pp1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1431 #define drive_extperiph1_clk_pp0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1432 #define drive_cam_i2c_sda_pp3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1433 #define drive_cam_i2c_scl_pp2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1434 #define drive_soc_gpio40_pq4 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1435 #define drive_soc_gpio41_pq5 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1436 #define drive_soc_gpio42_pq6 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1437 #define drive_soc_gpio43_pq7 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1438 #define drive_soc_gpio44_pr0 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1439 #define drive_soc_gpio45_pr1 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1440 #define drive_soc_gpio20_pq0 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1441 #define drive_soc_gpio21_pq1 DRV_PINGROUP_ENTRY_Y(0x005c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1442 #define drive_soc_gpio22_pq2 DRV_PINGROUP_ENTRY_Y(0x0064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1443 #define drive_soc_gpio23_pq3 DRV_PINGROUP_ENTRY_Y(0x006c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1444 #define drive_soc_gpio04_pp4 DRV_PINGROUP_ENTRY_Y(0x0074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1445 #define drive_soc_gpio05_pp5 DRV_PINGROUP_ENTRY_Y(0x007c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1446 #define drive_soc_gpio06_pp6 DRV_PINGROUP_ENTRY_Y(0x0084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1447 #define drive_soc_gpio07_pp7 DRV_PINGROUP_ENTRY_Y(0x008c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1448 #define drive_uart1_cts_pr5 DRV_PINGROUP_ENTRY_Y(0x0094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449 #define drive_uart1_rts_pr4 DRV_PINGROUP_ENTRY_Y(0x009c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450 #define drive_uart1_rx_pr3 DRV_PINGROUP_ENTRY_Y(0x00a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451 #define drive_uart1_tx_pr2 DRV_PINGROUP_ENTRY_Y(0x00ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452 #define drive_dap2_din_pi1 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453 #define drive_dap2_dout_pi0 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454 #define drive_dap2_fs_pi2 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455 #define drive_dap2_sclk_ph7 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1456 #define drive_uart4_cts_ph6 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1457 #define drive_uart4_rts_ph5 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1458 #define drive_uart4_rx_ph4 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1459 #define drive_uart4_tx_ph3 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1460 #define drive_soc_gpio03_pg3 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1461 #define drive_soc_gpio02_pg2 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1462 #define drive_soc_gpio01_pg1 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1463 #define drive_soc_gpio00_pg0 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1464 #define drive_gen1_i2c_scl_pi3 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1465 #define drive_gen1_i2c_sda_pi4 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1466 #define drive_soc_gpio08_pg4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1467 #define drive_soc_gpio09_pg5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1468 #define drive_soc_gpio10_pg6 DRV_PINGROUP_ENTRY_Y(0x4084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1469 #define drive_soc_gpio11_pg7 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1470 #define drive_soc_gpio12_ph0 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1471 #define drive_soc_gpio13_ph1 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1472 #define drive_soc_gpio14_ph2 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1473 #define drive_soc_gpio50_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1474 #define drive_soc_gpio51_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1475 #define drive_soc_gpio52_pm7 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1476 #define drive_soc_gpio53_pn0 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1477 #define drive_soc_gpio54_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1478 #define drive_soc_gpio55_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1479 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1480 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1481 #define drive_dp_aux_ch2_hpd_pm2 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1482 #define drive_dp_aux_ch3_hpd_pm3 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1483 #define drive_hdmi_cec_pm4 DRV_PINGROUP_ENTRY_Y(0x10054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1484 #define drive_pex_l2_clkreq_n_pk4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1485 #define drive_pex_wake_n_pl2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1486 #define drive_pex_l1_clkreq_n_pk2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1487 #define drive_pex_l1_rst_n_pk3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1488 #define drive_pex_l0_clkreq_n_pk0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1489 #define drive_pex_l0_rst_n_pk1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1490 #define drive_pex_l2_rst_n_pk5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1491 #define drive_pex_l3_clkreq_n_pk6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1492 #define drive_pex_l3_rst_n_pk7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1493 #define drive_pex_l4_clkreq_n_pl0 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1494 #define drive_pex_l4_rst_n_pl1 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1495 #define drive_sata_dev_slp_pl3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1496 #define drive_pex_l5_clkreq_n_pgg0 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1497 #define drive_pex_l5_rst_n_pgg1 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1498 #define drive_cpu_pwr_req_1_pb1 DRV_PINGROUP_ENTRY_Y(0x16004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1499 #define drive_cpu_pwr_req_0_pb0 DRV_PINGROUP_ENTRY_Y(0x1600c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1500 #define drive_sdmmc1_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x8004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1501 #define drive_sdmmc1_cmd_pj1 DRV_PINGROUP_ENTRY_Y(0x800c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1502 #define drive_sdmmc1_dat3_pj5 DRV_PINGROUP_ENTRY_Y(0x801c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1503 #define drive_sdmmc1_dat2_pj4 DRV_PINGROUP_ENTRY_Y(0x8024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1504 #define drive_sdmmc1_dat1_pj3 DRV_PINGROUP_ENTRY_Y(0x802c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1505 #define drive_sdmmc1_dat0_pj2 DRV_PINGROUP_ENTRY_Y(0x8034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1506 #define drive_sdmmc3_dat3_po5 DRV_PINGROUP_ENTRY_Y(0xa004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1507 #define drive_sdmmc3_dat2_po4 DRV_PINGROUP_ENTRY_Y(0xa00c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1508 #define drive_sdmmc3_dat1_po3 DRV_PINGROUP_ENTRY_Y(0xa014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1509 #define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1510 #define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1511 #define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1512 #define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1513 #define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1514 #define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1515 #define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1516 #define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1517 #define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1518 #define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1519 #define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1520 #define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1521 #define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1522 #define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1523 #define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1524 #define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1525 #define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1526 #define drive_spi3_cs0_py3 DRV_PINGROUP_ENTRY_Y(0xD01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1527 #define drive_spi1_miso_pz4 DRV_PINGROUP_ENTRY_Y(0xD024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1528 #define drive_spi3_cs1_py4 DRV_PINGROUP_ENTRY_Y(0xD02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1529 #define drive_gp_pwm3_px3 DRV_PINGROUP_ENTRY_Y(0xD034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1530 #define drive_gp_pwm2_px2 DRV_PINGROUP_ENTRY_Y(0xD03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1531 #define drive_spi1_sck_pz3 DRV_PINGROUP_ENTRY_Y(0xD044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1532 #define drive_spi3_sck_py0 DRV_PINGROUP_ENTRY_Y(0xD04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1533 #define drive_spi1_cs1_pz7 DRV_PINGROUP_ENTRY_Y(0xD054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1534 #define drive_spi1_mosi_pz5 DRV_PINGROUP_ENTRY_Y(0xD05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1535 #define drive_spi3_mosi_py2 DRV_PINGROUP_ENTRY_Y(0xD064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1536 #define drive_cv_pwr_req_px1 DRV_PINGROUP_ENTRY_Y(0xD06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1537 #define drive_uart2_tx_px4 DRV_PINGROUP_ENTRY_Y(0xD074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1538 #define drive_uart2_rx_px5 DRV_PINGROUP_ENTRY_Y(0xD07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1539 #define drive_uart2_rts_px6 DRV_PINGROUP_ENTRY_Y(0xD084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1540 #define drive_uart2_cts_px7 DRV_PINGROUP_ENTRY_Y(0xD08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1541 #define drive_uart5_rx_py6 DRV_PINGROUP_ENTRY_Y(0xD094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1542 #define drive_uart5_tx_py5 DRV_PINGROUP_ENTRY_Y(0xD09c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1543 #define drive_uart5_rts_py7 DRV_PINGROUP_ENTRY_Y(0xD0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1544 #define drive_uart5_cts_pz0 DRV_PINGROUP_ENTRY_Y(0xD0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1545 #define drive_usb_vbus_en0_pz1 DRV_PINGROUP_ENTRY_Y(0xD0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1546 #define drive_usb_vbus_en1_pz2 DRV_PINGROUP_ENTRY_Y(0xD0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1547 #define drive_ufs0_rst_pff1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1548 #define drive_ufs0_ref_clk_pff0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1549
1550 #define drive_directdc_comp DRV_PINGROUP_ENTRY_N(no_entry)
1551 #define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry)
1552 #define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry)
1553 #define drive_sdmmc3_comp DRV_PINGROUP_ENTRY_N(no_entry)
1554 #define drive_sdmmc4_clk DRV_PINGROUP_ENTRY_N(no_entry)
1555 #define drive_sdmmc4_cmd DRV_PINGROUP_ENTRY_N(no_entry)
1556 #define drive_sdmmc4_dqs DRV_PINGROUP_ENTRY_N(no_entry)
1557 #define drive_sdmmc4_dat7 DRV_PINGROUP_ENTRY_N(no_entry)
1558 #define drive_sdmmc4_dat6 DRV_PINGROUP_ENTRY_N(no_entry)
1559 #define drive_sdmmc4_dat5 DRV_PINGROUP_ENTRY_N(no_entry)
1560 #define drive_sdmmc4_dat4 DRV_PINGROUP_ENTRY_N(no_entry)
1561 #define drive_sdmmc4_dat3 DRV_PINGROUP_ENTRY_N(no_entry)
1562 #define drive_sdmmc4_dat2 DRV_PINGROUP_ENTRY_N(no_entry)
1563 #define drive_sdmmc4_dat1 DRV_PINGROUP_ENTRY_N(no_entry)
1564 #define drive_sdmmc4_dat0 DRV_PINGROUP_ENTRY_N(no_entry)
1565 #define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry)
1566 #define drive_qspi1_cs_n_pc7 DRV_PINGROUP_ENTRY_N(no_entry)
1567 #define drive_qspi1_sck_pc6 DRV_PINGROUP_ENTRY_N(no_entry)
1568 #define drive_qspi1_io0_pd0 DRV_PINGROUP_ENTRY_N(no_entry)
1569 #define drive_qspi1_io1_pd1 DRV_PINGROUP_ENTRY_N(no_entry)
1570 #define drive_qspi1_io2_pd2 DRV_PINGROUP_ENTRY_N(no_entry)
1571 #define drive_qspi1_io3_pd3 DRV_PINGROUP_ENTRY_N(no_entry)
1572 #define drive_qspi0_io0_pc2 DRV_PINGROUP_ENTRY_N(no_entry)
1573 #define drive_qspi0_io1_pc3 DRV_PINGROUP_ENTRY_N(no_entry)
1574 #define drive_qspi0_io2_pc4 DRV_PINGROUP_ENTRY_N(no_entry)
1575 #define drive_qspi0_io3_pc5 DRV_PINGROUP_ENTRY_N(no_entry)
1576 #define drive_qspi0_cs_n_pc1 DRV_PINGROUP_ENTRY_N(no_entry)
1577 #define drive_qspi0_sck_pc0 DRV_PINGROUP_ENTRY_N(no_entry)
1578 #define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_N(no_entry)
1579 #define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_N(no_entry)
1580 #define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_N(no_entry)
1581 #define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_N(no_entry)
1582 #define drive_eqos_sma_mdc_pf5 DRV_PINGROUP_ENTRY_N(no_entry)
1583 #define drive_eqos_sma_mdio_pf4 DRV_PINGROUP_ENTRY_N(no_entry)
1584 #define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_N(no_entry)
1585 #define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_N(no_entry)
1586 #define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_N(no_entry)
1587 #define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_N(no_entry)
1588 #define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_N(no_entry)
1589 #define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_N(no_entry)
1590 #define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_N(no_entry)
1591 #define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_N(no_entry)
1592 #define drive_directdc1_out7_pw1 DRV_PINGROUP_ENTRY_N(no_entry)
1593 #define drive_directdc1_out6_pw0 DRV_PINGROUP_ENTRY_N(no_entry)
1594 #define drive_directdc1_out5_pv7 DRV_PINGROUP_ENTRY_N(no_entry)
1595 #define drive_directdc1_out4_pv6 DRV_PINGROUP_ENTRY_N(no_entry)
1596 #define drive_directdc1_out3_pv5 DRV_PINGROUP_ENTRY_N(no_entry)
1597 #define drive_directdc1_out2_pv4 DRV_PINGROUP_ENTRY_N(no_entry)
1598 #define drive_directdc1_out1_pv3 DRV_PINGROUP_ENTRY_N(no_entry)
1599 #define drive_directdc1_out0_pv2 DRV_PINGROUP_ENTRY_N(no_entry)
1600 #define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry)
1601 #define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry)
1602
1603 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1604 gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \
1605 { \
1606 .name = #pg_name, \
1607 .pins = pg_name##_pins, \
1608 .npins = ARRAY_SIZE(pg_name##_pins), \
1609 .funcs = { \
1610 TEGRA_MUX_##f0, \
1611 TEGRA_MUX_##f1, \
1612 TEGRA_MUX_##f2, \
1613 TEGRA_MUX_##f3, \
1614 }, \
1615 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1616 e_input, e_lpdr, e_pbias_buf, \
1617 gpio_sfio_sel, e_od, \
1618 schmitt_b, drvtype, \
1619 epreemp, io_reset, \
1620 rfu_in, io_rail) \
1621 drive_##pg_name, \
1622 }
1623
1624 static const struct tegra_pingroup tegra194_groups[] = {
1625
1626 PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1627 PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1628 PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1629 PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1630 PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1631 PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1632 PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1633 PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1634 PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1635 PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1636 PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1637 PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1638 PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1639 PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1640 PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1641 PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1642 PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1643 PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1644 PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1645 PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1646 PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1647 PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1648 PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1649 PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1650 PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1651 PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1652 PINGROUP(soc_gpio30_ps5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1653 PINGROUP(aud_mclk_ps4, AUD, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1654 PINGROUP(dap1_fs_ps3, I2S1, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1655 PINGROUP(dap1_din_ps2, I2S1, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1656 PINGROUP(dap1_dout_ps1, I2S1, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1657 PINGROUP(dap1_sclk_ps0, I2S1, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1658 PINGROUP(dap3_fs_pt4, I2S3, DMIC2, RSVD2, RSVD3, 0x1048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1659 PINGROUP(dap3_din_pt3, I2S3, DMIC2, RSVD2, RSVD3, 0x1050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1660 PINGROUP(dap3_dout_pt2, I2S3, DMIC1, RSVD2, RSVD3, 0x1058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1661 PINGROUP(dap3_sclk_pt1, I2S3, DMIC1, RSVD2, RSVD3, 0x1060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1662 PINGROUP(dap5_fs_pu0, I2S5, DMIC4, DSPK1, RSVD3, 0x1068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1663 PINGROUP(dap5_din_pt7, I2S5, DMIC4, DSPK1, RSVD3, 0x1070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1664 PINGROUP(dap5_dout_pt6, I2S5, DSPK0, RSVD2, RSVD3, 0x1078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1665 PINGROUP(dap5_sclk_pt5, I2S5, DSPK0, RSVD2, RSVD3, 0x1080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1666 PINGROUP(dap6_fs_pa3, I2S6, IQC1, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1667 PINGROUP(dap6_din_pa2, I2S6, IQC1, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1668 PINGROUP(dap6_dout_pa1, I2S6, IQC1, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1669 PINGROUP(dap6_sclk_pa0, I2S6, IQC1, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1670 PINGROUP(dap4_fs_pa7, I2S4, IQC2, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1671 PINGROUP(dap4_din_pa6, I2S4, IQC2, RSVD2, RSVD3, 0x2028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1672 PINGROUP(dap4_dout_pa5, I2S4, IQC2, RSVD2, RSVD3, 0x2030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1673 PINGROUP(dap4_sclk_pa4, I2S4, IQC2, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
1674 PINGROUP(extperiph2_clk_pp1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1675 PINGROUP(extperiph1_clk_pp0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1676 PINGROUP(cam_i2c_sda_pp3, I2C3, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1677 PINGROUP(cam_i2c_scl_pp2, I2C3, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1678 PINGROUP(soc_gpio40_pq4, VGP1, SLVS, RSVD2, RSVD3, 0x0020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1679 PINGROUP(soc_gpio41_pq5, VGP2, EXTPERIPH3, RSVD2, RSVD3, 0x0028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1680 PINGROUP(soc_gpio42_pq6, VGP3, EXTPERIPH4, RSVD2, RSVD3, 0x0030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1681 PINGROUP(soc_gpio43_pq7, VGP4, SLVS, RSVD2, RSVD3, 0x0038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1682 PINGROUP(soc_gpio44_pr0, VGP5, GP, RSVD2, RSVD3, 0x0040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1683 PINGROUP(soc_gpio45_pr1, VGP6, RSVD1, RSVD2, RSVD3, 0x0048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1684 PINGROUP(soc_gpio20_pq0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1685 PINGROUP(soc_gpio21_pq1, RSVD0, RSVD1, RSVD2, RSVD3, 0x0058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1686 PINGROUP(soc_gpio22_pq2, RSVD0, NV, RSVD2, RSVD3, 0x0060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1687 PINGROUP(soc_gpio23_pq3, RSVD0, WDT, RSVD2, RSVD3, 0x0068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1688 PINGROUP(soc_gpio04_pp4, RSVD0, RSVD1, RSVD2, RSVD3, 0x0070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1689 PINGROUP(soc_gpio05_pp5, RSVD0, IGPU, RSVD2, RSVD3, 0x0078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1690 PINGROUP(soc_gpio06_pp6, RSVD0, RSVD1, RSVD2, RSVD3, 0x0080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1691 PINGROUP(soc_gpio07_pp7, RSVD0, SATA, SOC, RSVD3, 0x0088, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1692 PINGROUP(uart1_cts_pr5, UARTA, RSVD1, RSVD2, RSVD3, 0x0090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1693 PINGROUP(uart1_rts_pr4, UARTA, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1694 PINGROUP(uart1_rx_pr3, UARTA, RSVD1, RSVD2, RSVD3, 0x00a0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1695 PINGROUP(uart1_tx_pr2, UARTA, RSVD1, RSVD2, RSVD3, 0x00a8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
1696 PINGROUP(dap2_din_pi1, I2S2, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1697 PINGROUP(dap2_dout_pi0, I2S2, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1698 PINGROUP(dap2_fs_pi2, I2S2, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1699 PINGROUP(dap2_sclk_ph7, I2S2, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1700 PINGROUP(uart4_cts_ph6, UARTD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1701 PINGROUP(uart4_rts_ph5, UARTD, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1702 PINGROUP(uart4_rx_ph4, UARTD, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1703 PINGROUP(uart4_tx_ph3, UARTD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1704 PINGROUP(soc_gpio03_pg3, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1705 PINGROUP(soc_gpio02_pg2, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1706 PINGROUP(soc_gpio01_pg1, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1707 PINGROUP(soc_gpio00_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1708 PINGROUP(gen1_i2c_scl_pi3, I2C1, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1709 PINGROUP(gen1_i2c_sda_pi4, I2C1, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1710 PINGROUP(soc_gpio08_pg4, RSVD0, CCLA, RSVD2, RSVD3, 0x4070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1711 PINGROUP(soc_gpio09_pg5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1712 PINGROUP(soc_gpio10_pg6, GP, RSVD1, RSVD2, RSVD3, 0x4080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1713 PINGROUP(soc_gpio11_pg7, RSVD0, SDMMC1, RSVD2, RSVD3, 0x4088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1714 PINGROUP(soc_gpio12_ph0, RSVD0, GP, RSVD2, RSVD3, 0x4090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1715 PINGROUP(soc_gpio13_ph1, RSVD0, GP, RSVD2, RSVD3, 0x4098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1716 PINGROUP(soc_gpio14_ph2, RSVD0, SDMMC1, RSVD2, RSVD3, 0x40a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
1717 PINGROUP(directdc1_out7_pw1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1718 PINGROUP(directdc1_out6_pw0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1719 PINGROUP(directdc1_out5_pv7, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1720 PINGROUP(directdc1_out4_pv6, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1721 PINGROUP(directdc1_out3_pv5, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1722 PINGROUP(directdc1_out2_pv4, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1723 PINGROUP(directdc1_out1_pv3, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1724 PINGROUP(directdc1_out0_pv2, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1725 PINGROUP(directdc1_in_pv1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1726 PINGROUP(directdc1_clk_pv0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
1727 PINGROUP(directdc_comp, DIRECTDC, RSVD1, RSVD2, RSVD3, 0x5058, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_debug"),
1728 PINGROUP(soc_gpio50_pm5, RSVD0, DCA, RSVD2, RSVD3, 0x10000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1729 PINGROUP(soc_gpio51_pm6, RSVD0, DCA, RSVD2, RSVD3, 0x10008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1730 PINGROUP(soc_gpio52_pm7, RSVD0, DCB, DGPU, RSVD3, 0x10010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1731 PINGROUP(soc_gpio53_pn0, RSVD0, DCB, RSVD2, RSVD3, 0x10018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1732 PINGROUP(soc_gpio54_pn1, RSVD0, SDMMC3, GP, RSVD3, 0x10020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1733 PINGROUP(soc_gpio55_pn2, RSVD0, SDMMC3, RSVD2, RSVD3, 0x10028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1734 PINGROUP(dp_aux_ch0_hpd_pm0, DP, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1735 PINGROUP(dp_aux_ch1_hpd_pm1, DP, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1736 PINGROUP(dp_aux_ch2_hpd_pm2, DP, DISPLAYA, RSVD2, RSVD3, 0x10040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1737 PINGROUP(dp_aux_ch3_hpd_pm3, DP, DISPLAYB, RSVD2, RSVD3, 0x10048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1738 PINGROUP(hdmi_cec_pm4, HDMI, RSVD1, RSVD2, RSVD3, 0x10050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
1739 PINGROUP(eqos_td3_pe4, EQOS, RSVD1, RSVD2, RSVD3, 0x15000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1740 PINGROUP(eqos_td2_pe3, EQOS, RSVD1, RSVD2, RSVD3, 0x15008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1741 PINGROUP(eqos_td1_pe2, EQOS, RSVD1, RSVD2, RSVD3, 0x15010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1742 PINGROUP(eqos_td0_pe1, EQOS, RSVD1, RSVD2, RSVD3, 0x15018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1743 PINGROUP(eqos_rd3_pf1, EQOS, RSVD1, RSVD2, RSVD3, 0x15020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1744 PINGROUP(eqos_rd2_pf0, EQOS, RSVD1, RSVD2, RSVD3, 0x15028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1745 PINGROUP(eqos_rd1_pe7, EQOS, RSVD1, RSVD2, RSVD3, 0x15030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1746 PINGROUP(eqos_sma_mdio_pf4, EQOS, RSVD1, RSVD2, RSVD3, 0x15038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1747 PINGROUP(eqos_rd0_pe6, EQOS, RSVD1, RSVD2, RSVD3, 0x15040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1748 PINGROUP(eqos_sma_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x15048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1749 PINGROUP(eqos_comp, EQOS, RSVD1, RSVD2, RSVD3, 0x15050, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_eqos"),
1750 PINGROUP(eqos_txc_pe0, EQOS, RSVD1, RSVD2, RSVD3, 0x15058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1751 PINGROUP(eqos_rxc_pf3, EQOS, RSVD1, RSVD2, RSVD3, 0x15060, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1752 PINGROUP(eqos_tx_ctl_pe5, EQOS, RSVD1, RSVD2, RSVD3, 0x15068, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1753 PINGROUP(eqos_rx_ctl_pf2, EQOS, RSVD1, RSVD2, RSVD3, 0x15070, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
1754 PINGROUP(pex_l2_clkreq_n_pk4, PE2, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1755 PINGROUP(pex_wake_n_pl2, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1756 PINGROUP(pex_l1_clkreq_n_pk2, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1757 PINGROUP(pex_l1_rst_n_pk3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1758 PINGROUP(pex_l0_clkreq_n_pk0, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1759 PINGROUP(pex_l0_rst_n_pk1, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1760 PINGROUP(pex_l2_rst_n_pk5, PE2, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1761 PINGROUP(pex_l3_clkreq_n_pk6, PE3, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1762 PINGROUP(pex_l3_rst_n_pk7, PE3, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1763 PINGROUP(pex_l4_clkreq_n_pl0, PE4, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1764 PINGROUP(pex_l4_rst_n_pl1, PE4, RSVD1, RSVD2, RSVD3, 0x7050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1765 PINGROUP(sata_dev_slp_pl3, SATA, RSVD1, RSVD2, RSVD3, 0x7058, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
1766 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl_2"),
1767 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl_2"),
1768 PINGROUP(cpu_pwr_req_1_pb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x16000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pwr_ctl"),
1769 PINGROUP(cpu_pwr_req_0_pb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x16008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pwr_ctl"),
1770 PINGROUP(qspi0_io3_pc5, QSPI0, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1771 PINGROUP(qspi0_io2_pc4, QSPI0, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1772 PINGROUP(qspi0_io1_pc3, QSPI0, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1773 PINGROUP(qspi0_io0_pc2, QSPI0, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1774 PINGROUP(qspi0_sck_pc0, QSPI0, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1775 PINGROUP(qspi0_cs_n_pc1, QSPI0, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1776 PINGROUP(qspi1_io3_pd3, QSPI1, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1777 PINGROUP(qspi1_io2_pd2, QSPI1, RSVD1, RSVD2, RSVD3, 0xB038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1778 PINGROUP(qspi1_io1_pd1, QSPI1, RSVD1, RSVD2, RSVD3, 0xB040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1779 PINGROUP(qspi1_io0_pd0, QSPI1, RSVD1, RSVD2, RSVD3, 0xB048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1780 PINGROUP(qspi1_sck_pc6, QSPI1, RSVD1, RSVD2, RSVD3, 0xB050, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1781 PINGROUP(qspi1_cs_n_pc7, QSPI1, RSVD1, RSVD2, RSVD3, 0xB058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
1782 PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB060, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_qspi"),
1783 PINGROUP(sdmmc1_clk_pj0, SDMMC1, RSVD1, MIPI, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1784 PINGROUP(sdmmc1_cmd_pj1, SDMMC1, RSVD1, MIPI, RSVD3, 0x8008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1785 PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc1_hv"),
1786 PINGROUP(sdmmc1_dat3_pj5, SDMMC1, RSVD1, MIPI, RSVD3, 0x8018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1787 PINGROUP(sdmmc1_dat2_pj4, SDMMC1, RSVD1, MIPI, RSVD3, 0x8020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1788 PINGROUP(sdmmc1_dat1_pj3, SDMMC1, RSVD1, MIPI, RSVD3, 0x8028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1789 PINGROUP(sdmmc1_dat0_pj2, SDMMC1, RSVD1, MIPI, RSVD3, 0x8030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
1790 PINGROUP(sdmmc3_dat3_po5, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1791 PINGROUP(sdmmc3_dat2_po4, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1792 PINGROUP(sdmmc3_dat1_po3, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1793 PINGROUP(sdmmc3_dat0_po2, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1794 PINGROUP(sdmmc3_comp, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA020, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc3_hv"),
1795 PINGROUP(sdmmc3_cmd_po1, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1796 PINGROUP(sdmmc3_clk_po0, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA030, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
1797 PINGROUP(sdmmc4_clk, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, -1, 5, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1798 PINGROUP(sdmmc4_cmd, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1799 PINGROUP(sdmmc4_dqs, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc4"),
1800 PINGROUP(sdmmc4_dat7, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6020, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1801 PINGROUP(sdmmc4_dat6, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6028, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1802 PINGROUP(sdmmc4_dat5, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6030, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1803 PINGROUP(sdmmc4_dat4, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6038, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1804 PINGROUP(sdmmc4_dat3, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1805 PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1806 PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1807 PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1808 PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 1, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1809 PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1810 PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1811 PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1812 PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1813 PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1814 PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 1, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1815 PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1816 PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1817 PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1818 PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1819 PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1820 PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1821 PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1822 PINGROUP(spi3_cs0_py3, SPI3, RSVD1, RSVD2, RSVD3, 0xD018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1823 PINGROUP(spi1_miso_pz4, SPI1, RSVD1, RSVD2, RSVD3, 0xD020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1824 PINGROUP(spi3_cs1_py4, SPI3, RSVD1, RSVD2, RSVD3, 0xD028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1825 PINGROUP(gp_pwm3_px3, GP, RSVD1, RSVD2, RSVD3, 0xD030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1826 PINGROUP(gp_pwm2_px2, GP, RSVD1, RSVD2, RSVD3, 0xD038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1827 PINGROUP(spi1_sck_pz3, SPI1, RSVD1, RSVD2, RSVD3, 0xD040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1828 PINGROUP(spi3_sck_py0, SPI3, RSVD1, RSVD2, RSVD3, 0xD048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1829 PINGROUP(spi1_cs1_pz7, SPI1, RSVD1, RSVD2, RSVD3, 0xD050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1830 PINGROUP(spi1_mosi_pz5, SPI1, RSVD1, RSVD2, RSVD3, 0xD058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1831 PINGROUP(spi3_mosi_py2, SPI3, RSVD1, RSVD2, RSVD3, 0xD060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1832 PINGROUP(cv_pwr_req_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0xD068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1833 PINGROUP(uart2_tx_px4, UARTB, RSVD1, RSVD2, RSVD3, 0xD070, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1834 PINGROUP(uart2_rx_px5, UARTB, RSVD1, RSVD2, RSVD3, 0xD078, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1835 PINGROUP(uart2_rts_px6, UARTB, RSVD1, RSVD2, RSVD3, 0xD080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1836 PINGROUP(uart2_cts_px7, UARTB, RSVD1, RSVD2, RSVD3, 0xD088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1837 PINGROUP(uart5_rx_py6, UARTE, RSVD1, RSVD2, RSVD3, 0xD090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1838 PINGROUP(uart5_tx_py5, UARTE, RSVD1, RSVD2, RSVD3, 0xD098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1839 PINGROUP(uart5_rts_py7, UARTE, RSVD1, RSVD2, RSVD3, 0xD0a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1840 PINGROUP(uart5_cts_pz0, UARTE, RSVD1, RSVD2, RSVD3, 0xD0a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1841 PINGROUP(usb_vbus_en0_pz1, USB, RSVD1, RSVD2, RSVD3, 0xD0b0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1842 PINGROUP(usb_vbus_en1_pz2, USB, RSVD1, RSVD2, RSVD3, 0xD0b8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1843 PINGROUP(ufs0_rst_pff1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_ufs"),
1844 PINGROUP(ufs0_ref_clk_pff0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_ufs"),
1845 };
1846
1847 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
1848 .pins = tegra194_pins,
1849 .npins = ARRAY_SIZE(tegra194_pins),
1850 .functions = tegra194_functions,
1851 .nfunctions = ARRAY_SIZE(tegra194_functions),
1852 .groups = tegra194_groups,
1853 .ngroups = ARRAY_SIZE(tegra194_groups),
1854 .hsm_in_mux = true,
1855 .schmitt_in_mux = true,
1856 .drvtype_in_mux = true,
1857 .sfsel_in_mux = true,
1858 };
1859
tegra194_pinctrl_probe(struct platform_device * pdev)1860 static int tegra194_pinctrl_probe(struct platform_device *pdev)
1861 {
1862 return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
1863 }
1864
1865 static const struct of_device_id tegra194_pinctrl_of_match[] = {
1866 { .compatible = "nvidia,tegra194-pinmux", },
1867 { },
1868 };
1869
1870 static struct platform_driver tegra194_pinctrl_driver = {
1871 .driver = {
1872 .name = "tegra194-pinctrl",
1873 .of_match_table = tegra194_pinctrl_of_match,
1874 },
1875 .probe = tegra194_pinctrl_probe,
1876 };
1877
tegra194_pinctrl_init(void)1878 static int __init tegra194_pinctrl_init(void)
1879 {
1880 return platform_driver_register(&tegra194_pinctrl_driver);
1881 }
1882 arch_initcall(tegra194_pinctrl_init);
1883