1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 //
5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 // http://www.samsung.com
7 // Copyright (c) 2012 Linaro Ltd
8 // http://www.linaro.org
9 //
10 // Author: Thomas Abraham <thomas.ab@samsung.com>
11 //
12 // This file contains the Samsung Exynos specific information required by the
13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 // external gpio and wakeup interrupt support.
15
16 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/regmap.h>
26 #include <linux/err.h>
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
29
30 #include <dt-bindings/pinctrl/samsung.h>
31
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
34
35 struct exynos_irq_chip {
36 struct irq_chip chip;
37
38 u32 eint_con;
39 u32 eint_mask;
40 u32 eint_pend;
41 u32 *eint_wake_mask_value;
42 u32 eint_wake_mask_reg;
43 void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
44 struct exynos_irq_chip *irq_chip);
45 };
46
to_exynos_irq_chip(struct irq_chip * chip)47 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
48 {
49 return container_of(chip, struct exynos_irq_chip, chip);
50 }
51
exynos_irq_mask(struct irq_data * irqd)52 static void exynos_irq_mask(struct irq_data *irqd)
53 {
54 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
55 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
58 unsigned int mask;
59 unsigned long flags;
60
61 raw_spin_lock_irqsave(&bank->slock, flags);
62
63 mask = readl(bank->eint_base + reg_mask);
64 mask |= 1 << irqd->hwirq;
65 writel(mask, bank->eint_base + reg_mask);
66
67 raw_spin_unlock_irqrestore(&bank->slock, flags);
68 }
69
exynos_irq_ack(struct irq_data * irqd)70 static void exynos_irq_ack(struct irq_data *irqd)
71 {
72 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
73 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
76
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
78 }
79
exynos_irq_unmask(struct irq_data * irqd)80 static void exynos_irq_unmask(struct irq_data *irqd)
81 {
82 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
83 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
86 unsigned int mask;
87 unsigned long flags;
88
89 /*
90 * Ack level interrupts right before unmask
91 *
92 * If we don't do this we'll get a double-interrupt. Level triggered
93 * interrupts must not fire an interrupt if the level is not
94 * _currently_ active, even if it was active while the interrupt was
95 * masked.
96 */
97 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
98 exynos_irq_ack(irqd);
99
100 raw_spin_lock_irqsave(&bank->slock, flags);
101
102 mask = readl(bank->eint_base + reg_mask);
103 mask &= ~(1 << irqd->hwirq);
104 writel(mask, bank->eint_base + reg_mask);
105
106 raw_spin_unlock_irqrestore(&bank->slock, flags);
107 }
108
exynos_irq_set_type(struct irq_data * irqd,unsigned int type)109 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
110 {
111 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
112 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
113 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
114 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
115 unsigned int con, trig_type;
116 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
117
118 switch (type) {
119 case IRQ_TYPE_EDGE_RISING:
120 trig_type = EXYNOS_EINT_EDGE_RISING;
121 break;
122 case IRQ_TYPE_EDGE_FALLING:
123 trig_type = EXYNOS_EINT_EDGE_FALLING;
124 break;
125 case IRQ_TYPE_EDGE_BOTH:
126 trig_type = EXYNOS_EINT_EDGE_BOTH;
127 break;
128 case IRQ_TYPE_LEVEL_HIGH:
129 trig_type = EXYNOS_EINT_LEVEL_HIGH;
130 break;
131 case IRQ_TYPE_LEVEL_LOW:
132 trig_type = EXYNOS_EINT_LEVEL_LOW;
133 break;
134 default:
135 pr_err("unsupported external interrupt type\n");
136 return -EINVAL;
137 }
138
139 if (type & IRQ_TYPE_EDGE_BOTH)
140 irq_set_handler_locked(irqd, handle_edge_irq);
141 else
142 irq_set_handler_locked(irqd, handle_level_irq);
143
144 con = readl(bank->eint_base + reg_con);
145 con &= ~(EXYNOS_EINT_CON_MASK << shift);
146 con |= trig_type << shift;
147 writel(con, bank->eint_base + reg_con);
148
149 return 0;
150 }
151
exynos_irq_request_resources(struct irq_data * irqd)152 static int exynos_irq_request_resources(struct irq_data *irqd)
153 {
154 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
155 const struct samsung_pin_bank_type *bank_type = bank->type;
156 unsigned long reg_con, flags;
157 unsigned int shift, mask, con;
158 int ret;
159
160 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
161 if (ret) {
162 dev_err(bank->gpio_chip.parent,
163 "unable to lock pin %s-%lu IRQ\n",
164 bank->name, irqd->hwirq);
165 return ret;
166 }
167
168 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
169 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
170 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
171
172 raw_spin_lock_irqsave(&bank->slock, flags);
173
174 con = readl(bank->pctl_base + reg_con);
175 con &= ~(mask << shift);
176 con |= EXYNOS_PIN_FUNC_EINT << shift;
177 writel(con, bank->pctl_base + reg_con);
178
179 raw_spin_unlock_irqrestore(&bank->slock, flags);
180
181 return 0;
182 }
183
exynos_irq_release_resources(struct irq_data * irqd)184 static void exynos_irq_release_resources(struct irq_data *irqd)
185 {
186 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
187 const struct samsung_pin_bank_type *bank_type = bank->type;
188 unsigned long reg_con, flags;
189 unsigned int shift, mask, con;
190
191 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
192 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
193 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
194
195 raw_spin_lock_irqsave(&bank->slock, flags);
196
197 con = readl(bank->pctl_base + reg_con);
198 con &= ~(mask << shift);
199 con |= EXYNOS_PIN_FUNC_INPUT << shift;
200 writel(con, bank->pctl_base + reg_con);
201
202 raw_spin_unlock_irqrestore(&bank->slock, flags);
203
204 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
205 }
206
207 /*
208 * irq_chip for gpio interrupts.
209 */
210 static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
211 .chip = {
212 .name = "exynos_gpio_irq_chip",
213 .irq_unmask = exynos_irq_unmask,
214 .irq_mask = exynos_irq_mask,
215 .irq_ack = exynos_irq_ack,
216 .irq_set_type = exynos_irq_set_type,
217 .irq_request_resources = exynos_irq_request_resources,
218 .irq_release_resources = exynos_irq_release_resources,
219 },
220 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
221 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
222 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
223 /* eint_wake_mask_value not used */
224 };
225
exynos_eint_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)226 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
227 irq_hw_number_t hw)
228 {
229 struct samsung_pin_bank *b = h->host_data;
230
231 irq_set_chip_data(virq, b);
232 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
233 handle_level_irq);
234 return 0;
235 }
236
237 /*
238 * irq domain callbacks for external gpio and wakeup interrupt controllers.
239 */
240 static const struct irq_domain_ops exynos_eint_irqd_ops = {
241 .map = exynos_eint_irq_map,
242 .xlate = irq_domain_xlate_twocell,
243 };
244
exynos_eint_gpio_irq(int irq,void * data)245 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
246 {
247 struct samsung_pinctrl_drv_data *d = data;
248 struct samsung_pin_bank *bank = d->pin_banks;
249 unsigned int svc, group, pin;
250 int ret;
251
252 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
253 group = EXYNOS_SVC_GROUP(svc);
254 pin = svc & EXYNOS_SVC_NUM_MASK;
255
256 if (!group)
257 return IRQ_HANDLED;
258 bank += (group - 1);
259
260 ret = generic_handle_domain_irq(bank->irq_domain, pin);
261 if (ret)
262 return IRQ_NONE;
263
264 return IRQ_HANDLED;
265 }
266
267 struct exynos_eint_gpio_save {
268 u32 eint_con;
269 u32 eint_fltcon0;
270 u32 eint_fltcon1;
271 u32 eint_mask;
272 };
273
274 /*
275 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
276 * @d: driver data of samsung pinctrl driver.
277 */
exynos_eint_gpio_init(struct samsung_pinctrl_drv_data * d)278 __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
279 {
280 struct samsung_pin_bank *bank;
281 struct device *dev = d->dev;
282 int ret;
283 int i;
284
285 if (!d->irq) {
286 dev_err(dev, "irq number not available\n");
287 return -EINVAL;
288 }
289
290 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
291 0, dev_name(dev), d);
292 if (ret) {
293 dev_err(dev, "irq request failed\n");
294 return -ENXIO;
295 }
296
297 bank = d->pin_banks;
298 for (i = 0; i < d->nr_banks; ++i, ++bank) {
299 if (bank->eint_type != EINT_TYPE_GPIO)
300 continue;
301
302 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
303 sizeof(*bank->irq_chip), GFP_KERNEL);
304 if (!bank->irq_chip) {
305 ret = -ENOMEM;
306 goto err_domains;
307 }
308 bank->irq_chip->chip.name = bank->name;
309
310 bank->irq_domain = irq_domain_create_linear(bank->fwnode,
311 bank->nr_pins, &exynos_eint_irqd_ops, bank);
312 if (!bank->irq_domain) {
313 dev_err(dev, "gpio irq domain add failed\n");
314 ret = -ENXIO;
315 goto err_domains;
316 }
317
318 bank->soc_priv = devm_kzalloc(d->dev,
319 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
320 if (!bank->soc_priv) {
321 irq_domain_remove(bank->irq_domain);
322 ret = -ENOMEM;
323 goto err_domains;
324 }
325
326 }
327
328 return 0;
329
330 err_domains:
331 for (--i, --bank; i >= 0; --i, --bank) {
332 if (bank->eint_type != EINT_TYPE_GPIO)
333 continue;
334 irq_domain_remove(bank->irq_domain);
335 }
336
337 return ret;
338 }
339
exynos_wkup_irq_set_wake(struct irq_data * irqd,unsigned int on)340 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
341 {
342 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
343 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
344 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
345 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
346
347 pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled",
348 irqd->irq, bank->name, irqd->hwirq);
349
350 if (!on)
351 *our_chip->eint_wake_mask_value |= bit;
352 else
353 *our_chip->eint_wake_mask_value &= ~bit;
354
355 return 0;
356 }
357
358 static void
exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data * drvdata,struct exynos_irq_chip * irq_chip)359 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
360 struct exynos_irq_chip *irq_chip)
361 {
362 struct regmap *pmu_regs;
363
364 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
365 dev_warn(drvdata->dev,
366 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
367 return;
368 }
369
370 pmu_regs = drvdata->retention_ctrl->priv;
371 dev_info(drvdata->dev,
372 "Setting external wakeup interrupt mask: 0x%x\n",
373 *irq_chip->eint_wake_mask_value);
374
375 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
376 *irq_chip->eint_wake_mask_value);
377 }
378
379 static void
s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data * drvdata,struct exynos_irq_chip * irq_chip)380 s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
381 struct exynos_irq_chip *irq_chip)
382
383 {
384 void __iomem *clk_base;
385
386 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
387 dev_warn(drvdata->dev,
388 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
389 return;
390 }
391
392
393 clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
394
395 __raw_writel(*irq_chip->eint_wake_mask_value,
396 clk_base + irq_chip->eint_wake_mask_reg);
397 }
398
399 static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED;
400 /*
401 * irq_chip for wakeup interrupts
402 */
403 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = {
404 .chip = {
405 .name = "s5pv210_wkup_irq_chip",
406 .irq_unmask = exynos_irq_unmask,
407 .irq_mask = exynos_irq_mask,
408 .irq_ack = exynos_irq_ack,
409 .irq_set_type = exynos_irq_set_type,
410 .irq_set_wake = exynos_wkup_irq_set_wake,
411 .irq_request_resources = exynos_irq_request_resources,
412 .irq_release_resources = exynos_irq_release_resources,
413 },
414 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
415 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
416 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
417 .eint_wake_mask_value = &eint_wake_mask_value,
418 /* Only differences with exynos4210_wkup_irq_chip: */
419 .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
420 .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
421 };
422
423 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
424 .chip = {
425 .name = "exynos4210_wkup_irq_chip",
426 .irq_unmask = exynos_irq_unmask,
427 .irq_mask = exynos_irq_mask,
428 .irq_ack = exynos_irq_ack,
429 .irq_set_type = exynos_irq_set_type,
430 .irq_set_wake = exynos_wkup_irq_set_wake,
431 .irq_request_resources = exynos_irq_request_resources,
432 .irq_release_resources = exynos_irq_release_resources,
433 },
434 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
435 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
436 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
437 .eint_wake_mask_value = &eint_wake_mask_value,
438 .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
439 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
440 };
441
442 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
443 .chip = {
444 .name = "exynos7_wkup_irq_chip",
445 .irq_unmask = exynos_irq_unmask,
446 .irq_mask = exynos_irq_mask,
447 .irq_ack = exynos_irq_ack,
448 .irq_set_type = exynos_irq_set_type,
449 .irq_set_wake = exynos_wkup_irq_set_wake,
450 .irq_request_resources = exynos_irq_request_resources,
451 .irq_release_resources = exynos_irq_release_resources,
452 },
453 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
454 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
455 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
456 .eint_wake_mask_value = &eint_wake_mask_value,
457 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
458 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
459 };
460
461 /* list of external wakeup controllers supported */
462 static const struct of_device_id exynos_wkup_irq_ids[] = {
463 { .compatible = "samsung,s5pv210-wakeup-eint",
464 .data = &s5pv210_wkup_irq_chip },
465 { .compatible = "samsung,exynos4210-wakeup-eint",
466 .data = &exynos4210_wkup_irq_chip },
467 { .compatible = "samsung,exynos7-wakeup-eint",
468 .data = &exynos7_wkup_irq_chip },
469 { .compatible = "samsung,exynos850-wakeup-eint",
470 .data = &exynos7_wkup_irq_chip },
471 { .compatible = "samsung,exynosautov9-wakeup-eint",
472 .data = &exynos7_wkup_irq_chip },
473 { }
474 };
475
476 /* interrupt handler for wakeup interrupts 0..15 */
exynos_irq_eint0_15(struct irq_desc * desc)477 static void exynos_irq_eint0_15(struct irq_desc *desc)
478 {
479 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
480 struct samsung_pin_bank *bank = eintd->bank;
481 struct irq_chip *chip = irq_desc_get_chip(desc);
482
483 chained_irq_enter(chip, desc);
484
485 generic_handle_domain_irq(bank->irq_domain, eintd->irq);
486
487 chained_irq_exit(chip, desc);
488 }
489
exynos_irq_demux_eint(unsigned int pend,struct irq_domain * domain)490 static inline void exynos_irq_demux_eint(unsigned int pend,
491 struct irq_domain *domain)
492 {
493 unsigned int irq;
494
495 while (pend) {
496 irq = fls(pend) - 1;
497 generic_handle_domain_irq(domain, irq);
498 pend &= ~(1 << irq);
499 }
500 }
501
502 /* interrupt handler for wakeup interrupt 16 */
exynos_irq_demux_eint16_31(struct irq_desc * desc)503 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
504 {
505 struct irq_chip *chip = irq_desc_get_chip(desc);
506 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
507 unsigned int pend;
508 unsigned int mask;
509 int i;
510
511 chained_irq_enter(chip, desc);
512
513 for (i = 0; i < eintd->nr_banks; ++i) {
514 struct samsung_pin_bank *b = eintd->banks[i];
515 pend = readl(b->eint_base + b->irq_chip->eint_pend
516 + b->eint_offset);
517 mask = readl(b->eint_base + b->irq_chip->eint_mask
518 + b->eint_offset);
519 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
520 }
521
522 chained_irq_exit(chip, desc);
523 }
524
525 /*
526 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
527 * @d: driver data of samsung pinctrl driver.
528 */
exynos_eint_wkup_init(struct samsung_pinctrl_drv_data * d)529 __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
530 {
531 struct device *dev = d->dev;
532 struct device_node *wkup_np = NULL;
533 struct device_node *np;
534 struct samsung_pin_bank *bank;
535 struct exynos_weint_data *weint_data;
536 struct exynos_muxed_weint_data *muxed_data;
537 const struct exynos_irq_chip *irq_chip;
538 unsigned int muxed_banks = 0;
539 unsigned int i;
540 int idx, irq;
541
542 for_each_child_of_node(dev->of_node, np) {
543 const struct of_device_id *match;
544
545 match = of_match_node(exynos_wkup_irq_ids, np);
546 if (match) {
547 irq_chip = match->data;
548 wkup_np = np;
549 break;
550 }
551 }
552 if (!wkup_np)
553 return -ENODEV;
554
555 bank = d->pin_banks;
556 for (i = 0; i < d->nr_banks; ++i, ++bank) {
557 if (bank->eint_type != EINT_TYPE_WKUP)
558 continue;
559
560 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
561 GFP_KERNEL);
562 if (!bank->irq_chip) {
563 of_node_put(wkup_np);
564 return -ENOMEM;
565 }
566 bank->irq_chip->chip.name = bank->name;
567
568 bank->irq_domain = irq_domain_create_linear(bank->fwnode,
569 bank->nr_pins, &exynos_eint_irqd_ops, bank);
570 if (!bank->irq_domain) {
571 dev_err(dev, "wkup irq domain add failed\n");
572 of_node_put(wkup_np);
573 return -ENXIO;
574 }
575
576 if (!fwnode_property_present(bank->fwnode, "interrupts")) {
577 bank->eint_type = EINT_TYPE_WKUP_MUX;
578 ++muxed_banks;
579 continue;
580 }
581
582 weint_data = devm_kcalloc(dev,
583 bank->nr_pins, sizeof(*weint_data),
584 GFP_KERNEL);
585 if (!weint_data) {
586 of_node_put(wkup_np);
587 return -ENOMEM;
588 }
589
590 for (idx = 0; idx < bank->nr_pins; ++idx) {
591 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
592 if (!irq) {
593 dev_err(dev, "irq number for eint-%s-%d not found\n",
594 bank->name, idx);
595 continue;
596 }
597 weint_data[idx].irq = idx;
598 weint_data[idx].bank = bank;
599 irq_set_chained_handler_and_data(irq,
600 exynos_irq_eint0_15,
601 &weint_data[idx]);
602 }
603 }
604
605 if (!muxed_banks) {
606 of_node_put(wkup_np);
607 return 0;
608 }
609
610 irq = irq_of_parse_and_map(wkup_np, 0);
611 of_node_put(wkup_np);
612 if (!irq) {
613 dev_err(dev, "irq number for muxed EINTs not found\n");
614 return 0;
615 }
616
617 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
618 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
619 if (!muxed_data)
620 return -ENOMEM;
621
622 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
623 muxed_data);
624
625 bank = d->pin_banks;
626 idx = 0;
627 for (i = 0; i < d->nr_banks; ++i, ++bank) {
628 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
629 continue;
630
631 muxed_data->banks[idx++] = bank;
632 }
633 muxed_data->nr_banks = muxed_banks;
634
635 return 0;
636 }
637
exynos_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)638 static void exynos_pinctrl_suspend_bank(
639 struct samsung_pinctrl_drv_data *drvdata,
640 struct samsung_pin_bank *bank)
641 {
642 struct exynos_eint_gpio_save *save = bank->soc_priv;
643 void __iomem *regs = bank->eint_base;
644
645 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
646 + bank->eint_offset);
647 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
648 + 2 * bank->eint_offset);
649 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
650 + 2 * bank->eint_offset + 4);
651 save->eint_mask = readl(regs + bank->irq_chip->eint_mask
652 + bank->eint_offset);
653
654 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
655 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
656 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
657 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
658 }
659
exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data * drvdata)660 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
661 {
662 struct samsung_pin_bank *bank = drvdata->pin_banks;
663 struct exynos_irq_chip *irq_chip = NULL;
664 int i;
665
666 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
667 if (bank->eint_type == EINT_TYPE_GPIO)
668 exynos_pinctrl_suspend_bank(drvdata, bank);
669 else if (bank->eint_type == EINT_TYPE_WKUP) {
670 if (!irq_chip) {
671 irq_chip = bank->irq_chip;
672 irq_chip->set_eint_wakeup_mask(drvdata,
673 irq_chip);
674 }
675 }
676 }
677 }
678
exynos_pinctrl_resume_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)679 static void exynos_pinctrl_resume_bank(
680 struct samsung_pinctrl_drv_data *drvdata,
681 struct samsung_pin_bank *bank)
682 {
683 struct exynos_eint_gpio_save *save = bank->soc_priv;
684 void __iomem *regs = bank->eint_base;
685
686 pr_debug("%s: con %#010x => %#010x\n", bank->name,
687 readl(regs + EXYNOS_GPIO_ECON_OFFSET
688 + bank->eint_offset), save->eint_con);
689 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
690 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
691 + 2 * bank->eint_offset), save->eint_fltcon0);
692 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
693 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
694 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
695 pr_debug("%s: mask %#010x => %#010x\n", bank->name,
696 readl(regs + bank->irq_chip->eint_mask
697 + bank->eint_offset), save->eint_mask);
698
699 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
700 + bank->eint_offset);
701 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
702 + 2 * bank->eint_offset);
703 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
704 + 2 * bank->eint_offset + 4);
705 writel(save->eint_mask, regs + bank->irq_chip->eint_mask
706 + bank->eint_offset);
707 }
708
exynos_pinctrl_resume(struct samsung_pinctrl_drv_data * drvdata)709 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
710 {
711 struct samsung_pin_bank *bank = drvdata->pin_banks;
712 int i;
713
714 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
715 if (bank->eint_type == EINT_TYPE_GPIO)
716 exynos_pinctrl_resume_bank(drvdata, bank);
717 }
718
exynos_retention_enable(struct samsung_pinctrl_drv_data * drvdata)719 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
720 {
721 if (drvdata->retention_ctrl->refcnt)
722 atomic_inc(drvdata->retention_ctrl->refcnt);
723 }
724
exynos_retention_disable(struct samsung_pinctrl_drv_data * drvdata)725 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
726 {
727 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl;
728 struct regmap *pmu_regs = ctrl->priv;
729 int i;
730
731 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt))
732 return;
733
734 for (i = 0; i < ctrl->nr_regs; i++)
735 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
736 }
737
738 struct samsung_retention_ctrl *
exynos_retention_init(struct samsung_pinctrl_drv_data * drvdata,const struct samsung_retention_data * data)739 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
740 const struct samsung_retention_data *data)
741 {
742 struct samsung_retention_ctrl *ctrl;
743 struct regmap *pmu_regs;
744 int i;
745
746 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
747 if (!ctrl)
748 return ERR_PTR(-ENOMEM);
749
750 pmu_regs = exynos_get_pmu_regmap();
751 if (IS_ERR(pmu_regs))
752 return ERR_CAST(pmu_regs);
753
754 ctrl->priv = pmu_regs;
755 ctrl->regs = data->regs;
756 ctrl->nr_regs = data->nr_regs;
757 ctrl->value = data->value;
758 ctrl->refcnt = data->refcnt;
759 ctrl->enable = exynos_retention_enable;
760 ctrl->disable = exynos_retention_disable;
761
762 /* Ensure that retention is disabled on driver init */
763 for (i = 0; i < ctrl->nr_regs; i++)
764 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
765
766 return ctrl;
767 }
768