1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30
31 #include "../../pci.h"
32 #include "pcie-designware.h"
33
34 #define PCIE20_PARF_SYS_CTRL 0x00
35 #define MST_WAKEUP_EN BIT(13)
36 #define SLV_WAKEUP_EN BIT(12)
37 #define MSTR_ACLK_CGC_DIS BIT(10)
38 #define SLV_ACLK_CGC_DIS BIT(9)
39 #define CORE_CLK_CGC_DIS BIT(6)
40 #define AUX_PWR_DET BIT(4)
41 #define L23_CLK_RMV_DIS BIT(2)
42 #define L1_CLK_RMV_DIS BIT(1)
43
44 #define PCIE20_PARF_PHY_CTRL 0x40
45 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
46 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
47
48 #define PCIE20_PARF_PHY_REFCLK 0x4C
49 #define PHY_REFCLK_SSP_EN BIT(16)
50 #define PHY_REFCLK_USE_PAD BIT(12)
51
52 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
53 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
54 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
55 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
56 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
57 #define PCIE20_PARF_LTSSM 0x1B0
58 #define PCIE20_PARF_SID_OFFSET 0x234
59 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
60 #define PCIE20_PARF_DEVICE_TYPE 0x1000
61 #define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
62
63 #define PCIE20_ELBI_SYS_CTRL 0x04
64 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
65
66 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
67 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
68 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
69 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
70 #define CFG_BRIDGE_SB_INIT BIT(0)
71
72 #define PCIE_CAP_LINK1_VAL 0x2FD7F
73
74 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
75
76 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
77 #define DBI_RO_WR_EN 1
78
79 #define PERST_DELAY_US 1000
80 /* PARF registers */
81 #define PCIE20_PARF_PCS_DEEMPH 0x34
82 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
83 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
84 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
85
86 #define PCIE20_PARF_PCS_SWING 0x38
87 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
88 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
89
90 #define PCIE20_PARF_CONFIG_BITS 0x50
91 #define PHY_RX0_EQ(x) ((x) << 24)
92
93 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
94 #define SLV_ADDR_SPACE_SZ 0x10000000
95
96 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
97
98 #define DEVICE_TYPE_RC 0x4
99
100 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
101 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
102
103 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
104
105 struct qcom_pcie_resources_2_1_0 {
106 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
107 struct reset_control *pci_reset;
108 struct reset_control *axi_reset;
109 struct reset_control *ahb_reset;
110 struct reset_control *por_reset;
111 struct reset_control *phy_reset;
112 struct reset_control *ext_reset;
113 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
114 };
115
116 struct qcom_pcie_resources_1_0_0 {
117 struct clk *iface;
118 struct clk *aux;
119 struct clk *master_bus;
120 struct clk *slave_bus;
121 struct reset_control *core;
122 struct regulator *vdda;
123 };
124
125 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
126 struct qcom_pcie_resources_2_3_2 {
127 struct clk *aux_clk;
128 struct clk *master_clk;
129 struct clk *slave_clk;
130 struct clk *cfg_clk;
131 struct clk *pipe_clk;
132 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
133 };
134
135 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
136 struct qcom_pcie_resources_2_4_0 {
137 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
138 int num_clks;
139 struct reset_control *axi_m_reset;
140 struct reset_control *axi_s_reset;
141 struct reset_control *pipe_reset;
142 struct reset_control *axi_m_vmid_reset;
143 struct reset_control *axi_s_xpu_reset;
144 struct reset_control *parf_reset;
145 struct reset_control *phy_reset;
146 struct reset_control *axi_m_sticky_reset;
147 struct reset_control *pipe_sticky_reset;
148 struct reset_control *pwr_reset;
149 struct reset_control *ahb_reset;
150 struct reset_control *phy_ahb_reset;
151 };
152
153 struct qcom_pcie_resources_2_3_3 {
154 struct clk *iface;
155 struct clk *axi_m_clk;
156 struct clk *axi_s_clk;
157 struct clk *ahb_clk;
158 struct clk *aux_clk;
159 struct reset_control *rst[7];
160 };
161
162 /* 6 clocks typically, 7 for sm8250 */
163 struct qcom_pcie_resources_2_7_0 {
164 struct clk_bulk_data clks[9];
165 int num_clks;
166 struct regulator_bulk_data supplies[2];
167 struct reset_control *pci_reset;
168 struct clk *pipe_clk;
169 struct clk *pipe_clk_src;
170 struct clk *phy_pipe_clk;
171 struct clk *ref_clk_src;
172 };
173
174 union qcom_pcie_resources {
175 struct qcom_pcie_resources_1_0_0 v1_0_0;
176 struct qcom_pcie_resources_2_1_0 v2_1_0;
177 struct qcom_pcie_resources_2_3_2 v2_3_2;
178 struct qcom_pcie_resources_2_3_3 v2_3_3;
179 struct qcom_pcie_resources_2_4_0 v2_4_0;
180 struct qcom_pcie_resources_2_7_0 v2_7_0;
181 };
182
183 struct qcom_pcie;
184
185 struct qcom_pcie_ops {
186 int (*get_resources)(struct qcom_pcie *pcie);
187 int (*init)(struct qcom_pcie *pcie);
188 int (*post_init)(struct qcom_pcie *pcie);
189 void (*deinit)(struct qcom_pcie *pcie);
190 void (*post_deinit)(struct qcom_pcie *pcie);
191 void (*ltssm_enable)(struct qcom_pcie *pcie);
192 int (*config_sid)(struct qcom_pcie *pcie);
193 };
194
195 struct qcom_pcie_cfg {
196 const struct qcom_pcie_ops *ops;
197 unsigned int pipe_clk_need_muxing:1;
198 unsigned int has_tbu_clk:1;
199 unsigned int has_ddrss_sf_tbu_clk:1;
200 unsigned int has_aggre0_clk:1;
201 unsigned int has_aggre1_clk:1;
202 };
203
204 struct qcom_pcie {
205 struct dw_pcie *pci;
206 void __iomem *parf; /* DT parf */
207 void __iomem *elbi; /* DT elbi */
208 union qcom_pcie_resources res;
209 struct phy *phy;
210 struct gpio_desc *reset;
211 const struct qcom_pcie_cfg *cfg;
212 };
213
214 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
215
qcom_ep_reset_assert(struct qcom_pcie * pcie)216 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
217 {
218 gpiod_set_value_cansleep(pcie->reset, 1);
219 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
220 }
221
qcom_ep_reset_deassert(struct qcom_pcie * pcie)222 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
223 {
224 /* Ensure that PERST has been asserted for at least 100 ms */
225 msleep(100);
226 gpiod_set_value_cansleep(pcie->reset, 0);
227 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
228 }
229
qcom_pcie_start_link(struct dw_pcie * pci)230 static int qcom_pcie_start_link(struct dw_pcie *pci)
231 {
232 struct qcom_pcie *pcie = to_qcom_pcie(pci);
233
234 /* Enable Link Training state machine */
235 if (pcie->cfg->ops->ltssm_enable)
236 pcie->cfg->ops->ltssm_enable(pcie);
237
238 return 0;
239 }
240
qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie * pcie)241 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
242 {
243 u32 val;
244
245 /* enable link training */
246 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
247 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
248 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
249 }
250
qcom_pcie_get_resources_2_1_0(struct qcom_pcie * pcie)251 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
252 {
253 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
254 struct dw_pcie *pci = pcie->pci;
255 struct device *dev = pci->dev;
256 int ret;
257
258 res->supplies[0].supply = "vdda";
259 res->supplies[1].supply = "vdda_phy";
260 res->supplies[2].supply = "vdda_refclk";
261 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
262 res->supplies);
263 if (ret)
264 return ret;
265
266 res->clks[0].id = "iface";
267 res->clks[1].id = "core";
268 res->clks[2].id = "phy";
269 res->clks[3].id = "aux";
270 res->clks[4].id = "ref";
271
272 /* iface, core, phy are required */
273 ret = devm_clk_bulk_get(dev, 3, res->clks);
274 if (ret < 0)
275 return ret;
276
277 /* aux, ref are optional */
278 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
279 if (ret < 0)
280 return ret;
281
282 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
283 if (IS_ERR(res->pci_reset))
284 return PTR_ERR(res->pci_reset);
285
286 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
287 if (IS_ERR(res->axi_reset))
288 return PTR_ERR(res->axi_reset);
289
290 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
291 if (IS_ERR(res->ahb_reset))
292 return PTR_ERR(res->ahb_reset);
293
294 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
295 if (IS_ERR(res->por_reset))
296 return PTR_ERR(res->por_reset);
297
298 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
299 if (IS_ERR(res->ext_reset))
300 return PTR_ERR(res->ext_reset);
301
302 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
303 return PTR_ERR_OR_ZERO(res->phy_reset);
304 }
305
qcom_pcie_deinit_2_1_0(struct qcom_pcie * pcie)306 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
307 {
308 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
309
310 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
311 reset_control_assert(res->pci_reset);
312 reset_control_assert(res->axi_reset);
313 reset_control_assert(res->ahb_reset);
314 reset_control_assert(res->por_reset);
315 reset_control_assert(res->ext_reset);
316 reset_control_assert(res->phy_reset);
317
318 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
319
320 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
321 }
322
qcom_pcie_init_2_1_0(struct qcom_pcie * pcie)323 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
324 {
325 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
326 struct dw_pcie *pci = pcie->pci;
327 struct device *dev = pci->dev;
328 struct device_node *node = dev->of_node;
329 u32 val;
330 int ret;
331
332 /* reset the PCIe interface as uboot can leave it undefined state */
333 reset_control_assert(res->pci_reset);
334 reset_control_assert(res->axi_reset);
335 reset_control_assert(res->ahb_reset);
336 reset_control_assert(res->por_reset);
337 reset_control_assert(res->ext_reset);
338 reset_control_assert(res->phy_reset);
339
340 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
341 if (ret < 0) {
342 dev_err(dev, "cannot enable regulators\n");
343 return ret;
344 }
345
346 ret = reset_control_deassert(res->ahb_reset);
347 if (ret) {
348 dev_err(dev, "cannot deassert ahb reset\n");
349 goto err_deassert_ahb;
350 }
351
352 ret = reset_control_deassert(res->ext_reset);
353 if (ret) {
354 dev_err(dev, "cannot deassert ext reset\n");
355 goto err_deassert_ext;
356 }
357
358 ret = reset_control_deassert(res->phy_reset);
359 if (ret) {
360 dev_err(dev, "cannot deassert phy reset\n");
361 goto err_deassert_phy;
362 }
363
364 ret = reset_control_deassert(res->pci_reset);
365 if (ret) {
366 dev_err(dev, "cannot deassert pci reset\n");
367 goto err_deassert_pci;
368 }
369
370 ret = reset_control_deassert(res->por_reset);
371 if (ret) {
372 dev_err(dev, "cannot deassert por reset\n");
373 goto err_deassert_por;
374 }
375
376 ret = reset_control_deassert(res->axi_reset);
377 if (ret) {
378 dev_err(dev, "cannot deassert axi reset\n");
379 goto err_deassert_axi;
380 }
381
382 /* enable PCIe clocks and resets */
383 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
384 val &= ~BIT(0);
385 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
386
387 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
388 if (ret)
389 goto err_clks;
390
391 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
392 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
393 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
394 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
395 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
396 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
397 writel(PCS_SWING_TX_SWING_FULL(120) |
398 PCS_SWING_TX_SWING_LOW(120),
399 pcie->parf + PCIE20_PARF_PCS_SWING);
400 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
401 }
402
403 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
404 /* set TX termination offset */
405 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
406 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
407 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
408 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
409 }
410
411 /* enable external reference clock */
412 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
413 /* USE_PAD is required only for ipq806x */
414 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
415 val &= ~PHY_REFCLK_USE_PAD;
416 val |= PHY_REFCLK_SSP_EN;
417 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
418
419 /* wait for clock acquisition */
420 usleep_range(1000, 1500);
421
422 /* Set the Max TLP size to 2K, instead of using default of 4K */
423 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
424 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
425 writel(CFG_BRIDGE_SB_INIT,
426 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
427
428 return 0;
429
430 err_clks:
431 reset_control_assert(res->axi_reset);
432 err_deassert_axi:
433 reset_control_assert(res->por_reset);
434 err_deassert_por:
435 reset_control_assert(res->pci_reset);
436 err_deassert_pci:
437 reset_control_assert(res->phy_reset);
438 err_deassert_phy:
439 reset_control_assert(res->ext_reset);
440 err_deassert_ext:
441 reset_control_assert(res->ahb_reset);
442 err_deassert_ahb:
443 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
444
445 return ret;
446 }
447
qcom_pcie_get_resources_1_0_0(struct qcom_pcie * pcie)448 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
449 {
450 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
451 struct dw_pcie *pci = pcie->pci;
452 struct device *dev = pci->dev;
453
454 res->vdda = devm_regulator_get(dev, "vdda");
455 if (IS_ERR(res->vdda))
456 return PTR_ERR(res->vdda);
457
458 res->iface = devm_clk_get(dev, "iface");
459 if (IS_ERR(res->iface))
460 return PTR_ERR(res->iface);
461
462 res->aux = devm_clk_get(dev, "aux");
463 if (IS_ERR(res->aux))
464 return PTR_ERR(res->aux);
465
466 res->master_bus = devm_clk_get(dev, "master_bus");
467 if (IS_ERR(res->master_bus))
468 return PTR_ERR(res->master_bus);
469
470 res->slave_bus = devm_clk_get(dev, "slave_bus");
471 if (IS_ERR(res->slave_bus))
472 return PTR_ERR(res->slave_bus);
473
474 res->core = devm_reset_control_get_exclusive(dev, "core");
475 return PTR_ERR_OR_ZERO(res->core);
476 }
477
qcom_pcie_deinit_1_0_0(struct qcom_pcie * pcie)478 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
479 {
480 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
481
482 reset_control_assert(res->core);
483 clk_disable_unprepare(res->slave_bus);
484 clk_disable_unprepare(res->master_bus);
485 clk_disable_unprepare(res->iface);
486 clk_disable_unprepare(res->aux);
487 regulator_disable(res->vdda);
488 }
489
qcom_pcie_init_1_0_0(struct qcom_pcie * pcie)490 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
491 {
492 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
493 struct dw_pcie *pci = pcie->pci;
494 struct device *dev = pci->dev;
495 int ret;
496
497 ret = reset_control_deassert(res->core);
498 if (ret) {
499 dev_err(dev, "cannot deassert core reset\n");
500 return ret;
501 }
502
503 ret = clk_prepare_enable(res->aux);
504 if (ret) {
505 dev_err(dev, "cannot prepare/enable aux clock\n");
506 goto err_res;
507 }
508
509 ret = clk_prepare_enable(res->iface);
510 if (ret) {
511 dev_err(dev, "cannot prepare/enable iface clock\n");
512 goto err_aux;
513 }
514
515 ret = clk_prepare_enable(res->master_bus);
516 if (ret) {
517 dev_err(dev, "cannot prepare/enable master_bus clock\n");
518 goto err_iface;
519 }
520
521 ret = clk_prepare_enable(res->slave_bus);
522 if (ret) {
523 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
524 goto err_master;
525 }
526
527 ret = regulator_enable(res->vdda);
528 if (ret) {
529 dev_err(dev, "cannot enable vdda regulator\n");
530 goto err_slave;
531 }
532
533 /* change DBI base address */
534 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
535
536 if (IS_ENABLED(CONFIG_PCI_MSI)) {
537 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
538
539 val |= BIT(31);
540 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
541 }
542
543 return 0;
544 err_slave:
545 clk_disable_unprepare(res->slave_bus);
546 err_master:
547 clk_disable_unprepare(res->master_bus);
548 err_iface:
549 clk_disable_unprepare(res->iface);
550 err_aux:
551 clk_disable_unprepare(res->aux);
552 err_res:
553 reset_control_assert(res->core);
554
555 return ret;
556 }
557
qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie * pcie)558 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
559 {
560 u32 val;
561
562 /* enable link training */
563 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
564 val |= BIT(8);
565 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
566 }
567
qcom_pcie_get_resources_2_3_2(struct qcom_pcie * pcie)568 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
569 {
570 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
571 struct dw_pcie *pci = pcie->pci;
572 struct device *dev = pci->dev;
573 int ret;
574
575 res->supplies[0].supply = "vdda";
576 res->supplies[1].supply = "vddpe-3v3";
577 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
578 res->supplies);
579 if (ret)
580 return ret;
581
582 res->aux_clk = devm_clk_get(dev, "aux");
583 if (IS_ERR(res->aux_clk))
584 return PTR_ERR(res->aux_clk);
585
586 res->cfg_clk = devm_clk_get(dev, "cfg");
587 if (IS_ERR(res->cfg_clk))
588 return PTR_ERR(res->cfg_clk);
589
590 res->master_clk = devm_clk_get(dev, "bus_master");
591 if (IS_ERR(res->master_clk))
592 return PTR_ERR(res->master_clk);
593
594 res->slave_clk = devm_clk_get(dev, "bus_slave");
595 if (IS_ERR(res->slave_clk))
596 return PTR_ERR(res->slave_clk);
597
598 res->pipe_clk = devm_clk_get(dev, "pipe");
599 return PTR_ERR_OR_ZERO(res->pipe_clk);
600 }
601
qcom_pcie_deinit_2_3_2(struct qcom_pcie * pcie)602 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
603 {
604 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
605
606 clk_disable_unprepare(res->slave_clk);
607 clk_disable_unprepare(res->master_clk);
608 clk_disable_unprepare(res->cfg_clk);
609 clk_disable_unprepare(res->aux_clk);
610
611 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
612 }
613
qcom_pcie_post_deinit_2_3_2(struct qcom_pcie * pcie)614 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
615 {
616 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
617
618 clk_disable_unprepare(res->pipe_clk);
619 }
620
qcom_pcie_init_2_3_2(struct qcom_pcie * pcie)621 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
622 {
623 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
624 struct dw_pcie *pci = pcie->pci;
625 struct device *dev = pci->dev;
626 u32 val;
627 int ret;
628
629 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
630 if (ret < 0) {
631 dev_err(dev, "cannot enable regulators\n");
632 return ret;
633 }
634
635 ret = clk_prepare_enable(res->aux_clk);
636 if (ret) {
637 dev_err(dev, "cannot prepare/enable aux clock\n");
638 goto err_aux_clk;
639 }
640
641 ret = clk_prepare_enable(res->cfg_clk);
642 if (ret) {
643 dev_err(dev, "cannot prepare/enable cfg clock\n");
644 goto err_cfg_clk;
645 }
646
647 ret = clk_prepare_enable(res->master_clk);
648 if (ret) {
649 dev_err(dev, "cannot prepare/enable master clock\n");
650 goto err_master_clk;
651 }
652
653 ret = clk_prepare_enable(res->slave_clk);
654 if (ret) {
655 dev_err(dev, "cannot prepare/enable slave clock\n");
656 goto err_slave_clk;
657 }
658
659 /* enable PCIe clocks and resets */
660 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
661 val &= ~BIT(0);
662 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
663
664 /* change DBI base address */
665 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
666
667 /* MAC PHY_POWERDOWN MUX DISABLE */
668 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
669 val &= ~BIT(29);
670 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
671
672 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
673 val |= BIT(4);
674 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
675
676 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
677 val |= BIT(31);
678 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
679
680 return 0;
681
682 err_slave_clk:
683 clk_disable_unprepare(res->master_clk);
684 err_master_clk:
685 clk_disable_unprepare(res->cfg_clk);
686 err_cfg_clk:
687 clk_disable_unprepare(res->aux_clk);
688
689 err_aux_clk:
690 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
691
692 return ret;
693 }
694
qcom_pcie_post_init_2_3_2(struct qcom_pcie * pcie)695 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
696 {
697 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
698 struct dw_pcie *pci = pcie->pci;
699 struct device *dev = pci->dev;
700 int ret;
701
702 ret = clk_prepare_enable(res->pipe_clk);
703 if (ret) {
704 dev_err(dev, "cannot prepare/enable pipe clock\n");
705 return ret;
706 }
707
708 return 0;
709 }
710
qcom_pcie_get_resources_2_4_0(struct qcom_pcie * pcie)711 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
712 {
713 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
714 struct dw_pcie *pci = pcie->pci;
715 struct device *dev = pci->dev;
716 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
717 int ret;
718
719 res->clks[0].id = "aux";
720 res->clks[1].id = "master_bus";
721 res->clks[2].id = "slave_bus";
722 res->clks[3].id = "iface";
723
724 /* qcom,pcie-ipq4019 is defined without "iface" */
725 res->num_clks = is_ipq ? 3 : 4;
726
727 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
728 if (ret < 0)
729 return ret;
730
731 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
732 if (IS_ERR(res->axi_m_reset))
733 return PTR_ERR(res->axi_m_reset);
734
735 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
736 if (IS_ERR(res->axi_s_reset))
737 return PTR_ERR(res->axi_s_reset);
738
739 if (is_ipq) {
740 /*
741 * These resources relates to the PHY or are secure clocks, but
742 * are controlled here for IPQ4019
743 */
744 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
745 if (IS_ERR(res->pipe_reset))
746 return PTR_ERR(res->pipe_reset);
747
748 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
749 "axi_m_vmid");
750 if (IS_ERR(res->axi_m_vmid_reset))
751 return PTR_ERR(res->axi_m_vmid_reset);
752
753 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
754 "axi_s_xpu");
755 if (IS_ERR(res->axi_s_xpu_reset))
756 return PTR_ERR(res->axi_s_xpu_reset);
757
758 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
759 if (IS_ERR(res->parf_reset))
760 return PTR_ERR(res->parf_reset);
761
762 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
763 if (IS_ERR(res->phy_reset))
764 return PTR_ERR(res->phy_reset);
765 }
766
767 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
768 "axi_m_sticky");
769 if (IS_ERR(res->axi_m_sticky_reset))
770 return PTR_ERR(res->axi_m_sticky_reset);
771
772 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
773 "pipe_sticky");
774 if (IS_ERR(res->pipe_sticky_reset))
775 return PTR_ERR(res->pipe_sticky_reset);
776
777 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
778 if (IS_ERR(res->pwr_reset))
779 return PTR_ERR(res->pwr_reset);
780
781 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
782 if (IS_ERR(res->ahb_reset))
783 return PTR_ERR(res->ahb_reset);
784
785 if (is_ipq) {
786 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
787 if (IS_ERR(res->phy_ahb_reset))
788 return PTR_ERR(res->phy_ahb_reset);
789 }
790
791 return 0;
792 }
793
qcom_pcie_deinit_2_4_0(struct qcom_pcie * pcie)794 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
795 {
796 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
797
798 reset_control_assert(res->axi_m_reset);
799 reset_control_assert(res->axi_s_reset);
800 reset_control_assert(res->pipe_reset);
801 reset_control_assert(res->pipe_sticky_reset);
802 reset_control_assert(res->phy_reset);
803 reset_control_assert(res->phy_ahb_reset);
804 reset_control_assert(res->axi_m_sticky_reset);
805 reset_control_assert(res->pwr_reset);
806 reset_control_assert(res->ahb_reset);
807 clk_bulk_disable_unprepare(res->num_clks, res->clks);
808 }
809
qcom_pcie_init_2_4_0(struct qcom_pcie * pcie)810 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
811 {
812 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
813 struct dw_pcie *pci = pcie->pci;
814 struct device *dev = pci->dev;
815 u32 val;
816 int ret;
817
818 ret = reset_control_assert(res->axi_m_reset);
819 if (ret) {
820 dev_err(dev, "cannot assert axi master reset\n");
821 return ret;
822 }
823
824 ret = reset_control_assert(res->axi_s_reset);
825 if (ret) {
826 dev_err(dev, "cannot assert axi slave reset\n");
827 return ret;
828 }
829
830 usleep_range(10000, 12000);
831
832 ret = reset_control_assert(res->pipe_reset);
833 if (ret) {
834 dev_err(dev, "cannot assert pipe reset\n");
835 return ret;
836 }
837
838 ret = reset_control_assert(res->pipe_sticky_reset);
839 if (ret) {
840 dev_err(dev, "cannot assert pipe sticky reset\n");
841 return ret;
842 }
843
844 ret = reset_control_assert(res->phy_reset);
845 if (ret) {
846 dev_err(dev, "cannot assert phy reset\n");
847 return ret;
848 }
849
850 ret = reset_control_assert(res->phy_ahb_reset);
851 if (ret) {
852 dev_err(dev, "cannot assert phy ahb reset\n");
853 return ret;
854 }
855
856 usleep_range(10000, 12000);
857
858 ret = reset_control_assert(res->axi_m_sticky_reset);
859 if (ret) {
860 dev_err(dev, "cannot assert axi master sticky reset\n");
861 return ret;
862 }
863
864 ret = reset_control_assert(res->pwr_reset);
865 if (ret) {
866 dev_err(dev, "cannot assert power reset\n");
867 return ret;
868 }
869
870 ret = reset_control_assert(res->ahb_reset);
871 if (ret) {
872 dev_err(dev, "cannot assert ahb reset\n");
873 return ret;
874 }
875
876 usleep_range(10000, 12000);
877
878 ret = reset_control_deassert(res->phy_ahb_reset);
879 if (ret) {
880 dev_err(dev, "cannot deassert phy ahb reset\n");
881 return ret;
882 }
883
884 ret = reset_control_deassert(res->phy_reset);
885 if (ret) {
886 dev_err(dev, "cannot deassert phy reset\n");
887 goto err_rst_phy;
888 }
889
890 ret = reset_control_deassert(res->pipe_reset);
891 if (ret) {
892 dev_err(dev, "cannot deassert pipe reset\n");
893 goto err_rst_pipe;
894 }
895
896 ret = reset_control_deassert(res->pipe_sticky_reset);
897 if (ret) {
898 dev_err(dev, "cannot deassert pipe sticky reset\n");
899 goto err_rst_pipe_sticky;
900 }
901
902 usleep_range(10000, 12000);
903
904 ret = reset_control_deassert(res->axi_m_reset);
905 if (ret) {
906 dev_err(dev, "cannot deassert axi master reset\n");
907 goto err_rst_axi_m;
908 }
909
910 ret = reset_control_deassert(res->axi_m_sticky_reset);
911 if (ret) {
912 dev_err(dev, "cannot deassert axi master sticky reset\n");
913 goto err_rst_axi_m_sticky;
914 }
915
916 ret = reset_control_deassert(res->axi_s_reset);
917 if (ret) {
918 dev_err(dev, "cannot deassert axi slave reset\n");
919 goto err_rst_axi_s;
920 }
921
922 ret = reset_control_deassert(res->pwr_reset);
923 if (ret) {
924 dev_err(dev, "cannot deassert power reset\n");
925 goto err_rst_pwr;
926 }
927
928 ret = reset_control_deassert(res->ahb_reset);
929 if (ret) {
930 dev_err(dev, "cannot deassert ahb reset\n");
931 goto err_rst_ahb;
932 }
933
934 usleep_range(10000, 12000);
935
936 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
937 if (ret)
938 goto err_clks;
939
940 /* enable PCIe clocks and resets */
941 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
942 val &= ~BIT(0);
943 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
944
945 /* change DBI base address */
946 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
947
948 /* MAC PHY_POWERDOWN MUX DISABLE */
949 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
950 val &= ~BIT(29);
951 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
952
953 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
954 val |= BIT(4);
955 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
956
957 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
958 val |= BIT(31);
959 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
960
961 return 0;
962
963 err_clks:
964 reset_control_assert(res->ahb_reset);
965 err_rst_ahb:
966 reset_control_assert(res->pwr_reset);
967 err_rst_pwr:
968 reset_control_assert(res->axi_s_reset);
969 err_rst_axi_s:
970 reset_control_assert(res->axi_m_sticky_reset);
971 err_rst_axi_m_sticky:
972 reset_control_assert(res->axi_m_reset);
973 err_rst_axi_m:
974 reset_control_assert(res->pipe_sticky_reset);
975 err_rst_pipe_sticky:
976 reset_control_assert(res->pipe_reset);
977 err_rst_pipe:
978 reset_control_assert(res->phy_reset);
979 err_rst_phy:
980 reset_control_assert(res->phy_ahb_reset);
981 return ret;
982 }
983
qcom_pcie_get_resources_2_3_3(struct qcom_pcie * pcie)984 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
985 {
986 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
987 struct dw_pcie *pci = pcie->pci;
988 struct device *dev = pci->dev;
989 int i;
990 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
991 "axi_m_sticky", "sticky",
992 "ahb", "sleep", };
993
994 res->iface = devm_clk_get(dev, "iface");
995 if (IS_ERR(res->iface))
996 return PTR_ERR(res->iface);
997
998 res->axi_m_clk = devm_clk_get(dev, "axi_m");
999 if (IS_ERR(res->axi_m_clk))
1000 return PTR_ERR(res->axi_m_clk);
1001
1002 res->axi_s_clk = devm_clk_get(dev, "axi_s");
1003 if (IS_ERR(res->axi_s_clk))
1004 return PTR_ERR(res->axi_s_clk);
1005
1006 res->ahb_clk = devm_clk_get(dev, "ahb");
1007 if (IS_ERR(res->ahb_clk))
1008 return PTR_ERR(res->ahb_clk);
1009
1010 res->aux_clk = devm_clk_get(dev, "aux");
1011 if (IS_ERR(res->aux_clk))
1012 return PTR_ERR(res->aux_clk);
1013
1014 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
1015 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
1016 if (IS_ERR(res->rst[i]))
1017 return PTR_ERR(res->rst[i]);
1018 }
1019
1020 return 0;
1021 }
1022
qcom_pcie_deinit_2_3_3(struct qcom_pcie * pcie)1023 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1024 {
1025 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1026
1027 clk_disable_unprepare(res->iface);
1028 clk_disable_unprepare(res->axi_m_clk);
1029 clk_disable_unprepare(res->axi_s_clk);
1030 clk_disable_unprepare(res->ahb_clk);
1031 clk_disable_unprepare(res->aux_clk);
1032 }
1033
qcom_pcie_init_2_3_3(struct qcom_pcie * pcie)1034 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1035 {
1036 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1037 struct dw_pcie *pci = pcie->pci;
1038 struct device *dev = pci->dev;
1039 int i, ret;
1040
1041 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1042 ret = reset_control_assert(res->rst[i]);
1043 if (ret) {
1044 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1045 return ret;
1046 }
1047 }
1048
1049 usleep_range(2000, 2500);
1050
1051 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1052 ret = reset_control_deassert(res->rst[i]);
1053 if (ret) {
1054 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1055 ret);
1056 return ret;
1057 }
1058 }
1059
1060 /*
1061 * Don't have a way to see if the reset has completed.
1062 * Wait for some time.
1063 */
1064 usleep_range(2000, 2500);
1065
1066 ret = clk_prepare_enable(res->iface);
1067 if (ret) {
1068 dev_err(dev, "cannot prepare/enable core clock\n");
1069 goto err_clk_iface;
1070 }
1071
1072 ret = clk_prepare_enable(res->axi_m_clk);
1073 if (ret) {
1074 dev_err(dev, "cannot prepare/enable core clock\n");
1075 goto err_clk_axi_m;
1076 }
1077
1078 ret = clk_prepare_enable(res->axi_s_clk);
1079 if (ret) {
1080 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1081 goto err_clk_axi_s;
1082 }
1083
1084 ret = clk_prepare_enable(res->ahb_clk);
1085 if (ret) {
1086 dev_err(dev, "cannot prepare/enable ahb clock\n");
1087 goto err_clk_ahb;
1088 }
1089
1090 ret = clk_prepare_enable(res->aux_clk);
1091 if (ret) {
1092 dev_err(dev, "cannot prepare/enable aux clock\n");
1093 goto err_clk_aux;
1094 }
1095
1096 return 0;
1097
1098 err_clk_aux:
1099 clk_disable_unprepare(res->ahb_clk);
1100 err_clk_ahb:
1101 clk_disable_unprepare(res->axi_s_clk);
1102 err_clk_axi_s:
1103 clk_disable_unprepare(res->axi_m_clk);
1104 err_clk_axi_m:
1105 clk_disable_unprepare(res->iface);
1106 err_clk_iface:
1107 /*
1108 * Not checking for failure, will anyway return
1109 * the original failure in 'ret'.
1110 */
1111 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1112 reset_control_assert(res->rst[i]);
1113
1114 return ret;
1115 }
1116
qcom_pcie_post_init_2_3_3(struct qcom_pcie * pcie)1117 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
1118 {
1119 struct dw_pcie *pci = pcie->pci;
1120 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1121 u32 val;
1122
1123 writel(SLV_ADDR_SPACE_SZ,
1124 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1125
1126 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1127 val &= ~BIT(0);
1128 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1129
1130 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1131
1132 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1133 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1134 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1135 pcie->parf + PCIE20_PARF_SYS_CTRL);
1136 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1137
1138 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1139 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1140 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1141
1142 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1143 val &= ~PCI_EXP_LNKCAP_ASPMS;
1144 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1145
1146 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1147 PCI_EXP_DEVCTL2);
1148
1149 return 0;
1150 }
1151
qcom_pcie_get_resources_2_7_0(struct qcom_pcie * pcie)1152 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1153 {
1154 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1155 struct dw_pcie *pci = pcie->pci;
1156 struct device *dev = pci->dev;
1157 unsigned int idx;
1158 int ret;
1159
1160 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1161 if (IS_ERR(res->pci_reset))
1162 return PTR_ERR(res->pci_reset);
1163
1164 res->supplies[0].supply = "vdda";
1165 res->supplies[1].supply = "vddpe-3v3";
1166 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1167 res->supplies);
1168 if (ret)
1169 return ret;
1170
1171 idx = 0;
1172 res->clks[idx++].id = "aux";
1173 res->clks[idx++].id = "cfg";
1174 res->clks[idx++].id = "bus_master";
1175 res->clks[idx++].id = "bus_slave";
1176 res->clks[idx++].id = "slave_q2a";
1177 if (pcie->cfg->has_tbu_clk)
1178 res->clks[idx++].id = "tbu";
1179 if (pcie->cfg->has_ddrss_sf_tbu_clk)
1180 res->clks[idx++].id = "ddrss_sf_tbu";
1181 if (pcie->cfg->has_aggre0_clk)
1182 res->clks[idx++].id = "aggre0";
1183 if (pcie->cfg->has_aggre1_clk)
1184 res->clks[idx++].id = "aggre1";
1185
1186 res->num_clks = idx;
1187
1188 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
1189 if (ret < 0)
1190 return ret;
1191
1192 if (pcie->cfg->pipe_clk_need_muxing) {
1193 res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
1194 if (IS_ERR(res->pipe_clk_src))
1195 return PTR_ERR(res->pipe_clk_src);
1196
1197 res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
1198 if (IS_ERR(res->phy_pipe_clk))
1199 return PTR_ERR(res->phy_pipe_clk);
1200
1201 res->ref_clk_src = devm_clk_get(dev, "ref");
1202 if (IS_ERR(res->ref_clk_src))
1203 return PTR_ERR(res->ref_clk_src);
1204 }
1205
1206 res->pipe_clk = devm_clk_get(dev, "pipe");
1207 return PTR_ERR_OR_ZERO(res->pipe_clk);
1208 }
1209
qcom_pcie_init_2_7_0(struct qcom_pcie * pcie)1210 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1211 {
1212 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1213 struct dw_pcie *pci = pcie->pci;
1214 struct device *dev = pci->dev;
1215 u32 val;
1216 int ret;
1217
1218 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1219 if (ret < 0) {
1220 dev_err(dev, "cannot enable regulators\n");
1221 return ret;
1222 }
1223
1224 /* Set TCXO as clock source for pcie_pipe_clk_src */
1225 if (pcie->cfg->pipe_clk_need_muxing)
1226 clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
1227
1228 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
1229 if (ret < 0)
1230 goto err_disable_regulators;
1231
1232 ret = reset_control_assert(res->pci_reset);
1233 if (ret < 0) {
1234 dev_err(dev, "cannot deassert pci reset\n");
1235 goto err_disable_clocks;
1236 }
1237
1238 usleep_range(1000, 1500);
1239
1240 ret = reset_control_deassert(res->pci_reset);
1241 if (ret < 0) {
1242 dev_err(dev, "cannot deassert pci reset\n");
1243 goto err_disable_clocks;
1244 }
1245
1246 /* Wait for reset to complete, required on SM8450 */
1247 usleep_range(1000, 1500);
1248
1249 /* configure PCIe to RC mode */
1250 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1251
1252 /* enable PCIe clocks and resets */
1253 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1254 val &= ~BIT(0);
1255 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1256
1257 /* change DBI base address */
1258 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1259
1260 /* MAC PHY_POWERDOWN MUX DISABLE */
1261 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1262 val &= ~BIT(29);
1263 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1264
1265 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1266 val |= BIT(4);
1267 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1268
1269 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1270 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1271 val |= BIT(31);
1272 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1273 }
1274
1275 return 0;
1276 err_disable_clocks:
1277 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1278 err_disable_regulators:
1279 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1280
1281 return ret;
1282 }
1283
qcom_pcie_deinit_2_7_0(struct qcom_pcie * pcie)1284 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1285 {
1286 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1287
1288 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1289 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1290 }
1291
qcom_pcie_post_init_2_7_0(struct qcom_pcie * pcie)1292 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1293 {
1294 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1295
1296 /* Set pipe clock as clock source for pcie_pipe_clk_src */
1297 if (pcie->cfg->pipe_clk_need_muxing)
1298 clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
1299
1300 return clk_prepare_enable(res->pipe_clk);
1301 }
1302
qcom_pcie_post_deinit_2_7_0(struct qcom_pcie * pcie)1303 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1304 {
1305 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1306
1307 clk_disable_unprepare(res->pipe_clk);
1308 }
1309
qcom_pcie_link_up(struct dw_pcie * pci)1310 static int qcom_pcie_link_up(struct dw_pcie *pci)
1311 {
1312 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1313 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1314
1315 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1316 }
1317
qcom_pcie_config_sid_sm8250(struct qcom_pcie * pcie)1318 static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
1319 {
1320 /* iommu map structure */
1321 struct {
1322 u32 bdf;
1323 u32 phandle;
1324 u32 smmu_sid;
1325 u32 smmu_sid_len;
1326 } *map;
1327 void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;
1328 struct device *dev = pcie->pci->dev;
1329 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1330 int i, nr_map, size = 0;
1331 u32 smmu_sid_base;
1332
1333 of_get_property(dev->of_node, "iommu-map", &size);
1334 if (!size)
1335 return 0;
1336
1337 map = kzalloc(size, GFP_KERNEL);
1338 if (!map)
1339 return -ENOMEM;
1340
1341 of_property_read_u32_array(dev->of_node,
1342 "iommu-map", (u32 *)map, size / sizeof(u32));
1343
1344 nr_map = size / (sizeof(*map));
1345
1346 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1347
1348 /* Registers need to be zero out first */
1349 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1350
1351 /* Extract the SMMU SID base from the first entry of iommu-map */
1352 smmu_sid_base = map[0].smmu_sid;
1353
1354 /* Look for an available entry to hold the mapping */
1355 for (i = 0; i < nr_map; i++) {
1356 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1357 u32 val;
1358 u8 hash;
1359
1360 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be),
1361 0);
1362
1363 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1364
1365 /* If the register is already populated, look for next available entry */
1366 while (val) {
1367 u8 current_hash = hash++;
1368 u8 next_mask = 0xff;
1369
1370 /* If NEXT field is NULL then update it with next hash */
1371 if (!(val & next_mask)) {
1372 val |= (u32)hash;
1373 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1374 }
1375
1376 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1377 }
1378
1379 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1380 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1381 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1382 }
1383
1384 kfree(map);
1385
1386 return 0;
1387 }
1388
qcom_pcie_host_init(struct pcie_port * pp)1389 static int qcom_pcie_host_init(struct pcie_port *pp)
1390 {
1391 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1392 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1393 int ret;
1394
1395 qcom_ep_reset_assert(pcie);
1396
1397 ret = pcie->cfg->ops->init(pcie);
1398 if (ret)
1399 return ret;
1400
1401 ret = phy_power_on(pcie->phy);
1402 if (ret)
1403 goto err_deinit;
1404
1405 if (pcie->cfg->ops->post_init) {
1406 ret = pcie->cfg->ops->post_init(pcie);
1407 if (ret)
1408 goto err_disable_phy;
1409 }
1410
1411 qcom_ep_reset_deassert(pcie);
1412
1413 if (pcie->cfg->ops->config_sid) {
1414 ret = pcie->cfg->ops->config_sid(pcie);
1415 if (ret)
1416 goto err;
1417 }
1418
1419 return 0;
1420
1421 err:
1422 qcom_ep_reset_assert(pcie);
1423 if (pcie->cfg->ops->post_deinit)
1424 pcie->cfg->ops->post_deinit(pcie);
1425 err_disable_phy:
1426 phy_power_off(pcie->phy);
1427 err_deinit:
1428 pcie->cfg->ops->deinit(pcie);
1429
1430 return ret;
1431 }
1432
1433 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1434 .host_init = qcom_pcie_host_init,
1435 };
1436
1437 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1438 static const struct qcom_pcie_ops ops_2_1_0 = {
1439 .get_resources = qcom_pcie_get_resources_2_1_0,
1440 .init = qcom_pcie_init_2_1_0,
1441 .deinit = qcom_pcie_deinit_2_1_0,
1442 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1443 };
1444
1445 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1446 static const struct qcom_pcie_ops ops_1_0_0 = {
1447 .get_resources = qcom_pcie_get_resources_1_0_0,
1448 .init = qcom_pcie_init_1_0_0,
1449 .deinit = qcom_pcie_deinit_1_0_0,
1450 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1451 };
1452
1453 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1454 static const struct qcom_pcie_ops ops_2_3_2 = {
1455 .get_resources = qcom_pcie_get_resources_2_3_2,
1456 .init = qcom_pcie_init_2_3_2,
1457 .post_init = qcom_pcie_post_init_2_3_2,
1458 .deinit = qcom_pcie_deinit_2_3_2,
1459 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1460 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1461 };
1462
1463 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1464 static const struct qcom_pcie_ops ops_2_4_0 = {
1465 .get_resources = qcom_pcie_get_resources_2_4_0,
1466 .init = qcom_pcie_init_2_4_0,
1467 .deinit = qcom_pcie_deinit_2_4_0,
1468 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1469 };
1470
1471 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1472 static const struct qcom_pcie_ops ops_2_3_3 = {
1473 .get_resources = qcom_pcie_get_resources_2_3_3,
1474 .init = qcom_pcie_init_2_3_3,
1475 .post_init = qcom_pcie_post_init_2_3_3,
1476 .deinit = qcom_pcie_deinit_2_3_3,
1477 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1478 };
1479
1480 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1481 static const struct qcom_pcie_ops ops_2_7_0 = {
1482 .get_resources = qcom_pcie_get_resources_2_7_0,
1483 .init = qcom_pcie_init_2_7_0,
1484 .deinit = qcom_pcie_deinit_2_7_0,
1485 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1486 .post_init = qcom_pcie_post_init_2_7_0,
1487 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1488 };
1489
1490 /* Qcom IP rev.: 1.9.0 */
1491 static const struct qcom_pcie_ops ops_1_9_0 = {
1492 .get_resources = qcom_pcie_get_resources_2_7_0,
1493 .init = qcom_pcie_init_2_7_0,
1494 .deinit = qcom_pcie_deinit_2_7_0,
1495 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1496 .post_init = qcom_pcie_post_init_2_7_0,
1497 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1498 .config_sid = qcom_pcie_config_sid_sm8250,
1499 };
1500
1501 static const struct qcom_pcie_cfg apq8084_cfg = {
1502 .ops = &ops_1_0_0,
1503 };
1504
1505 static const struct qcom_pcie_cfg ipq8064_cfg = {
1506 .ops = &ops_2_1_0,
1507 };
1508
1509 static const struct qcom_pcie_cfg msm8996_cfg = {
1510 .ops = &ops_2_3_2,
1511 };
1512
1513 static const struct qcom_pcie_cfg ipq8074_cfg = {
1514 .ops = &ops_2_3_3,
1515 };
1516
1517 static const struct qcom_pcie_cfg ipq4019_cfg = {
1518 .ops = &ops_2_4_0,
1519 };
1520
1521 static const struct qcom_pcie_cfg sdm845_cfg = {
1522 .ops = &ops_2_7_0,
1523 .has_tbu_clk = true,
1524 };
1525
1526 static const struct qcom_pcie_cfg sm8150_cfg = {
1527 /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as
1528 * 1.9.0, so reuse the same.
1529 */
1530 .ops = &ops_1_9_0,
1531 };
1532
1533 static const struct qcom_pcie_cfg sm8250_cfg = {
1534 .ops = &ops_1_9_0,
1535 .has_tbu_clk = true,
1536 .has_ddrss_sf_tbu_clk = true,
1537 };
1538
1539 static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
1540 .ops = &ops_1_9_0,
1541 .has_ddrss_sf_tbu_clk = true,
1542 .pipe_clk_need_muxing = true,
1543 .has_aggre0_clk = true,
1544 .has_aggre1_clk = true,
1545 };
1546
1547 static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
1548 .ops = &ops_1_9_0,
1549 .has_ddrss_sf_tbu_clk = true,
1550 .pipe_clk_need_muxing = true,
1551 .has_aggre1_clk = true,
1552 };
1553
1554 static const struct qcom_pcie_cfg sc7280_cfg = {
1555 .ops = &ops_1_9_0,
1556 .has_tbu_clk = true,
1557 .pipe_clk_need_muxing = true,
1558 };
1559
1560 static const struct qcom_pcie_cfg sc8180x_cfg = {
1561 .ops = &ops_1_9_0,
1562 .has_tbu_clk = true,
1563 };
1564
1565 static const struct dw_pcie_ops dw_pcie_ops = {
1566 .link_up = qcom_pcie_link_up,
1567 .start_link = qcom_pcie_start_link,
1568 };
1569
qcom_pcie_probe(struct platform_device * pdev)1570 static int qcom_pcie_probe(struct platform_device *pdev)
1571 {
1572 struct device *dev = &pdev->dev;
1573 struct pcie_port *pp;
1574 struct dw_pcie *pci;
1575 struct qcom_pcie *pcie;
1576 const struct qcom_pcie_cfg *pcie_cfg;
1577 int ret;
1578
1579 pcie_cfg = of_device_get_match_data(dev);
1580 if (!pcie_cfg || !pcie_cfg->ops) {
1581 dev_err(dev, "Invalid platform data\n");
1582 return -EINVAL;
1583 }
1584
1585 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1586 if (!pcie)
1587 return -ENOMEM;
1588
1589 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1590 if (!pci)
1591 return -ENOMEM;
1592
1593 pm_runtime_enable(dev);
1594 ret = pm_runtime_get_sync(dev);
1595 if (ret < 0)
1596 goto err_pm_runtime_put;
1597
1598 pci->dev = dev;
1599 pci->ops = &dw_pcie_ops;
1600 pp = &pci->pp;
1601
1602 pcie->pci = pci;
1603
1604 pcie->cfg = pcie_cfg;
1605
1606 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1607 if (IS_ERR(pcie->reset)) {
1608 ret = PTR_ERR(pcie->reset);
1609 goto err_pm_runtime_put;
1610 }
1611
1612 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1613 if (IS_ERR(pcie->parf)) {
1614 ret = PTR_ERR(pcie->parf);
1615 goto err_pm_runtime_put;
1616 }
1617
1618 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1619 if (IS_ERR(pcie->elbi)) {
1620 ret = PTR_ERR(pcie->elbi);
1621 goto err_pm_runtime_put;
1622 }
1623
1624 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1625 if (IS_ERR(pcie->phy)) {
1626 ret = PTR_ERR(pcie->phy);
1627 goto err_pm_runtime_put;
1628 }
1629
1630 ret = pcie->cfg->ops->get_resources(pcie);
1631 if (ret)
1632 goto err_pm_runtime_put;
1633
1634 pp->ops = &qcom_pcie_dw_ops;
1635
1636 ret = phy_init(pcie->phy);
1637 if (ret)
1638 goto err_pm_runtime_put;
1639
1640 platform_set_drvdata(pdev, pcie);
1641
1642 ret = dw_pcie_host_init(pp);
1643 if (ret) {
1644 dev_err(dev, "cannot initialize host\n");
1645 goto err_phy_exit;
1646 }
1647
1648 return 0;
1649
1650 err_phy_exit:
1651 phy_exit(pcie->phy);
1652 err_pm_runtime_put:
1653 pm_runtime_put(dev);
1654 pm_runtime_disable(dev);
1655
1656 return ret;
1657 }
1658
1659 static const struct of_device_id qcom_pcie_match[] = {
1660 { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
1661 { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
1662 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
1663 { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
1664 { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
1665 { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
1666 { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
1667 { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
1668 { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
1669 { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
1670 { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
1671 { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg },
1672 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
1673 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
1674 { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
1675 { }
1676 };
1677
qcom_fixup_class(struct pci_dev * dev)1678 static void qcom_fixup_class(struct pci_dev *dev)
1679 {
1680 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1681 }
1682 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1683 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1684 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1685 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1686 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1687 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1688 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1689
1690 static struct platform_driver qcom_pcie_driver = {
1691 .probe = qcom_pcie_probe,
1692 .driver = {
1693 .name = "qcom-pcie",
1694 .suppress_bind_attrs = true,
1695 .of_match_table = qcom_pcie_match,
1696 },
1697 };
1698 builtin_platform_driver(qcom_pcie_driver);
1699