1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_table.h"
13 #include "txrx.h"
14
15 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
16 {128, 1896, grp_0}, /* ACH 0 */
17 {128, 1896, grp_0}, /* ACH 1 */
18 {128, 1896, grp_0}, /* ACH 2 */
19 {128, 1896, grp_0}, /* ACH 3 */
20 {128, 1896, grp_1}, /* ACH 4 */
21 {128, 1896, grp_1}, /* ACH 5 */
22 {128, 1896, grp_1}, /* ACH 6 */
23 {128, 1896, grp_1}, /* ACH 7 */
24 {32, 1896, grp_0}, /* B0MGQ */
25 {128, 1896, grp_0}, /* B0HIQ */
26 {32, 1896, grp_1}, /* B1MGQ */
27 {128, 1896, grp_1}, /* B1HIQ */
28 {40, 0, 0} /* FWCMDQ */
29 };
30
31 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
32 1896, /* Group 0 */
33 1896, /* Group 1 */
34 3792, /* Public Max */
35 0 /* WP threshold */
36 };
37
38 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
39 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
40 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
41 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
42 RTW89_HCIFC_POH},
43 [RTW89_QTA_INVALID] = {NULL},
44 };
45
46 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
47 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
48 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
49 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
50 &rtw89_mac_size.ple_qt5},
51 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
52 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
53 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
54 &rtw89_mac_size.ple_qt13},
55 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
56 NULL},
57 };
58
59 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
60 {0x44AC, 0x00000000},
61 {0x44B0, 0x00000000},
62 {0x44B4, 0x00000000},
63 {0x44B8, 0x00000000},
64 {0x44BC, 0x00000000},
65 {0x44C0, 0x00000000},
66 {0x44C4, 0x00000000},
67 {0x44C8, 0x00000000},
68 {0x44CC, 0x00000000},
69 {0x44D0, 0x00000000},
70 {0x44D4, 0x00000000},
71 {0x44D8, 0x00000000},
72 {0x44DC, 0x00000000},
73 {0x44E0, 0x00000000},
74 {0x44E4, 0x00000000},
75 {0x44E8, 0x00000000},
76 {0x44EC, 0x00000000},
77 {0x44F0, 0x00000000},
78 {0x44F4, 0x00000000},
79 {0x44F8, 0x00000000},
80 {0x44FC, 0x00000000},
81 {0x4500, 0x00000000},
82 {0x4504, 0x00000000},
83 {0x4508, 0x00000000},
84 {0x450C, 0x00000000},
85 {0x4510, 0x00000000},
86 {0x4514, 0x00000000},
87 {0x4518, 0x00000000},
88 {0x451C, 0x00000000},
89 {0x4520, 0x00000000},
90 {0x4524, 0x00000000},
91 {0x4528, 0x00000000},
92 {0x452C, 0x00000000},
93 {0x4530, 0x4E1F3E81},
94 {0x4534, 0x00000000},
95 {0x4538, 0x0000005A},
96 {0x453C, 0x00000000},
97 {0x4540, 0x00000000},
98 {0x4544, 0x00000000},
99 {0x4548, 0x00000000},
100 {0x454C, 0x00000000},
101 {0x4550, 0x00000000},
102 {0x4554, 0x00000000},
103 {0x4558, 0x00000000},
104 {0x455C, 0x00000000},
105 {0x4560, 0x4060001A},
106 {0x4564, 0x40000000},
107 {0x4568, 0x00000000},
108 {0x456C, 0x00000000},
109 {0x4570, 0x04000007},
110 {0x4574, 0x0000DC87},
111 {0x4578, 0x00000BAB},
112 {0x457C, 0x03E00000},
113 {0x4580, 0x00000048},
114 {0x4584, 0x00000000},
115 {0x4588, 0x000003E8},
116 {0x458C, 0x30000000},
117 {0x4590, 0x00000000},
118 {0x4594, 0x10000000},
119 {0x4598, 0x00000001},
120 {0x459C, 0x00030000},
121 {0x45A0, 0x01000000},
122 {0x45A4, 0x03000200},
123 {0x45A8, 0xC00001C0},
124 {0x45AC, 0x78018000},
125 {0x45B0, 0x80000000},
126 {0x45B4, 0x01C80600},
127 {0x45B8, 0x00000002},
128 {0x4594, 0x10000000}
129 };
130
131 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
132 {0x4624, GENMASK(20, 14), 0x40},
133 {0x46f8, GENMASK(20, 14), 0x40},
134 {0x4674, GENMASK(20, 19), 0x2},
135 {0x4748, GENMASK(20, 19), 0x2},
136 {0x4650, GENMASK(14, 10), 0x18},
137 {0x4724, GENMASK(14, 10), 0x18},
138 {0x4688, GENMASK(1, 0), 0x3},
139 {0x475c, GENMASK(1, 0), 0x3},
140 };
141
142 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
143
144 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
145 {0x4624, GENMASK(20, 14), 0x1a},
146 {0x46f8, GENMASK(20, 14), 0x1a},
147 {0x4674, GENMASK(20, 19), 0x1},
148 {0x4748, GENMASK(20, 19), 0x1},
149 {0x4650, GENMASK(14, 10), 0x12},
150 {0x4724, GENMASK(14, 10), 0x12},
151 {0x4688, GENMASK(1, 0), 0x0},
152 {0x475c, GENMASK(1, 0), 0x0},
153 };
154
155 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
156
157 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
158 {0x00C6,
159 PWR_CV_MSK_B,
160 PWR_INTF_MSK_PCIE,
161 PWR_BASE_MAC,
162 PWR_CMD_WRITE, BIT(6), BIT(6)},
163 {0x1086,
164 PWR_CV_MSK_ALL,
165 PWR_INTF_MSK_SDIO,
166 PWR_BASE_MAC,
167 PWR_CMD_WRITE, BIT(0), 0},
168 {0x1086,
169 PWR_CV_MSK_ALL,
170 PWR_INTF_MSK_SDIO,
171 PWR_BASE_MAC,
172 PWR_CMD_POLL, BIT(1), BIT(1)},
173 {0x0005,
174 PWR_CV_MSK_ALL,
175 PWR_INTF_MSK_ALL,
176 PWR_BASE_MAC,
177 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
178 {0x0005,
179 PWR_CV_MSK_ALL,
180 PWR_INTF_MSK_ALL,
181 PWR_BASE_MAC,
182 PWR_CMD_WRITE, BIT(7), 0},
183 {0x0005,
184 PWR_CV_MSK_ALL,
185 PWR_INTF_MSK_ALL,
186 PWR_BASE_MAC,
187 PWR_CMD_WRITE, BIT(2), 0},
188 {0x0006,
189 PWR_CV_MSK_ALL,
190 PWR_INTF_MSK_ALL,
191 PWR_BASE_MAC,
192 PWR_CMD_POLL, BIT(1), BIT(1)},
193 {0x0006,
194 PWR_CV_MSK_ALL,
195 PWR_INTF_MSK_ALL,
196 PWR_BASE_MAC,
197 PWR_CMD_WRITE, BIT(0), BIT(0)},
198 {0x0005,
199 PWR_CV_MSK_ALL,
200 PWR_INTF_MSK_ALL,
201 PWR_BASE_MAC,
202 PWR_CMD_WRITE, BIT(0), BIT(0)},
203 {0x0005,
204 PWR_CV_MSK_ALL,
205 PWR_INTF_MSK_ALL,
206 PWR_BASE_MAC,
207 PWR_CMD_POLL, BIT(0), 0},
208 {0x106D,
209 PWR_CV_MSK_B | PWR_CV_MSK_C,
210 PWR_INTF_MSK_USB,
211 PWR_BASE_MAC,
212 PWR_CMD_WRITE, BIT(6), 0},
213 {0x0088,
214 PWR_CV_MSK_ALL,
215 PWR_INTF_MSK_ALL,
216 PWR_BASE_MAC,
217 PWR_CMD_WRITE, BIT(0), BIT(0)},
218 {0x0088,
219 PWR_CV_MSK_ALL,
220 PWR_INTF_MSK_ALL,
221 PWR_BASE_MAC,
222 PWR_CMD_WRITE, BIT(0), 0},
223 {0x0088,
224 PWR_CV_MSK_ALL,
225 PWR_INTF_MSK_ALL,
226 PWR_BASE_MAC,
227 PWR_CMD_WRITE, BIT(0), BIT(0)},
228 {0x0088,
229 PWR_CV_MSK_ALL,
230 PWR_INTF_MSK_ALL,
231 PWR_BASE_MAC,
232 PWR_CMD_WRITE, BIT(0), 0},
233 {0x0088,
234 PWR_CV_MSK_ALL,
235 PWR_INTF_MSK_ALL,
236 PWR_BASE_MAC,
237 PWR_CMD_WRITE, BIT(0), BIT(0)},
238 {0x0083,
239 PWR_CV_MSK_ALL,
240 PWR_INTF_MSK_ALL,
241 PWR_BASE_MAC,
242 PWR_CMD_WRITE, BIT(6), 0},
243 {0x0080,
244 PWR_CV_MSK_ALL,
245 PWR_INTF_MSK_ALL,
246 PWR_BASE_MAC,
247 PWR_CMD_WRITE, BIT(5), BIT(5)},
248 {0x0024,
249 PWR_CV_MSK_ALL,
250 PWR_INTF_MSK_ALL,
251 PWR_BASE_MAC,
252 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
253 {0x02A0,
254 PWR_CV_MSK_ALL,
255 PWR_INTF_MSK_ALL,
256 PWR_BASE_MAC,
257 PWR_CMD_WRITE, BIT(1), BIT(1)},
258 {0x02A2,
259 PWR_CV_MSK_ALL,
260 PWR_INTF_MSK_ALL,
261 PWR_BASE_MAC,
262 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
263 {0x0071,
264 PWR_CV_MSK_ALL,
265 PWR_INTF_MSK_PCIE,
266 PWR_BASE_MAC,
267 PWR_CMD_WRITE, BIT(4), 0},
268 {0x0010,
269 PWR_CV_MSK_A,
270 PWR_INTF_MSK_PCIE,
271 PWR_BASE_MAC,
272 PWR_CMD_WRITE, BIT(2), BIT(2)},
273 {0x02A0,
274 PWR_CV_MSK_A,
275 PWR_INTF_MSK_ALL,
276 PWR_BASE_MAC,
277 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
278 {0xFFFF,
279 PWR_CV_MSK_ALL,
280 PWR_INTF_MSK_ALL,
281 0,
282 PWR_CMD_END, 0, 0},
283 };
284
285 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
286 {0x02F0,
287 PWR_CV_MSK_ALL,
288 PWR_INTF_MSK_ALL,
289 PWR_BASE_MAC,
290 PWR_CMD_WRITE, 0xFF, 0},
291 {0x02F1,
292 PWR_CV_MSK_ALL,
293 PWR_INTF_MSK_ALL,
294 PWR_BASE_MAC,
295 PWR_CMD_WRITE, 0xFF, 0},
296 {0x0006,
297 PWR_CV_MSK_ALL,
298 PWR_INTF_MSK_ALL,
299 PWR_BASE_MAC,
300 PWR_CMD_WRITE, BIT(0), BIT(0)},
301 {0x0002,
302 PWR_CV_MSK_ALL,
303 PWR_INTF_MSK_ALL,
304 PWR_BASE_MAC,
305 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
306 {0x0082,
307 PWR_CV_MSK_ALL,
308 PWR_INTF_MSK_ALL,
309 PWR_BASE_MAC,
310 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
311 {0x106D,
312 PWR_CV_MSK_B | PWR_CV_MSK_C,
313 PWR_INTF_MSK_USB,
314 PWR_BASE_MAC,
315 PWR_CMD_WRITE, BIT(6), BIT(6)},
316 {0x0005,
317 PWR_CV_MSK_ALL,
318 PWR_INTF_MSK_ALL,
319 PWR_BASE_MAC,
320 PWR_CMD_WRITE, BIT(1), BIT(1)},
321 {0x0005,
322 PWR_CV_MSK_ALL,
323 PWR_INTF_MSK_ALL,
324 PWR_BASE_MAC,
325 PWR_CMD_POLL, BIT(1), 0},
326 {0x0091,
327 PWR_CV_MSK_ALL,
328 PWR_INTF_MSK_PCIE,
329 PWR_BASE_MAC,
330 PWR_CMD_WRITE, BIT(0), 0},
331 {0x0005,
332 PWR_CV_MSK_ALL,
333 PWR_INTF_MSK_PCIE,
334 PWR_BASE_MAC,
335 PWR_CMD_WRITE, BIT(2), BIT(2)},
336 {0x0007,
337 PWR_CV_MSK_ALL,
338 PWR_INTF_MSK_USB,
339 PWR_BASE_MAC,
340 PWR_CMD_WRITE, BIT(4), 0},
341 {0x0007,
342 PWR_CV_MSK_ALL,
343 PWR_INTF_MSK_SDIO,
344 PWR_BASE_MAC,
345 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
346 {0x0005,
347 PWR_CV_MSK_ALL,
348 PWR_INTF_MSK_SDIO,
349 PWR_BASE_MAC,
350 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
351 {0x0005,
352 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
353 PWR_CV_MSK_G,
354 PWR_INTF_MSK_USB,
355 PWR_BASE_MAC,
356 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
357 {0x1086,
358 PWR_CV_MSK_ALL,
359 PWR_INTF_MSK_SDIO,
360 PWR_BASE_MAC,
361 PWR_CMD_WRITE, BIT(0), BIT(0)},
362 {0x1086,
363 PWR_CV_MSK_ALL,
364 PWR_INTF_MSK_SDIO,
365 PWR_BASE_MAC,
366 PWR_CMD_POLL, BIT(1), 0},
367 {0xFFFF,
368 PWR_CV_MSK_ALL,
369 PWR_INTF_MSK_ALL,
370 0,
371 PWR_CMD_END, 0, 0},
372 };
373
374 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
375 rtw8852a_pwron, NULL
376 };
377
378 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
379 rtw8852a_pwroff, NULL
380 };
381
382 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
383 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
384 R_AX_H2CREG_DATA3
385 };
386
387 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
388 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
389 R_AX_C2HREG_DATA3
390 };
391
392 static const struct rtw89_page_regs rtw8852a_page_regs = {
393 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
394 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
395 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
396 .ach_page_info = R_AX_ACH0_PAGE_INFO,
397 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
398 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
399 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
400 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
401 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
402 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
403 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
404 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
405 };
406
407 static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
408 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
409 };
410
411 static const struct rtw89_imr_info rtw8852a_imr_info = {
412 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
413 .wsec_imr_reg = R_AX_SEC_DEBUG,
414 .wsec_imr_set = B_AX_IMR_ERROR,
415 .mpdu_tx_imr_set = 0,
416 .mpdu_rx_imr_set = 0,
417 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
418 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
419 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
420 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
421 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
422 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
423 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
424 .wde_imr_clr = B_AX_WDE_IMR_CLR,
425 .wde_imr_set = B_AX_WDE_IMR_SET,
426 .ple_imr_clr = B_AX_PLE_IMR_CLR,
427 .ple_imr_set = B_AX_PLE_IMR_SET,
428 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
429 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
430 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
431 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
432 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
433 .other_disp_imr_set = 0,
434 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
435 .bbrpt_err_imr_set = 0,
436 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
437 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
438 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
439 .cdma_imr_0_reg = R_AX_DLE_CTRL,
440 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
441 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
442 .cdma_imr_1_reg = 0,
443 .cdma_imr_1_clr = 0,
444 .cdma_imr_1_set = 0,
445 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
446 .phy_intf_imr_clr = 0,
447 .phy_intf_imr_set = 0,
448 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
449 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
450 .rmac_imr_set = B_AX_RMAC_IMR_SET,
451 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
452 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
453 .tmac_imr_set = B_AX_TMAC_IMR_SET,
454 };
455
rtw8852ae_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8852a_efuse * map)456 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
457 struct rtw8852a_efuse *map)
458 {
459 ether_addr_copy(efuse->addr, map->e.mac_addr);
460 efuse->rfe_type = map->rfe_type;
461 efuse->xtal_cap = map->xtal_k;
462 }
463
rtw8852a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852a_efuse * map)464 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
465 struct rtw8852a_efuse *map)
466 {
467 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
468 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
469 u8 i, j;
470
471 tssi->thermal[RF_PATH_A] = map->path_a_therm;
472 tssi->thermal[RF_PATH_B] = map->path_b_therm;
473
474 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
475 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
476 sizeof(ofst[i]->cck_tssi));
477
478 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
479 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
480 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
481 i, j, tssi->tssi_cck[i][j]);
482
483 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
484 sizeof(ofst[i]->bw40_tssi));
485 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
486 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
487
488 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
489 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
490 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
491 i, j, tssi->tssi_mcs[i][j]);
492 }
493 }
494
rtw8852a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map)495 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
496 {
497 struct rtw89_efuse *efuse = &rtwdev->efuse;
498 struct rtw8852a_efuse *map;
499
500 map = (struct rtw8852a_efuse *)log_map;
501
502 efuse->country_code[0] = map->country_code[0];
503 efuse->country_code[1] = map->country_code[1];
504 rtw8852a_efuse_parsing_tssi(rtwdev, map);
505
506 switch (rtwdev->hci.type) {
507 case RTW89_HCI_TYPE_PCIE:
508 rtw8852ae_efuse_parsing(efuse, map);
509 break;
510 default:
511 return -ENOTSUPP;
512 }
513
514 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
515
516 return 0;
517 }
518
rtw8852a_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)519 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
520 {
521 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
522 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
523 u32 addr = rtwdev->chip->phycap_addr;
524 bool pg = false;
525 u32 ofst;
526 u8 i, j;
527
528 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
529 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
530 /* addrs are in decreasing order */
531 ofst = tssi_trim_addr[i] - addr - j;
532 tssi->tssi_trim[i][j] = phycap_map[ofst];
533
534 if (phycap_map[ofst] != 0xff)
535 pg = true;
536 }
537 }
538
539 if (!pg) {
540 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
541 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
542 "[TSSI][TRIM] no PG, set all trim info to 0\n");
543 }
544
545 for (i = 0; i < RF_PATH_NUM_8852A; i++)
546 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
547 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
548 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
549 i, j, tssi->tssi_trim[i][j],
550 tssi_trim_addr[i] - j);
551 }
552
rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)553 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
554 u8 *phycap_map)
555 {
556 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
557 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
558 u32 addr = rtwdev->chip->phycap_addr;
559 u8 i;
560
561 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
562 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
563
564 rtw89_debug(rtwdev, RTW89_DBG_RFK,
565 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
566 i, info->thermal_trim[i]);
567
568 if (info->thermal_trim[i] != 0xff)
569 info->pg_thermal_trim = true;
570 }
571 }
572
rtw8852a_thermal_trim(struct rtw89_dev * rtwdev)573 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
574 {
575 #define __thm_setting(raw) \
576 ({ \
577 u8 __v = (raw); \
578 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
579 })
580 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
581 u8 i, val;
582
583 if (!info->pg_thermal_trim) {
584 rtw89_debug(rtwdev, RTW89_DBG_RFK,
585 "[THERMAL][TRIM] no PG, do nothing\n");
586
587 return;
588 }
589
590 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
591 val = __thm_setting(info->thermal_trim[i]);
592 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
593
594 rtw89_debug(rtwdev, RTW89_DBG_RFK,
595 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
596 i, val);
597 }
598 #undef __thm_setting
599 }
600
rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)601 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
602 u8 *phycap_map)
603 {
604 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
605 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
606 u32 addr = rtwdev->chip->phycap_addr;
607 u8 i;
608
609 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
610 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
611
612 rtw89_debug(rtwdev, RTW89_DBG_RFK,
613 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
614 i, info->pa_bias_trim[i]);
615
616 if (info->pa_bias_trim[i] != 0xff)
617 info->pg_pa_bias_trim = true;
618 }
619 }
620
rtw8852a_pa_bias_trim(struct rtw89_dev * rtwdev)621 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
622 {
623 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
624 u8 pabias_2g, pabias_5g;
625 u8 i;
626
627 if (!info->pg_pa_bias_trim) {
628 rtw89_debug(rtwdev, RTW89_DBG_RFK,
629 "[PA_BIAS][TRIM] no PG, do nothing\n");
630
631 return;
632 }
633
634 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
635 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
636 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
637
638 rtw89_debug(rtwdev, RTW89_DBG_RFK,
639 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
640 i, pabias_2g, pabias_5g);
641
642 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
643 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
644 }
645 }
646
rtw8852a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)647 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
648 {
649 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
650 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
651 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
652
653 return 0;
654 }
655
rtw8852a_power_trim(struct rtw89_dev * rtwdev)656 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
657 {
658 rtw8852a_thermal_trim(rtwdev);
659 rtw8852a_pa_bias_trim(rtwdev);
660 }
661
rtw8852a_set_channel_mac(struct rtw89_dev * rtwdev,struct rtw89_channel_params * param,u8 mac_idx)662 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
663 struct rtw89_channel_params *param,
664 u8 mac_idx)
665 {
666 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
667 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE,
668 mac_idx);
669 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
670 u8 txsc20 = 0, txsc40 = 0;
671
672 switch (param->bandwidth) {
673 case RTW89_CHANNEL_WIDTH_80:
674 txsc40 = rtw89_phy_get_txsc(rtwdev, param,
675 RTW89_CHANNEL_WIDTH_40);
676 fallthrough;
677 case RTW89_CHANNEL_WIDTH_40:
678 txsc20 = rtw89_phy_get_txsc(rtwdev, param,
679 RTW89_CHANNEL_WIDTH_20);
680 break;
681 default:
682 break;
683 }
684
685 switch (param->bandwidth) {
686 case RTW89_CHANNEL_WIDTH_80:
687 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
688 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
689 break;
690 case RTW89_CHANNEL_WIDTH_40:
691 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
692 rtw89_write32(rtwdev, sub_carr, txsc20);
693 break;
694 case RTW89_CHANNEL_WIDTH_20:
695 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
696 rtw89_write32(rtwdev, sub_carr, 0);
697 break;
698 default:
699 break;
700 }
701
702 if (param->center_chan > 14)
703 rtw89_write8_set(rtwdev, chk_rate,
704 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
705 else
706 rtw89_write8_clr(rtwdev, chk_rate,
707 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
708 }
709
710 static const u32 rtw8852a_sco_barker_threshold[14] = {
711 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
712 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
713 };
714
715 static const u32 rtw8852a_sco_cck_threshold[14] = {
716 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
717 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
718 };
719
rtw8852a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 central_ch,u8 primary_ch,enum rtw89_bandwidth bw)720 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
721 u8 primary_ch, enum rtw89_bandwidth bw)
722 {
723 u8 ch_element;
724
725 if (bw == RTW89_CHANNEL_WIDTH_20) {
726 ch_element = central_ch - 1;
727 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
728 if (primary_ch == 1)
729 ch_element = central_ch - 1 + 2;
730 else
731 ch_element = central_ch - 1 - 2;
732 } else {
733 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
734 return -EINVAL;
735 }
736 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
737 rtw8852a_sco_barker_threshold[ch_element]);
738 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
739 rtw8852a_sco_cck_threshold[ch_element]);
740
741 return 0;
742 }
743
rtw8852a_ch_setting(struct rtw89_dev * rtwdev,u8 central_ch,u8 path)744 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
745 u8 path)
746 {
747 u32 val;
748
749 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
750 if (val == INV_RF_DATA) {
751 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
752 return;
753 }
754 val &= ~0x303ff;
755 val |= central_ch;
756 if (central_ch > 14)
757 val |= (BIT(16) | BIT(8));
758 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
759 }
760
rtw8852a_sco_mapping(u8 central_ch)761 static u8 rtw8852a_sco_mapping(u8 central_ch)
762 {
763 if (central_ch == 1)
764 return 109;
765 else if (central_ch >= 2 && central_ch <= 6)
766 return 108;
767 else if (central_ch >= 7 && central_ch <= 10)
768 return 107;
769 else if (central_ch >= 11 && central_ch <= 14)
770 return 106;
771 else if (central_ch == 36 || central_ch == 38)
772 return 51;
773 else if (central_ch >= 40 && central_ch <= 58)
774 return 50;
775 else if (central_ch >= 60 && central_ch <= 64)
776 return 49;
777 else if (central_ch == 100 || central_ch == 102)
778 return 48;
779 else if (central_ch >= 104 && central_ch <= 126)
780 return 47;
781 else if (central_ch >= 128 && central_ch <= 151)
782 return 46;
783 else if (central_ch >= 153 && central_ch <= 177)
784 return 45;
785 else
786 return 0;
787 }
788
rtw8852a_ctrl_ch(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)789 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
790 enum rtw89_phy_idx phy_idx)
791 {
792 u8 sco_comp;
793 bool is_2g = central_ch <= 14;
794
795 if (phy_idx == RTW89_PHY_0) {
796 /* Path A */
797 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
798 if (is_2g)
799 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
800 B_PATH0_TIA_ERR_G1_SEL, 1,
801 phy_idx);
802 else
803 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
804 B_PATH0_TIA_ERR_G1_SEL, 0,
805 phy_idx);
806
807 /* Path B */
808 if (!rtwdev->dbcc_en) {
809 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
810 if (is_2g)
811 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
812 B_P1_MODE_SEL,
813 1, phy_idx);
814 else
815 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
816 B_P1_MODE_SEL,
817 0, phy_idx);
818 } else {
819 if (is_2g)
820 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
821 B_2P4G_BAND_SEL);
822 else
823 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
824 B_2P4G_BAND_SEL);
825 }
826 /* SCO compensate FC setting */
827 sco_comp = rtw8852a_sco_mapping(central_ch);
828 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
829 sco_comp, phy_idx);
830 } else {
831 /* Path B */
832 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
833 if (is_2g)
834 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
835 B_P1_MODE_SEL,
836 1, phy_idx);
837 else
838 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
839 B_P1_MODE_SEL,
840 0, phy_idx);
841 /* SCO compensate FC setting */
842 sco_comp = rtw8852a_sco_mapping(central_ch);
843 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
844 sco_comp, phy_idx);
845 }
846
847 /* Band edge */
848 if (is_2g)
849 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
850 phy_idx);
851 else
852 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
853 phy_idx);
854
855 /* CCK parameters */
856 if (central_ch == 14) {
857 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
858 0x3b13ff);
859 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
860 0x1c42de);
861 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
862 0xfdb0ad);
863 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
864 0xf60f6e);
865 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
866 0xfd8f92);
867 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
868 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
869 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
870 0xfff00a);
871 } else {
872 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
873 0x3d23ff);
874 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
875 0x29b354);
876 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
877 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
878 0xfdb053);
879 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
880 0xf86f9a);
881 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
882 0xfaef92);
883 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
884 0xfe5fcc);
885 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
886 0xffdff5);
887 }
888 }
889
rtw8852a_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)890 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
891 {
892 u32 val = 0;
893 u32 adc_sel[2] = {0x12d0, 0x32d0};
894 u32 wbadc_sel[2] = {0x12ec, 0x32ec};
895
896 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
897 if (val == INV_RF_DATA) {
898 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
899 return;
900 }
901 val &= ~(BIT(11) | BIT(10));
902 switch (bw) {
903 case RTW89_CHANNEL_WIDTH_5:
904 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
905 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
906 val |= (BIT(11) | BIT(10));
907 break;
908 case RTW89_CHANNEL_WIDTH_10:
909 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
910 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
911 val |= (BIT(11) | BIT(10));
912 break;
913 case RTW89_CHANNEL_WIDTH_20:
914 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
915 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
916 val |= (BIT(11) | BIT(10));
917 break;
918 case RTW89_CHANNEL_WIDTH_40:
919 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
920 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
921 val |= BIT(11);
922 break;
923 case RTW89_CHANNEL_WIDTH_80:
924 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
925 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
926 val |= BIT(10);
927 break;
928 default:
929 rtw89_warn(rtwdev, "Fail to set ADC\n");
930 }
931
932 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
933 }
934
935 static void
rtw8852a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)936 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
937 enum rtw89_phy_idx phy_idx)
938 {
939 /* Switch bandwidth */
940 switch (bw) {
941 case RTW89_CHANNEL_WIDTH_5:
942 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
943 phy_idx);
944 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
945 phy_idx);
946 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
947 0x0, phy_idx);
948 break;
949 case RTW89_CHANNEL_WIDTH_10:
950 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
951 phy_idx);
952 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
953 phy_idx);
954 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
955 0x0, phy_idx);
956 break;
957 case RTW89_CHANNEL_WIDTH_20:
958 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
959 phy_idx);
960 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
961 phy_idx);
962 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
963 0x0, phy_idx);
964 break;
965 case RTW89_CHANNEL_WIDTH_40:
966 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
967 phy_idx);
968 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
969 phy_idx);
970 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
971 pri_ch,
972 phy_idx);
973 if (pri_ch == RTW89_SC_20_UPPER)
974 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
975 else
976 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
977 break;
978 case RTW89_CHANNEL_WIDTH_80:
979 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
980 phy_idx);
981 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
982 phy_idx);
983 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
984 pri_ch,
985 phy_idx);
986 break;
987 default:
988 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
989 pri_ch);
990 }
991
992 if (phy_idx == RTW89_PHY_0) {
993 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
994 if (!rtwdev->dbcc_en)
995 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
996 } else {
997 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
998 }
999 }
1000
rtw8852a_spur_elimination(struct rtw89_dev * rtwdev,u8 central_ch)1001 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1002 {
1003 if (central_ch == 153) {
1004 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1005 0x210);
1006 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1007 0x210);
1008 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0);
1009 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1010 B_P0_NBIIDX_NOTCH_EN, 0x1);
1011 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1012 B_P1_NBIIDX_NOTCH_EN, 0x1);
1013 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1014 0x1);
1015 } else if (central_ch == 151) {
1016 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1017 0x210);
1018 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1019 0x210);
1020 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40);
1021 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1022 B_P0_NBIIDX_NOTCH_EN, 0x1);
1023 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1024 B_P1_NBIIDX_NOTCH_EN, 0x1);
1025 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1026 0x1);
1027 } else if (central_ch == 155) {
1028 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1029 0x2d0);
1030 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1031 0x2d0);
1032 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740);
1033 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1034 B_P0_NBIIDX_NOTCH_EN, 0x1);
1035 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1036 B_P1_NBIIDX_NOTCH_EN, 0x1);
1037 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1038 0x1);
1039 } else {
1040 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1041 B_P0_NBIIDX_NOTCH_EN, 0x0);
1042 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1043 B_P1_NBIIDX_NOTCH_EN, 0x0);
1044 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1045 0x0);
1046 }
1047 }
1048
rtw8852a_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1049 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1050 enum rtw89_phy_idx phy_idx)
1051 {
1052 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1053 phy_idx);
1054 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1055 phy_idx);
1056 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1057 phy_idx);
1058 }
1059
rtw8852a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool en)1060 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1061 enum rtw89_phy_idx phy_idx, bool en)
1062 {
1063 if (en)
1064 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1065 1,
1066 phy_idx);
1067 else
1068 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1069 0,
1070 phy_idx);
1071 }
1072
rtw8852a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1073 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1074 enum rtw89_phy_idx phy_idx)
1075 {
1076 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1077 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1078 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1079 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1080 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1081 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1082 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1083 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1084 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1085 }
1086
rtw8852a_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1087 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1088 enum rtw89_phy_idx phy_idx)
1089 {
1090 u32 addr;
1091
1092 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1093 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1094 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1095 }
1096
rtw8852a_bb_sethw(struct rtw89_dev * rtwdev)1097 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1098 {
1099 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1100 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1101
1102 if (rtwdev->hal.cv <= CHIP_CCV) {
1103 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1104 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1105 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F);
1106 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1107 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1108 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1109 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1110 }
1111 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1112 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1113 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1114 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1115 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1116 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1117
1118 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1119 }
1120
rtw8852a_bbrst_for_rfk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1121 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1122 enum rtw89_phy_idx phy_idx)
1123 {
1124 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1125 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1126 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1127 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1128 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1129 udelay(1);
1130 }
1131
rtw8852a_set_channel_bb(struct rtw89_dev * rtwdev,struct rtw89_channel_params * param,enum rtw89_phy_idx phy_idx)1132 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1133 struct rtw89_channel_params *param,
1134 enum rtw89_phy_idx phy_idx)
1135 {
1136 bool cck_en = param->center_chan <= 14;
1137 u8 pri_ch_idx = param->pri_ch_idx;
1138
1139 if (cck_en)
1140 rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan,
1141 param->primary_chan, param->bandwidth);
1142
1143 rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx);
1144 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx);
1145 if (cck_en) {
1146 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1147 } else {
1148 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1149 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1150 }
1151 rtw8852a_spur_elimination(rtwdev, param->center_chan);
1152 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1153 param->primary_chan);
1154 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1155 }
1156
rtw8852a_set_channel(struct rtw89_dev * rtwdev,struct rtw89_channel_params * params)1157 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1158 struct rtw89_channel_params *params)
1159 {
1160 rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0);
1161 rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0);
1162 }
1163
rtw8852a_dfs_en(struct rtw89_dev * rtwdev,bool en)1164 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1165 {
1166 if (en)
1167 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1168 else
1169 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1170 }
1171
rtw8852a_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1172 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1173 enum rtw89_rf_path path)
1174 {
1175 static const u32 tssi_trk[2] = {0x5818, 0x7818};
1176 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1177
1178 if (en) {
1179 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1180 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1181 } else {
1182 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1183 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1184 }
1185 }
1186
rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1187 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1188 u8 phy_idx)
1189 {
1190 if (!rtwdev->dbcc_en) {
1191 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1192 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1193 } else {
1194 if (phy_idx == RTW89_PHY_0)
1195 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1196 else
1197 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1198 }
1199 }
1200
rtw8852a_adc_en(struct rtw89_dev * rtwdev,bool en)1201 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1202 {
1203 if (en)
1204 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1205 0x0);
1206 else
1207 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1208 0xf);
1209 }
1210
rtw8852a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p)1211 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1212 struct rtw89_channel_help_params *p)
1213 {
1214 u8 phy_idx = RTW89_PHY_0;
1215
1216 if (enter) {
1217 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1218 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1219 rtw8852a_dfs_en(rtwdev, false);
1220 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1221 rtw8852a_adc_en(rtwdev, false);
1222 fsleep(40);
1223 rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1224 } else {
1225 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1226 rtw8852a_adc_en(rtwdev, true);
1227 rtw8852a_dfs_en(rtwdev, true);
1228 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1229 rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1230 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1231 }
1232 }
1233
rtw8852a_fem_setup(struct rtw89_dev * rtwdev)1234 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1235 {
1236 struct rtw89_efuse *efuse = &rtwdev->efuse;
1237
1238 switch (efuse->rfe_type) {
1239 case 11:
1240 case 12:
1241 case 17:
1242 case 18:
1243 case 51:
1244 case 53:
1245 rtwdev->fem.epa_2g = true;
1246 rtwdev->fem.elna_2g = true;
1247 fallthrough;
1248 case 9:
1249 case 10:
1250 case 15:
1251 case 16:
1252 rtwdev->fem.epa_5g = true;
1253 rtwdev->fem.elna_5g = true;
1254 break;
1255 default:
1256 break;
1257 }
1258 }
1259
rtw8852a_rfk_init(struct rtw89_dev * rtwdev)1260 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1261 {
1262 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1263 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1264
1265 rtw8852a_rck(rtwdev);
1266 rtw8852a_dack(rtwdev);
1267 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
1268 }
1269
rtw8852a_rfk_channel(struct rtw89_dev * rtwdev)1270 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
1271 {
1272 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1273
1274 rtw8852a_rx_dck(rtwdev, phy_idx, true);
1275 rtw8852a_iqk(rtwdev, phy_idx);
1276 rtw8852a_tssi(rtwdev, phy_idx);
1277 rtw8852a_dpk(rtwdev, phy_idx);
1278 }
1279
rtw8852a_rfk_band_changed(struct rtw89_dev * rtwdev)1280 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev)
1281 {
1282 rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0);
1283 }
1284
rtw8852a_rfk_scan(struct rtw89_dev * rtwdev,bool start)1285 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1286 {
1287 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1288 }
1289
rtw8852a_rfk_track(struct rtw89_dev * rtwdev)1290 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1291 {
1292 rtw8852a_dpk_track(rtwdev);
1293 rtw8852a_iqk_track(rtwdev);
1294 rtw8852a_tssi_track(rtwdev);
1295 }
1296
rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1297 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1298 enum rtw89_phy_idx phy_idx, s16 ref)
1299 {
1300 s8 ofst_int = 0;
1301 u8 base_cw_0db = 0x27;
1302 u16 tssi_16dbm_cw = 0x12c;
1303 s16 pwr_s10_3 = 0;
1304 s16 rf_pwr_cw = 0;
1305 u16 bb_pwr_cw = 0;
1306 u32 pwr_cw = 0;
1307 u32 tssi_ofst_cw = 0;
1308
1309 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1310 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1311 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1312 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1313 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1314
1315 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1316 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1317 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1318 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1319
1320 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1321 }
1322
1323 static
rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1324 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1325 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1326 {
1327 s8 val_1t = 0;
1328 s8 val_2t = 0;
1329 u32 reg;
1330
1331 if (pw_ofst < -16 || pw_ofst > 15) {
1332 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1333 pw_ofst);
1334 return;
1335 }
1336 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
1337 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1338 val_1t = pw_ofst;
1339 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1340 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1341 val_2t = max(val_1t - 3, -16);
1342 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1343 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1344 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1345 val_1t, val_2t);
1346 }
1347
rtw8852a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1348 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1349 enum rtw89_phy_idx phy_idx)
1350 {
1351 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1352 const u32 mask = 0x7FFFFFF;
1353 const u8 ofst_ofdm = 0x4;
1354 const u8 ofst_cck = 0x8;
1355 s16 ref_ofdm = 0;
1356 s16 ref_cck = 0;
1357 u32 val;
1358 u8 i;
1359
1360 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1361
1362 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1363 GENMASK(27, 10), 0x0);
1364
1365 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1366 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1367
1368 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1369 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1370 phy_idx);
1371
1372 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1373 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1374
1375 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1376 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1377 phy_idx);
1378 }
1379
rtw8852a_set_txpwr_byrate(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1380 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev,
1381 enum rtw89_phy_idx phy_idx)
1382 {
1383 u8 ch = rtwdev->hal.current_channel;
1384 static const u8 rs[] = {
1385 RTW89_RS_CCK,
1386 RTW89_RS_OFDM,
1387 RTW89_RS_MCS,
1388 RTW89_RS_HEDCM,
1389 };
1390 s8 tmp;
1391 u8 i, j;
1392 u32 val, shf, addr = R_AX_PWR_BY_RATE;
1393 struct rtw89_rate_desc cur;
1394
1395 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1396 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
1397
1398 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
1399 for (i = 0; i < ARRAY_SIZE(rs); i++) {
1400 if (cur.nss >= rtw89_rs_nss_max[rs[i]])
1401 continue;
1402
1403 val = 0;
1404 cur.rs = rs[i];
1405
1406 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
1407 cur.idx = j;
1408 shf = (j % 4) * 8;
1409 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur);
1410 val |= (tmp << shf);
1411
1412 if ((j + 1) % 4)
1413 continue;
1414
1415 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1416 val = 0;
1417 addr += 4;
1418 }
1419 }
1420 }
1421 }
1422
rtw8852a_set_txpwr_offset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1423 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev,
1424 enum rtw89_phy_idx phy_idx)
1425 {
1426 struct rtw89_rate_desc desc = {
1427 .nss = RTW89_NSS_1,
1428 .rs = RTW89_RS_OFFSET,
1429 };
1430 u32 val = 0;
1431 s8 v;
1432
1433 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
1434
1435 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
1436 v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc);
1437 val |= ((v & 0xf) << (4 * desc.idx));
1438 }
1439
1440 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
1441 GENMASK(19, 0), val);
1442 }
1443
rtw8852a_set_txpwr_limit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1444 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev,
1445 enum rtw89_phy_idx phy_idx)
1446 {
1447 #define __MAC_TXPWR_LMT_PAGE_SIZE 40
1448 u8 ch = rtwdev->hal.current_channel;
1449 u8 bw = rtwdev->hal.current_band_width;
1450 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A];
1451 u32 addr, val;
1452 const s8 *ptr;
1453 u8 i, j, k;
1454
1455 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1456 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
1457
1458 for (i = 0; i < NTX_NUM_8852A; i++) {
1459 rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i);
1460
1461 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
1462 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
1463 ptr = (s8 *)&lmt[i] + j;
1464 val = 0;
1465
1466 for (k = 0; k < 4; k++)
1467 val |= (ptr[k] << (8 * k));
1468
1469 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1470 }
1471 }
1472 #undef __MAC_TXPWR_LMT_PAGE_SIZE
1473 }
1474
rtw8852a_set_txpwr_limit_ru(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1475 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1476 enum rtw89_phy_idx phy_idx)
1477 {
1478 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
1479 u8 ch = rtwdev->hal.current_channel;
1480 u8 bw = rtwdev->hal.current_band_width;
1481 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A];
1482 u32 addr, val;
1483 const s8 *ptr;
1484 u8 i, j, k;
1485
1486 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1487 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
1488
1489 for (i = 0; i < NTX_NUM_8852A; i++) {
1490 rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i);
1491
1492 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
1493 addr = R_AX_PWR_RU_LMT + j +
1494 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
1495 ptr = (s8 *)&lmt_ru[i] + j;
1496 val = 0;
1497
1498 for (k = 0; k < 4; k++)
1499 val |= (ptr[k] << (8 * k));
1500
1501 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1502 }
1503 }
1504
1505 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
1506 }
1507
rtw8852a_set_txpwr(struct rtw89_dev * rtwdev)1508 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev)
1509 {
1510 rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0);
1511 rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0);
1512 rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0);
1513 }
1514
rtw8852a_set_txpwr_ctrl(struct rtw89_dev * rtwdev)1515 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
1516 {
1517 rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0);
1518 rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0);
1519 }
1520
1521 static int
rtw8852a_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1522 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1523 {
1524 int ret;
1525
1526 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1527 if (ret)
1528 return ret;
1529
1530 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1531 if (ret)
1532 return ret;
1533
1534 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1535 if (ret)
1536 return ret;
1537
1538 return 0;
1539 }
1540
rtw8852a_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1541 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1542 {
1543 u8 i = 0;
1544 u32 addr, val;
1545
1546 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1547 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1548 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1549 rtw89_phy_write32(rtwdev, addr, val);
1550 }
1551 }
1552
rtw8852a_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1553 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1554 struct rtw8852a_bb_pmac_info *tx_info,
1555 enum rtw89_phy_idx idx)
1556 {
1557 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1558 if (tx_info->mode == CONT_TX)
1559 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1560 idx);
1561 else if (tx_info->mode == PKTS_TX)
1562 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1563 idx);
1564 }
1565
rtw8852a_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1566 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1567 struct rtw8852a_bb_pmac_info *tx_info,
1568 enum rtw89_phy_idx idx)
1569 {
1570 enum rtw8852a_pmac_mode mode = tx_info->mode;
1571 u32 pkt_cnt = tx_info->tx_cnt;
1572 u16 period = tx_info->period;
1573
1574 if (mode == CONT_TX && !tx_info->is_cck) {
1575 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1576 idx);
1577 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1578 } else if (mode == PKTS_TX) {
1579 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1580 idx);
1581 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1582 B_PMAC_TX_PRD_MSK, period, idx);
1583 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1584 pkt_cnt, idx);
1585 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1586 }
1587 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1588 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1589 }
1590
rtw8852a_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1591 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1592 struct rtw8852a_bb_pmac_info *tx_info,
1593 enum rtw89_phy_idx idx)
1594 {
1595 if (!tx_info->en_pmac_tx) {
1596 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1597 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1598 if (rtwdev->hal.current_band_type == RTW89_BAND_2G)
1599 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1600 return;
1601 }
1602 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1603 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1604 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1605 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1606 idx);
1607 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1608 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1609 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1610 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1611 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1612 }
1613
rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx)1614 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1615 u16 tx_cnt, u16 period, u16 tx_time,
1616 enum rtw89_phy_idx idx)
1617 {
1618 struct rtw8852a_bb_pmac_info tx_info = {0};
1619
1620 tx_info.en_pmac_tx = enable;
1621 tx_info.is_cck = 0;
1622 tx_info.mode = PKTS_TX;
1623 tx_info.tx_cnt = tx_cnt;
1624 tx_info.period = period;
1625 tx_info.tx_time = tx_time;
1626 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1627 }
1628
rtw8852a_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1629 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1630 enum rtw89_phy_idx idx)
1631 {
1632 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1633 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1634 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1635 }
1636
rtw8852a_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1637 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1638 {
1639 u32 rst_mask0 = 0;
1640 u32 rst_mask1 = 0;
1641
1642 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1643 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1644 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1645 if (!rtwdev->dbcc_en) {
1646 if (tx_path == RF_PATH_A) {
1647 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1648 B_TXPATH_SEL_MSK, 1);
1649 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1650 B_TXNSS_MAP_MSK, 0);
1651 } else if (tx_path == RF_PATH_B) {
1652 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1653 B_TXPATH_SEL_MSK, 2);
1654 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1655 B_TXNSS_MAP_MSK, 0);
1656 } else if (tx_path == RF_PATH_AB) {
1657 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1658 B_TXPATH_SEL_MSK, 3);
1659 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1660 B_TXNSS_MAP_MSK, 4);
1661 } else {
1662 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1663 }
1664 } else {
1665 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1666 1);
1667 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1668 RTW89_PHY_1);
1669 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1670 0);
1671 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1672 RTW89_PHY_1);
1673 }
1674 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1675 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1676 if (tx_path == RF_PATH_A) {
1677 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1678 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1679 } else {
1680 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1681 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1682 }
1683 }
1684
rtw8852a_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1685 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1686 enum rtw89_phy_idx idx, u8 mode)
1687 {
1688 if (mode != 0)
1689 return;
1690 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1691 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1692 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1693 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1694 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1695 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1696 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1697 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1698 }
1699
rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)1700 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1701 {
1702 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl :
1703 &rtw8852a_btc_preagc_dis_defs_tbl);
1704 }
1705
rtw8852a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1706 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1707 {
1708 if (rtwdev->is_tssi_mode[rf_path]) {
1709 u32 addr = 0x1c10 + (rf_path << 13);
1710
1711 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1712 }
1713
1714 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1715 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1716 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1717
1718 fsleep(200);
1719
1720 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1721 }
1722
rtw8852a_btc_set_rfe(struct rtw89_dev * rtwdev)1723 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1724 {
1725 struct rtw89_btc *btc = &rtwdev->btc;
1726 struct rtw89_btc_module *module = &btc->mdinfo;
1727
1728 module->rfe_type = rtwdev->efuse.rfe_type;
1729 module->cv = rtwdev->hal.cv;
1730 module->bt_solo = 0;
1731 module->switch_type = BTC_SWITCH_INTERNAL;
1732
1733 if (module->rfe_type > 0)
1734 module->ant.num = (module->rfe_type % 2 ? 2 : 3);
1735 else
1736 module->ant.num = 2;
1737
1738 module->ant.diversity = 0;
1739 module->ant.isolation = 10;
1740
1741 if (module->ant.num == 3) {
1742 module->ant.type = BTC_ANT_DEDICATED;
1743 module->bt_pos = BTC_BT_ALONE;
1744 } else {
1745 module->ant.type = BTC_ANT_SHARED;
1746 module->bt_pos = BTC_BT_BTG;
1747 }
1748 }
1749
1750 static
rtw8852a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1751 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1752 {
1753 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1754 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1755 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1756 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1757 }
1758
rtw8852a_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)1759 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1760 {
1761 if (btg) {
1762 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1763 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1764 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1765 } else {
1766 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1767 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1768 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1769 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1770 }
1771 }
1772
rtw8852a_btc_init_cfg(struct rtw89_dev * rtwdev)1773 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1774 {
1775 struct rtw89_btc *btc = &rtwdev->btc;
1776 struct rtw89_btc_module *module = &btc->mdinfo;
1777 const struct rtw89_chip_info *chip = rtwdev->chip;
1778 const struct rtw89_mac_ax_coex coex_params = {
1779 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1780 .direction = RTW89_MAC_AX_COEX_INNER,
1781 };
1782
1783 /* PTA init */
1784 rtw89_mac_coex_init(rtwdev, &coex_params);
1785
1786 /* set WL Tx response = Hi-Pri */
1787 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1788 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1789
1790 /* set rf gnt debug off */
1791 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1792 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1793
1794 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1795 if (module->ant.type == BTC_ANT_SHARED) {
1796 rtw8852a_set_trx_mask(rtwdev,
1797 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1798 rtw8852a_set_trx_mask(rtwdev,
1799 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1800 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1801 rtw8852a_set_trx_mask(rtwdev,
1802 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1803 rtw8852a_set_trx_mask(rtwdev,
1804 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1805 }
1806
1807 /* set PTA break table */
1808 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1809
1810 /* enable BT counter 0xda40[16,2] = 2b'11 */
1811 rtw89_write32_set(rtwdev,
1812 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1813 btc->cx.wl.status.map.init_ok = true;
1814 }
1815
1816 static
rtw8852a_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1817 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1818 {
1819 u32 bitmap = 0;
1820 u32 reg = 0;
1821
1822 switch (map) {
1823 case BTC_PRI_MASK_TX_RESP:
1824 reg = R_BTC_BT_COEX_MSK_TABLE;
1825 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1826 break;
1827 case BTC_PRI_MASK_BEACON:
1828 reg = R_AX_WL_PRI_MSK;
1829 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1830 break;
1831 default:
1832 return;
1833 }
1834
1835 if (state)
1836 rtw89_write32_set(rtwdev, reg, bitmap);
1837 else
1838 rtw89_write32_clr(rtwdev, reg, bitmap);
1839 }
1840
__btc_ctrl_val_all_time(u32 ctrl)1841 static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1842 {
1843 return FIELD_GET(GENMASK(15, 0), ctrl);
1844 }
1845
__btc_ctrl_rst_all_time(u32 cur)1846 static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1847 {
1848 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1849 }
1850
__btc_ctrl_gen_all_time(u32 cur,u32 val)1851 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1852 {
1853 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1854 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1855
1856 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1857 }
1858
__btc_ctrl_val_gnt_bt(u32 ctrl)1859 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1860 {
1861 return FIELD_GET(GENMASK(31, 16), ctrl);
1862 }
1863
__btc_ctrl_rst_gnt_bt(u32 cur)1864 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1865 {
1866 return cur & ~B_AX_TXAGC_BT_EN;
1867 }
1868
__btc_ctrl_gen_gnt_bt(u32 cur,u32 val)1869 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1870 {
1871 u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1872 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1873
1874 return ov | iv | B_AX_TXAGC_BT_EN;
1875 }
1876
1877 static void
rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)1878 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1879 {
1880 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1881 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1882
1883 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1884 #define __handle(_case) \
1885 do { \
1886 const u32 _reg = __btc_cr_ ## _case; \
1887 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \
1888 u32 _cur, _wrt; \
1889 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1890 "btc ctrl %s: 0x%x\n", #_case, _val); \
1891 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1892 break; \
1893 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1894 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \
1895 _wrt = __do_clr(_val) ? \
1896 __btc_ctrl_rst_ ## _case(_cur) : \
1897 __btc_ctrl_gen_ ## _case(_cur, _val); \
1898 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1899 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1900 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \
1901 } while (0)
1902
1903 __handle(all_time);
1904 __handle(gnt_bt);
1905
1906 #undef __handle
1907 #undef __do_clr
1908 }
1909
1910 static
rtw8852a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)1911 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1912 {
1913 return clamp_t(s8, val, -100, 0) + 100;
1914 }
1915
1916 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
1917 {255, 0, 0, 7}, /* 0 -> original */
1918 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1919 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1920 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1921 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1922 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1923 {6, 1, 0, 7},
1924 {13, 1, 0, 7},
1925 {13, 1, 0, 7}
1926 };
1927
1928 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
1929 {255, 0, 0, 7}, /* 0 -> original */
1930 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1931 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1932 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1933 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1934 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1935 {255, 1, 0, 7},
1936 {255, 1, 0, 7},
1937 {255, 1, 0, 7}
1938 };
1939
1940 static const
1941 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
1942 static const
1943 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
1944
1945 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
1946 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1947 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1948 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1949 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1950 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1951 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1952 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1953 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1954 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1955 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1956 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1957 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1958 };
1959
1960 static
rtw8852a_btc_bt_aci_imp(struct rtw89_dev * rtwdev)1961 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
1962 {
1963 struct rtw89_btc *btc = &rtwdev->btc;
1964 struct rtw89_btc_dm *dm = &btc->dm;
1965 struct rtw89_btc_bt_info *bt = &btc->cx.bt;
1966 struct rtw89_btc_bt_link_info *b = &bt->link_info;
1967
1968 /* fix LNA2 = level-5 for BT ACI issue at BTG */
1969 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
1970 dm->trx_para_level = 1;
1971 }
1972
1973 static
rtw8852a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)1974 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1975 {
1976 struct rtw89_btc *btc = &rtwdev->btc;
1977 struct rtw89_btc_cx *cx = &btc->cx;
1978 u32 val;
1979
1980 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1981 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
1982 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
1983
1984 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1985 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
1986 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
1987
1988 /* clock-gate off before reset counter*/
1989 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1990 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1991 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1992 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1993 }
1994
1995 static
rtw8852a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)1996 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1997 {
1998 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1999 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2000 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
2001
2002 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2003 if (state)
2004 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2005 RFREG_MASK, 0xa2d7c);
2006 else
2007 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2008 RFREG_MASK, 0xa2020);
2009
2010 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2011 }
2012
rtw8852a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2013 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2014 struct rtw89_rx_phy_ppdu *phy_ppdu,
2015 struct ieee80211_rx_status *status)
2016 {
2017 u16 chan = phy_ppdu->chan_idx;
2018 u8 band;
2019
2020 if (chan == 0)
2021 return;
2022
2023 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
2024 status->freq = ieee80211_channel_to_frequency(chan, band);
2025 status->band = band;
2026 }
2027
rtw8852a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2028 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2029 struct rtw89_rx_phy_ppdu *phy_ppdu,
2030 struct ieee80211_rx_status *status)
2031 {
2032 u8 path;
2033 s8 *rx_power = phy_ppdu->rssi;
2034
2035 status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]);
2036 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2037 status->chains |= BIT(path);
2038 status->chain_signal[path] = rx_power[path];
2039 }
2040 if (phy_ppdu->valid)
2041 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2042 }
2043
2044 static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2045 .enable_bb_rf = rtw89_mac_enable_bb_rf,
2046 .disable_bb_rf = rtw89_mac_disable_bb_rf,
2047 .bb_reset = rtw8852a_bb_reset,
2048 .bb_sethw = rtw8852a_bb_sethw,
2049 .read_rf = rtw89_phy_read_rf,
2050 .write_rf = rtw89_phy_write_rf,
2051 .set_channel = rtw8852a_set_channel,
2052 .set_channel_help = rtw8852a_set_channel_help,
2053 .read_efuse = rtw8852a_read_efuse,
2054 .read_phycap = rtw8852a_read_phycap,
2055 .fem_setup = rtw8852a_fem_setup,
2056 .rfk_init = rtw8852a_rfk_init,
2057 .rfk_channel = rtw8852a_rfk_channel,
2058 .rfk_band_changed = rtw8852a_rfk_band_changed,
2059 .rfk_scan = rtw8852a_rfk_scan,
2060 .rfk_track = rtw8852a_rfk_track,
2061 .power_trim = rtw8852a_power_trim,
2062 .set_txpwr = rtw8852a_set_txpwr,
2063 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl,
2064 .init_txpwr_unit = rtw8852a_init_txpwr_unit,
2065 .get_thermal = rtw8852a_get_thermal,
2066 .ctrl_btg = rtw8852a_ctrl_btg,
2067 .query_ppdu = rtw8852a_query_ppdu,
2068 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc,
2069 .cfg_txrx_path = NULL,
2070 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
2071 .pwr_on_func = NULL,
2072 .pwr_off_func = NULL,
2073 .fill_txdesc = rtw89_core_fill_txdesc,
2074 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2075 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2076 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2077 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2078 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2079 .h2c_dctl_sec_cam = NULL,
2080
2081 .btc_set_rfe = rtw8852a_btc_set_rfe,
2082 .btc_init_cfg = rtw8852a_btc_init_cfg,
2083 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
2084 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
2085 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
2086 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp,
2087 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
2088 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
2089 };
2090
2091 const struct rtw89_chip_info rtw8852a_chip_info = {
2092 .chip_id = RTL8852A,
2093 .ops = &rtw8852a_chip_ops,
2094 .fw_name = "rtw89/rtw8852a_fw.bin",
2095 .fifo_size = 458752,
2096 .max_amsdu_limit = 3500,
2097 .dis_2g_40m_ul_ofdma = true,
2098 .rsvd_ple_ofst = 0x6f800,
2099 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
2100 .dle_mem = rtw8852a_dle_mem_pcie,
2101 .rf_base_addr = {0xc000, 0xd000},
2102 .pwr_on_seq = pwr_on_seq_8852a,
2103 .pwr_off_seq = pwr_off_seq_8852a,
2104 .bb_table = &rtw89_8852a_phy_bb_table,
2105 .bb_gain_table = NULL,
2106 .rf_table = {&rtw89_8852a_phy_radioa_table,
2107 &rtw89_8852a_phy_radiob_table,},
2108 .nctl_table = &rtw89_8852a_phy_nctl_table,
2109 .byr_table = &rtw89_8852a_byr_table,
2110 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g,
2111 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g,
2112 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g,
2113 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g,
2114 .txpwr_factor_rf = 2,
2115 .txpwr_factor_mac = 1,
2116 .dig_table = &rtw89_8852a_phy_dig_table,
2117 .tssi_dbw_table = NULL,
2118 .support_bands = BIT(NL80211_BAND_2GHZ) |
2119 BIT(NL80211_BAND_5GHZ),
2120 .support_bw160 = false,
2121 .hw_sec_hdr = false,
2122 .rf_path_num = 2,
2123 .tx_nss = 2,
2124 .rx_nss = 2,
2125 .acam_num = 128,
2126 .bcam_num = 10,
2127 .scam_num = 128,
2128 .sec_ctrl_efuse_size = 4,
2129 .physical_efuse_size = 1216,
2130 .logical_efuse_size = 1536,
2131 .limit_efuse_size = 1152,
2132 .dav_phy_efuse_size = 0,
2133 .dav_log_efuse_size = 0,
2134 .phycap_addr = 0x580,
2135 .phycap_size = 128,
2136 .para_ver = 0x05050864,
2137 .wlcx_desired = 0x05050000,
2138 .btcx_desired = 0x5,
2139 .scbd = 0x1,
2140 .mailbox = 0x1,
2141 .afh_guard_ch = 6,
2142 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres,
2143 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres,
2144 .rssi_tol = 2,
2145 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2146 .mon_reg = rtw89_btc_8852a_mon_reg,
2147 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
2148 .rf_para_ulink = rtw89_btc_8852a_rf_ul,
2149 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2150 .rf_para_dlink = rtw89_btc_8852a_rf_dl,
2151 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2152 BIT(RTW89_PS_MODE_CLK_GATED) |
2153 BIT(RTW89_PS_MODE_PWR_GATED),
2154 .low_power_hci_modes = 0,
2155 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2156 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2157 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2158 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2159 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2160 .h2c_regs = rtw8852a_h2c_regs,
2161 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2162 .c2h_regs = rtw8852a_c2h_regs,
2163 .page_regs = &rtw8852a_page_regs,
2164 .dcfo_comp = &rtw8852a_dcfo_comp,
2165 .dcfo_comp_sft = 3,
2166 .imr_info = &rtw8852a_imr_info
2167 };
2168 EXPORT_SYMBOL(rtw8852a_chip_info);
2169
2170 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin");
2171 MODULE_AUTHOR("Realtek Corporation");
2172 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2173 MODULE_LICENSE("Dual BSD/GPL");
2174