1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/timekeeping.h>
6 #include "mt7915.h"
7 #include "../dma.h"
8 #include "mac.h"
9 #include "mcu.h"
10
11 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
12
13 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
14 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
15 IEEE80211_RADIOTAP_HE_##f)
16
17 static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
18 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
19 .radar_pattern = {
20 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
21 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
22 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
23 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
24 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
25 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
26 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
27 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
28 },
29 };
30
31 static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
32 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
33 .radar_pattern = {
34 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
35 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
36 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
37 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
38 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
39 },
40 };
41
42 static const struct mt7915_dfs_radar_spec jp_radar_specs = {
43 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
44 .radar_pattern = {
45 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
46 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
47 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
48 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
49 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
50 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
51 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
52 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
53 },
54 };
55
mt7915_rx_get_wcid(struct mt7915_dev * dev,u16 idx,bool unicast)56 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
57 u16 idx, bool unicast)
58 {
59 struct mt7915_sta *sta;
60 struct mt76_wcid *wcid;
61
62 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
63 return NULL;
64
65 wcid = rcu_dereference(dev->mt76.wcid[idx]);
66 if (unicast || !wcid)
67 return wcid;
68
69 if (!wcid->sta)
70 return NULL;
71
72 sta = container_of(wcid, struct mt7915_sta, wcid);
73 if (!sta->vif)
74 return NULL;
75
76 return &sta->vif->sta.wcid;
77 }
78
mt7915_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)79 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
80 {
81 }
82
mt7915_mac_wtbl_update(struct mt7915_dev * dev,int idx,u32 mask)83 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
84 {
85 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
86 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
87
88 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
89 0, 5000);
90 }
91
mt7915_mac_wtbl_lmac_addr(struct mt7915_dev * dev,u16 wcid,u8 dw)92 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw)
93 {
94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
96
97 return MT_WTBL_LMAC_OFFS(wcid, dw);
98 }
99
mt7915_mac_sta_poll(struct mt7915_dev * dev)100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
101 {
102 static const u8 ac_to_tid[] = {
103 [IEEE80211_AC_BE] = 0,
104 [IEEE80211_AC_BK] = 1,
105 [IEEE80211_AC_VI] = 4,
106 [IEEE80211_AC_VO] = 6
107 };
108 struct ieee80211_sta *sta;
109 struct mt7915_sta *msta;
110 struct rate_info *rate;
111 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
112 LIST_HEAD(sta_poll_list);
113 int i;
114
115 spin_lock_bh(&dev->sta_poll_lock);
116 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
117 spin_unlock_bh(&dev->sta_poll_lock);
118
119 rcu_read_lock();
120
121 while (true) {
122 bool clear = false;
123 u32 addr, val;
124 u16 idx;
125 u8 bw;
126
127 spin_lock_bh(&dev->sta_poll_lock);
128 if (list_empty(&sta_poll_list)) {
129 spin_unlock_bh(&dev->sta_poll_lock);
130 break;
131 }
132 msta = list_first_entry(&sta_poll_list,
133 struct mt7915_sta, poll_list);
134 list_del_init(&msta->poll_list);
135 spin_unlock_bh(&dev->sta_poll_lock);
136
137 idx = msta->wcid.idx;
138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20);
139
140 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
141 u32 tx_last = msta->airtime_ac[i];
142 u32 rx_last = msta->airtime_ac[i + 4];
143
144 msta->airtime_ac[i] = mt76_rr(dev, addr);
145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
146
147 tx_time[i] = msta->airtime_ac[i] - tx_last;
148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
149
150 if ((tx_last | rx_last) & BIT(30))
151 clear = true;
152
153 addr += 8;
154 }
155
156 if (clear) {
157 mt7915_mac_wtbl_update(dev, idx,
158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
160 }
161
162 if (!msta->wcid.sta)
163 continue;
164
165 sta = container_of((void *)msta, struct ieee80211_sta,
166 drv_priv);
167 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
168 u8 q = mt76_connac_lmac_mapping(i);
169 u32 tx_cur = tx_time[q];
170 u32 rx_cur = rx_time[q];
171 u8 tid = ac_to_tid[i];
172
173 if (!tx_cur && !rx_cur)
174 continue;
175
176 ieee80211_sta_register_airtime(sta, tid, tx_cur,
177 rx_cur);
178 }
179
180 /*
181 * We don't support reading GI info from txs packets.
182 * For accurate tx status reporting and AQL improvement,
183 * we need to make sure that flags match so polling GI
184 * from per-sta counters directly.
185 */
186 rate = &msta->wcid.rate;
187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7);
188 val = mt76_rr(dev, addr);
189
190 switch (rate->bw) {
191 case RATE_INFO_BW_160:
192 bw = IEEE80211_STA_RX_BW_160;
193 break;
194 case RATE_INFO_BW_80:
195 bw = IEEE80211_STA_RX_BW_80;
196 break;
197 case RATE_INFO_BW_40:
198 bw = IEEE80211_STA_RX_BW_40;
199 break;
200 default:
201 bw = IEEE80211_STA_RX_BW_20;
202 break;
203 }
204
205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) {
206 u8 offs = 24 + 2 * bw;
207
208 rate->he_gi = (val & (0x3 << offs)) >> offs;
209 } else if (rate->flags &
210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) {
211 if (val & BIT(12 + bw))
212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
213 else
214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI;
215 }
216 }
217
218 rcu_read_unlock();
219 }
220
221 static void
mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status * status,struct ieee80211_radiotap_he * he,__le32 * rxv)222 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
223 struct ieee80211_radiotap_he *he,
224 __le32 *rxv)
225 {
226 u32 ru_h, ru_l;
227 u8 ru, offs = 0;
228
229 ru_l = le32_get_bits(rxv[0], MT_PRXV_HE_RU_ALLOC_L);
230 ru_h = le32_get_bits(rxv[1], MT_PRXV_HE_RU_ALLOC_H);
231 ru = (u8)(ru_l | ru_h << 4);
232
233 status->bw = RATE_INFO_BW_HE_RU;
234
235 switch (ru) {
236 case 0 ... 36:
237 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
238 offs = ru;
239 break;
240 case 37 ... 52:
241 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
242 offs = ru - 37;
243 break;
244 case 53 ... 60:
245 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
246 offs = ru - 53;
247 break;
248 case 61 ... 64:
249 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
250 offs = ru - 61;
251 break;
252 case 65 ... 66:
253 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
254 offs = ru - 65;
255 break;
256 case 67:
257 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
258 break;
259 case 68:
260 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
261 break;
262 }
263
264 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
265 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
266 le16_encode_bits(offs,
267 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
268 }
269
270 static void
mt7915_mac_decode_he_mu_radiotap(struct sk_buff * skb,__le32 * rxv)271 mt7915_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv)
272 {
273 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
274 static const struct ieee80211_radiotap_he_mu mu_known = {
275 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) |
276 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) |
277 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) |
278 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN),
279 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN),
280 };
281 struct ieee80211_radiotap_he_mu *he_mu = NULL;
282
283 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
284
285 he_mu = skb_push(skb, sizeof(mu_known));
286 memcpy(he_mu, &mu_known, sizeof(mu_known));
287
288 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f)
289
290 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx);
291 if (status->he_dcm)
292 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm);
293
294 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) |
295 MU_PREP(FLAGS2_SIG_B_SYMS_USERS,
296 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER));
297
298 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0);
299
300 if (status->bw >= RATE_INFO_BW_40) {
301 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN);
302 he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1);
303 }
304
305 if (status->bw >= RATE_INFO_BW_80) {
306 he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2);
307 he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3);
308 }
309 }
310
311 static void
mt7915_mac_decode_he_radiotap(struct sk_buff * skb,__le32 * rxv,u8 mode)312 mt7915_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u8 mode)
313 {
314 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
315 static const struct ieee80211_radiotap_he known = {
316 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
317 HE_BITS(DATA1_DATA_DCM_KNOWN) |
318 HE_BITS(DATA1_STBC_KNOWN) |
319 HE_BITS(DATA1_CODING_KNOWN) |
320 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
321 HE_BITS(DATA1_DOPPLER_KNOWN) |
322 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
323 HE_BITS(DATA1_BSS_COLOR_KNOWN),
324 .data2 = HE_BITS(DATA2_GI_KNOWN) |
325 HE_BITS(DATA2_TXBF_KNOWN) |
326 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
327 HE_BITS(DATA2_TXOP_KNOWN),
328 };
329 struct ieee80211_radiotap_he *he = NULL;
330 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1;
331
332 status->flag |= RX_FLAG_RADIOTAP_HE;
333
334 he = skb_push(skb, sizeof(known));
335 memcpy(he, &known, sizeof(known));
336
337 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) |
338 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]);
339 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
340 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) |
341 le16_encode_bits(ltf_size,
342 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
343 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF)
344 he->data5 |= HE_BITS(DATA5_TXBF);
345 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) |
346 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]);
347
348 switch (mode) {
349 case MT_PHY_TYPE_HE_SU:
350 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
351 HE_BITS(DATA1_UL_DL_KNOWN) |
352 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
353 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
354
355 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) |
356 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
357 break;
358 case MT_PHY_TYPE_HE_EXT_SU:
359 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
360 HE_BITS(DATA1_UL_DL_KNOWN) |
361 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
362
363 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
364 break;
365 case MT_PHY_TYPE_HE_MU:
366 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
367 HE_BITS(DATA1_UL_DL_KNOWN);
368
369 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
370 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]);
371
372 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
373 mt7915_mac_decode_he_mu_radiotap(skb, rxv);
374 break;
375 case MT_PHY_TYPE_HE_TB:
376 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
377 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
378 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
379 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
380
381 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) |
382 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) |
383 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) |
384 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]);
385
386 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
387 break;
388 default:
389 break;
390 }
391 }
392
393 /* The HW does not translate the mac header to 802.3 for mesh point */
mt7915_reverse_frag0_hdr_trans(struct sk_buff * skb,u16 hdr_gap)394 static int mt7915_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap)
395 {
396 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
397 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap);
398 struct mt7915_sta *msta = (struct mt7915_sta *)status->wcid;
399 __le32 *rxd = (__le32 *)skb->data;
400 struct ieee80211_sta *sta;
401 struct ieee80211_vif *vif;
402 struct ieee80211_hdr hdr;
403 u16 frame_control;
404
405 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) !=
406 MT_RXD3_NORMAL_U2M)
407 return -EINVAL;
408
409 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4))
410 return -EINVAL;
411
412 if (!msta || !msta->vif)
413 return -EINVAL;
414
415 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
416 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
417
418 /* store the info from RXD and ethhdr to avoid being overridden */
419 frame_control = le32_get_bits(rxd[6], MT_RXD6_FRAME_CONTROL);
420 hdr.frame_control = cpu_to_le16(frame_control);
421 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_SEQ_CTRL));
422 hdr.duration_id = 0;
423
424 ether_addr_copy(hdr.addr1, vif->addr);
425 ether_addr_copy(hdr.addr2, sta->addr);
426 switch (frame_control & (IEEE80211_FCTL_TODS |
427 IEEE80211_FCTL_FROMDS)) {
428 case 0:
429 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid);
430 break;
431 case IEEE80211_FCTL_FROMDS:
432 ether_addr_copy(hdr.addr3, eth_hdr->h_source);
433 break;
434 case IEEE80211_FCTL_TODS:
435 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
436 break;
437 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS:
438 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
439 ether_addr_copy(hdr.addr4, eth_hdr->h_source);
440 break;
441 default:
442 break;
443 }
444
445 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2);
446 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) ||
447 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX))
448 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header);
449 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN)
450 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header);
451 else
452 skb_pull(skb, 2);
453
454 if (ieee80211_has_order(hdr.frame_control))
455 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[9],
456 IEEE80211_HT_CTL_LEN);
457 if (ieee80211_is_data_qos(hdr.frame_control)) {
458 __le16 qos_ctrl;
459
460 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_QOS_CTL));
461 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl,
462 IEEE80211_QOS_CTL_LEN);
463 }
464
465 if (ieee80211_has_a4(hdr.frame_control))
466 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr));
467 else
468 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6);
469
470 return 0;
471 }
472
473 static int
mt7915_mac_fill_rx_rate(struct mt7915_dev * dev,struct mt76_rx_status * status,struct ieee80211_supported_band * sband,__le32 * rxv,u8 * mode)474 mt7915_mac_fill_rx_rate(struct mt7915_dev *dev,
475 struct mt76_rx_status *status,
476 struct ieee80211_supported_band *sband,
477 __le32 *rxv, u8 *mode)
478 {
479 u32 v0, v2;
480 u8 stbc, gi, bw, dcm, nss;
481 int i, idx;
482 bool cck = false;
483
484 v0 = le32_to_cpu(rxv[0]);
485 v2 = le32_to_cpu(rxv[2]);
486
487 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
488 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;
489
490 if (!is_mt7915(&dev->mt76)) {
491 stbc = FIELD_GET(MT_PRXV_HT_STBC, v0);
492 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v0);
493 *mode = FIELD_GET(MT_PRXV_TX_MODE, v0);
494 dcm = FIELD_GET(MT_PRXV_DCM, v0);
495 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0);
496 } else {
497 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
498 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
499 *mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
500 dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM);
501 bw = FIELD_GET(MT_CRXV_FRAME_MODE, v2);
502 }
503
504 switch (*mode) {
505 case MT_PHY_TYPE_CCK:
506 cck = true;
507 fallthrough;
508 case MT_PHY_TYPE_OFDM:
509 i = mt76_get_rate(&dev->mt76, sband, i, cck);
510 break;
511 case MT_PHY_TYPE_HT_GF:
512 case MT_PHY_TYPE_HT:
513 status->encoding = RX_ENC_HT;
514 if (gi)
515 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
516 if (i > 31)
517 return -EINVAL;
518 break;
519 case MT_PHY_TYPE_VHT:
520 status->nss = nss;
521 status->encoding = RX_ENC_VHT;
522 if (gi)
523 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
524 if (i > 11)
525 return -EINVAL;
526 break;
527 case MT_PHY_TYPE_HE_MU:
528 case MT_PHY_TYPE_HE_SU:
529 case MT_PHY_TYPE_HE_EXT_SU:
530 case MT_PHY_TYPE_HE_TB:
531 status->nss = nss;
532 status->encoding = RX_ENC_HE;
533 i &= GENMASK(3, 0);
534
535 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
536 status->he_gi = gi;
537
538 status->he_dcm = dcm;
539 break;
540 default:
541 return -EINVAL;
542 }
543 status->rate_idx = i;
544
545 switch (bw) {
546 case IEEE80211_STA_RX_BW_20:
547 break;
548 case IEEE80211_STA_RX_BW_40:
549 if (*mode & MT_PHY_TYPE_HE_EXT_SU &&
550 (idx & MT_PRXV_TX_ER_SU_106T)) {
551 status->bw = RATE_INFO_BW_HE_RU;
552 status->he_ru =
553 NL80211_RATE_INFO_HE_RU_ALLOC_106;
554 } else {
555 status->bw = RATE_INFO_BW_40;
556 }
557 break;
558 case IEEE80211_STA_RX_BW_80:
559 status->bw = RATE_INFO_BW_80;
560 break;
561 case IEEE80211_STA_RX_BW_160:
562 status->bw = RATE_INFO_BW_160;
563 break;
564 default:
565 return -EINVAL;
566 }
567
568 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
569 if (*mode < MT_PHY_TYPE_HE_SU && gi)
570 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
571
572 return 0;
573 }
574
575 static int
mt7915_mac_fill_rx(struct mt7915_dev * dev,struct sk_buff * skb)576 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
577 {
578 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
579 struct mt76_phy *mphy = &dev->mt76.phy;
580 struct mt7915_phy *phy = &dev->phy;
581 struct ieee80211_supported_band *sband;
582 __le32 *rxd = (__le32 *)skb->data;
583 __le32 *rxv = NULL;
584 u32 rxd0 = le32_to_cpu(rxd[0]);
585 u32 rxd1 = le32_to_cpu(rxd[1]);
586 u32 rxd2 = le32_to_cpu(rxd[2]);
587 u32 rxd3 = le32_to_cpu(rxd[3]);
588 u32 rxd4 = le32_to_cpu(rxd[4]);
589 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
590 bool unicast, insert_ccmp_hdr = false;
591 u8 remove_pad, amsdu_info;
592 u8 mode = 0, qos_ctl = 0;
593 bool hdr_trans;
594 u16 hdr_gap;
595 u16 seq_ctrl = 0;
596 __le16 fc = 0;
597 int idx;
598
599 memset(status, 0, sizeof(*status));
600
601 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) {
602 mphy = dev->mt76.phy2;
603 if (!mphy)
604 return -EINVAL;
605
606 phy = mphy->priv;
607 status->ext_phy = true;
608 }
609
610 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
611 return -EINVAL;
612
613 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
614 return -EINVAL;
615
616 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS;
617 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM))
618 return -EINVAL;
619
620 /* ICV error or CCMP/BIP/WPI MIC error */
621 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR)
622 status->flag |= RX_FLAG_ONLY_MONITOR;
623
624 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
625 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
626 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
627
628 if (status->wcid) {
629 struct mt7915_sta *msta;
630
631 msta = container_of(status->wcid, struct mt7915_sta, wcid);
632 spin_lock_bh(&dev->sta_poll_lock);
633 if (list_empty(&msta->poll_list))
634 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
635 spin_unlock_bh(&dev->sta_poll_lock);
636 }
637
638 status->freq = mphy->chandef.chan->center_freq;
639 status->band = mphy->chandef.chan->band;
640 if (status->band == NL80211_BAND_5GHZ)
641 sband = &mphy->sband_5g.sband;
642 else if (status->band == NL80211_BAND_6GHZ)
643 sband = &mphy->sband_6g.sband;
644 else
645 sband = &mphy->sband_2g.sband;
646
647 if (!sband->channels)
648 return -EINVAL;
649
650 if ((rxd0 & csum_mask) == csum_mask)
651 skb->ip_summed = CHECKSUM_UNNECESSARY;
652
653 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
654 status->flag |= RX_FLAG_FAILED_FCS_CRC;
655
656 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
657 status->flag |= RX_FLAG_MMIC_ERROR;
658
659 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
660 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
661 status->flag |= RX_FLAG_DECRYPTED;
662 status->flag |= RX_FLAG_IV_STRIPPED;
663 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
664 }
665
666 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
667
668 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
669 return -EINVAL;
670
671 rxd += 6;
672 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
673 u32 v0 = le32_to_cpu(rxd[0]);
674 u32 v2 = le32_to_cpu(rxd[2]);
675
676 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
677 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2);
678 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
679
680 rxd += 4;
681 if ((u8 *)rxd - skb->data >= skb->len)
682 return -EINVAL;
683 }
684
685 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
686 u8 *data = (u8 *)rxd;
687
688 if (status->flag & RX_FLAG_DECRYPTED) {
689 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) {
690 case MT_CIPHER_AES_CCMP:
691 case MT_CIPHER_CCMP_CCX:
692 case MT_CIPHER_CCMP_256:
693 insert_ccmp_hdr =
694 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
695 fallthrough;
696 case MT_CIPHER_TKIP:
697 case MT_CIPHER_TKIP_NO_MIC:
698 case MT_CIPHER_GCMP:
699 case MT_CIPHER_GCMP_256:
700 status->iv[0] = data[5];
701 status->iv[1] = data[4];
702 status->iv[2] = data[3];
703 status->iv[3] = data[2];
704 status->iv[4] = data[1];
705 status->iv[5] = data[0];
706 break;
707 default:
708 break;
709 }
710 }
711 rxd += 4;
712 if ((u8 *)rxd - skb->data >= skb->len)
713 return -EINVAL;
714 }
715
716 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
717 status->timestamp = le32_to_cpu(rxd[0]);
718 status->flag |= RX_FLAG_MACTIME_START;
719
720 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
721 status->flag |= RX_FLAG_AMPDU_DETAILS;
722
723 /* all subframes of an A-MPDU have the same timestamp */
724 if (phy->rx_ampdu_ts != status->timestamp) {
725 if (!++phy->ampdu_ref)
726 phy->ampdu_ref++;
727 }
728 phy->rx_ampdu_ts = status->timestamp;
729
730 status->ampdu_ref = phy->ampdu_ref;
731 }
732
733 rxd += 2;
734 if ((u8 *)rxd - skb->data >= skb->len)
735 return -EINVAL;
736 }
737
738 /* RXD Group 3 - P-RXV */
739 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
740 u32 v0, v1;
741 int ret;
742
743 rxv = rxd;
744 rxd += 2;
745 if ((u8 *)rxd - skb->data >= skb->len)
746 return -EINVAL;
747
748 v0 = le32_to_cpu(rxv[0]);
749 v1 = le32_to_cpu(rxv[1]);
750
751 if (v0 & MT_PRXV_HT_AD_CODE)
752 status->enc_flags |= RX_ENC_FLAG_LDPC;
753
754 status->chains = mphy->antenna_mask;
755 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
756 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
757 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
758 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
759
760 /* RXD Group 5 - C-RXV */
761 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
762 rxd += 18;
763 if ((u8 *)rxd - skb->data >= skb->len)
764 return -EINVAL;
765 }
766
767 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) {
768 ret = mt7915_mac_fill_rx_rate(dev, status, sband, rxv,
769 &mode);
770 if (ret < 0)
771 return ret;
772 }
773 }
774
775 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4);
776 status->amsdu = !!amsdu_info;
777 if (status->amsdu) {
778 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
779 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
780 }
781
782 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
783 if (hdr_trans && ieee80211_has_morefrags(fc)) {
784 if (mt7915_reverse_frag0_hdr_trans(skb, hdr_gap))
785 return -EINVAL;
786 hdr_trans = false;
787 } else {
788 int pad_start = 0;
789
790 skb_pull(skb, hdr_gap);
791 if (!hdr_trans && status->amsdu) {
792 pad_start = ieee80211_get_hdrlen_from_skb(skb);
793 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
794 /*
795 * When header translation failure is indicated,
796 * the hardware will insert an extra 2-byte field
797 * containing the data length after the protocol
798 * type field.
799 */
800 pad_start = 12;
801 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
802 pad_start += 4;
803
804 if (get_unaligned_be16(skb->data + pad_start) !=
805 skb->len - pad_start - 2)
806 pad_start = 0;
807 }
808
809 if (pad_start) {
810 memmove(skb->data + 2, skb->data, pad_start);
811 skb_pull(skb, 2);
812 }
813 }
814
815 if (!hdr_trans) {
816 struct ieee80211_hdr *hdr;
817
818 if (insert_ccmp_hdr) {
819 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
820
821 mt76_insert_ccmp_hdr(skb, key_id);
822 }
823
824 hdr = mt76_skb_get_hdr(skb);
825 fc = hdr->frame_control;
826 if (ieee80211_is_data_qos(fc)) {
827 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
828 qos_ctl = *ieee80211_get_qos_ctl(hdr);
829 }
830 } else {
831 status->flag |= RX_FLAG_8023;
832 }
833
834 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
835 mt7915_mac_decode_he_radiotap(skb, rxv, mode);
836
837 if (!status->wcid || !ieee80211_is_data_qos(fc))
838 return 0;
839
840 status->aggr = unicast &&
841 !ieee80211_is_qos_nullfunc(fc);
842 status->qos_ctl = qos_ctl;
843 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
844
845 return 0;
846 }
847
848 static void
mt7915_mac_fill_rx_vector(struct mt7915_dev * dev,struct sk_buff * skb)849 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb)
850 {
851 #ifdef CONFIG_NL80211_TESTMODE
852 struct mt7915_phy *phy = &dev->phy;
853 __le32 *rxd = (__le32 *)skb->data;
854 __le32 *rxv_hdr = rxd + 2;
855 __le32 *rxv = rxd + 4;
856 u32 rcpi, ib_rssi, wb_rssi, v20, v21;
857 u8 band_idx;
858 s32 foe;
859 u8 snr;
860 int i;
861
862 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX);
863 if (band_idx && !phy->band_idx) {
864 phy = mt7915_ext_phy(dev);
865 if (!phy)
866 goto out;
867 }
868
869 rcpi = le32_to_cpu(rxv[6]);
870 ib_rssi = le32_to_cpu(rxv[7]);
871 wb_rssi = le32_to_cpu(rxv[8]) >> 5;
872
873 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) {
874 if (i == 3)
875 wb_rssi = le32_to_cpu(rxv[9]);
876
877 phy->test.last_rcpi[i] = rcpi & 0xff;
878 phy->test.last_ib_rssi[i] = ib_rssi & 0xff;
879 phy->test.last_wb_rssi[i] = wb_rssi & 0xff;
880 }
881
882 v20 = le32_to_cpu(rxv[20]);
883 v21 = le32_to_cpu(rxv[21]);
884
885 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |
886 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT);
887
888 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;
889
890 phy->test.last_freq_offset = foe;
891 phy->test.last_snr = snr;
892 out:
893 #endif
894 dev_kfree_skb(skb);
895 }
896
897 static void
mt7915_mac_write_txwi_tm(struct mt7915_phy * phy,__le32 * txwi,struct sk_buff * skb)898 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
899 struct sk_buff *skb)
900 {
901 #ifdef CONFIG_NL80211_TESTMODE
902 struct mt76_testmode_data *td = &phy->mt76->test;
903 const struct ieee80211_rate *r;
904 u8 bw, mode, nss = td->tx_rate_nss;
905 u8 rate_idx = td->tx_rate_idx;
906 u16 rateval = 0;
907 u32 val;
908 bool cck = false;
909 int band;
910
911 if (skb != phy->mt76->test.tx_skb)
912 return;
913
914 switch (td->tx_rate_mode) {
915 case MT76_TM_TX_MODE_HT:
916 nss = 1 + (rate_idx >> 3);
917 mode = MT_PHY_TYPE_HT;
918 break;
919 case MT76_TM_TX_MODE_VHT:
920 mode = MT_PHY_TYPE_VHT;
921 break;
922 case MT76_TM_TX_MODE_HE_SU:
923 mode = MT_PHY_TYPE_HE_SU;
924 break;
925 case MT76_TM_TX_MODE_HE_EXT_SU:
926 mode = MT_PHY_TYPE_HE_EXT_SU;
927 break;
928 case MT76_TM_TX_MODE_HE_TB:
929 mode = MT_PHY_TYPE_HE_TB;
930 break;
931 case MT76_TM_TX_MODE_HE_MU:
932 mode = MT_PHY_TYPE_HE_MU;
933 break;
934 case MT76_TM_TX_MODE_CCK:
935 cck = true;
936 fallthrough;
937 case MT76_TM_TX_MODE_OFDM:
938 band = phy->mt76->chandef.chan->band;
939 if (band == NL80211_BAND_2GHZ && !cck)
940 rate_idx += 4;
941
942 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx];
943 val = cck ? r->hw_value_short : r->hw_value;
944
945 mode = val >> 8;
946 rate_idx = val & 0xff;
947 break;
948 default:
949 mode = MT_PHY_TYPE_OFDM;
950 break;
951 }
952
953 switch (phy->mt76->chandef.width) {
954 case NL80211_CHAN_WIDTH_40:
955 bw = 1;
956 break;
957 case NL80211_CHAN_WIDTH_80:
958 bw = 2;
959 break;
960 case NL80211_CHAN_WIDTH_80P80:
961 case NL80211_CHAN_WIDTH_160:
962 bw = 3;
963 break;
964 default:
965 bw = 0;
966 break;
967 }
968
969 if (td->tx_rate_stbc && nss == 1) {
970 nss++;
971 rateval |= MT_TX_RATE_STBC;
972 }
973
974 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
975 FIELD_PREP(MT_TX_RATE_MODE, mode) |
976 FIELD_PREP(MT_TX_RATE_NSS, nss - 1);
977
978 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
979
980 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT);
981 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT)
982 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
983
984 val = MT_TXD6_FIXED_BW |
985 FIELD_PREP(MT_TXD6_BW, bw) |
986 FIELD_PREP(MT_TXD6_TX_RATE, rateval) |
987 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi);
988
989 /* for HE_SU/HE_EXT_SU PPDU
990 * - 1x, 2x, 4x LTF + 0.8us GI
991 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
992 * for HE_MU PPDU
993 * - 2x, 4x LTF + 0.8us GI
994 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
995 * for HE_TB PPDU
996 * - 1x, 2x LTF + 1.6us GI
997 * - 4x LTF + 3.2us GI
998 */
999 if (mode >= MT_PHY_TYPE_HE_SU)
1000 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
1001
1002 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
1003 val |= MT_TXD6_LDPC;
1004
1005 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
1006 txwi[6] |= cpu_to_le32(val);
1007 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
1008 phy->test.spe_idx));
1009 #endif
1010 }
1011
mt7915_mac_write_txwi(struct mt76_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,int pid,struct ieee80211_key_conf * key,u32 changed)1012 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
1013 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
1014 struct ieee80211_key_conf *key, u32 changed)
1015 {
1016 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1017 struct mt76_phy *mphy = &dev->phy;
1018
1019 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2)
1020 mphy = dev->phy2;
1021
1022 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, changed);
1023
1024
1025 if (mt76_testmode_enabled(mphy))
1026 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb);
1027 }
1028
mt7915_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)1029 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1030 enum mt76_txq_id qid, struct mt76_wcid *wcid,
1031 struct ieee80211_sta *sta,
1032 struct mt76_tx_info *tx_info)
1033 {
1034 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1035 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1036 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1037 struct ieee80211_key_conf *key = info->control.hw_key;
1038 struct ieee80211_vif *vif = info->control.vif;
1039 struct mt76_txwi_cache *t;
1040 struct mt7915_txp *txp;
1041 int id, i, nbuf = tx_info->nbuf - 1;
1042 u8 *txwi = (u8 *)txwi_ptr;
1043 int pid;
1044
1045 if (unlikely(tx_info->skb->len <= ETH_HLEN))
1046 return -EINVAL;
1047
1048 if (!wcid)
1049 wcid = &dev->mt76.global_wcid;
1050
1051 if (sta) {
1052 struct mt7915_sta *msta;
1053
1054 msta = (struct mt7915_sta *)sta->drv_priv;
1055
1056 if (time_after(jiffies, msta->jiffies + HZ / 4)) {
1057 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS;
1058 msta->jiffies = jiffies;
1059 }
1060 }
1061
1062 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
1063 t->skb = tx_info->skb;
1064
1065 id = mt76_token_consume(mdev, &t);
1066 if (id < 0)
1067 return id;
1068
1069 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1070 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 0);
1071
1072 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
1073 for (i = 0; i < nbuf; i++) {
1074 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
1075 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
1076 }
1077 txp->nbuf = nbuf;
1078
1079 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST);
1080
1081 if (!key)
1082 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
1083
1084 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
1085 ieee80211_is_mgmt(hdr->frame_control))
1086 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
1087
1088 if (vif) {
1089 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1090
1091 txp->bss_idx = mvif->mt76.idx;
1092 }
1093
1094 txp->token = cpu_to_le16(id);
1095 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags))
1096 txp->rept_wds_wcid = cpu_to_le16(wcid->idx);
1097 else
1098 txp->rept_wds_wcid = cpu_to_le16(0x3ff);
1099 tx_info->skb = DMA_DUMMY_DATA;
1100
1101 /* pass partial skb header to fw */
1102 tx_info->buf[1].len = MT_CT_PARSE_LEN;
1103 tx_info->buf[1].skip_unmap = true;
1104 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
1105
1106 return 0;
1107 }
1108
mt7915_wed_init_buf(void * ptr,dma_addr_t phys,int token_id)1109 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
1110 {
1111 struct mt7915_txp *txp = ptr + MT_TXD_SIZE;
1112 __le32 *txwi = ptr;
1113 u32 val;
1114
1115 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp));
1116
1117 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) |
1118 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT);
1119 txwi[0] = cpu_to_le32(val);
1120
1121 val = MT_TXD1_LONG_FORMAT |
1122 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3);
1123 txwi[1] = cpu_to_le32(val);
1124
1125 txp->token = cpu_to_le16(token_id);
1126 txp->nbuf = 1;
1127 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
1128
1129 return MT_TXD_SIZE + sizeof(*txp);
1130 }
1131
1132 static void
mt7915_tx_check_aggr(struct ieee80211_sta * sta,__le32 * txwi)1133 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
1134 {
1135 struct mt7915_sta *msta;
1136 u16 fc, tid;
1137 u32 val;
1138
1139 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he))
1140 return;
1141
1142 tid = le32_get_bits(txwi[1], MT_TXD1_TID);
1143 if (tid >= 6) /* skip VO queue */
1144 return;
1145
1146 val = le32_to_cpu(txwi[2]);
1147 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
1148 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
1149 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
1150 return;
1151
1152 msta = (struct mt7915_sta *)sta->drv_priv;
1153 if (!test_and_set_bit(tid, &msta->ampdu_state))
1154 ieee80211_start_tx_ba_session(sta, tid, 0);
1155 }
1156
1157 static void
mt7915_txp_skb_unmap(struct mt76_dev * dev,struct mt76_txwi_cache * t)1158 mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1159 {
1160 struct mt7915_txp *txp;
1161 int i;
1162
1163 txp = mt7915_txwi_to_txp(dev, t);
1164 for (i = 0; i < txp->nbuf; i++)
1165 dma_unmap_single(dev->dma_dev, le32_to_cpu(txp->buf[i]),
1166 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
1167 }
1168
1169 static void
mt7915_txwi_free(struct mt7915_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_sta * sta,struct list_head * free_list)1170 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
1171 struct ieee80211_sta *sta, struct list_head *free_list)
1172 {
1173 struct mt76_dev *mdev = &dev->mt76;
1174 struct mt7915_sta *msta;
1175 struct mt76_wcid *wcid;
1176 __le32 *txwi;
1177 u16 wcid_idx;
1178
1179 mt7915_txp_skb_unmap(mdev, t);
1180 if (!t->skb)
1181 goto out;
1182
1183 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t);
1184 if (sta) {
1185 wcid = (struct mt76_wcid *)sta->drv_priv;
1186 wcid_idx = wcid->idx;
1187 } else {
1188 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX);
1189 wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]);
1190
1191 if (wcid && wcid->sta) {
1192 msta = container_of(wcid, struct mt7915_sta, wcid);
1193 sta = container_of((void *)msta, struct ieee80211_sta,
1194 drv_priv);
1195 spin_lock_bh(&dev->sta_poll_lock);
1196 if (list_empty(&msta->poll_list))
1197 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1198 spin_unlock_bh(&dev->sta_poll_lock);
1199 }
1200 }
1201
1202 if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
1203 mt7915_tx_check_aggr(sta, txwi);
1204
1205 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list);
1206
1207 out:
1208 t->skb = NULL;
1209 mt76_put_txwi(mdev, t);
1210 }
1211
1212 static void
mt7915_mac_tx_free_prepare(struct mt7915_dev * dev)1213 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev)
1214 {
1215 struct mt76_dev *mdev = &dev->mt76;
1216 struct mt76_phy *mphy_ext = mdev->phy2;
1217
1218 /* clean DMA queues and unmap buffers first */
1219 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1220 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1221 if (mphy_ext) {
1222 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
1223 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
1224 }
1225 }
1226
1227 static void
mt7915_mac_tx_free_done(struct mt7915_dev * dev,struct list_head * free_list,bool wake)1228 mt7915_mac_tx_free_done(struct mt7915_dev *dev,
1229 struct list_head *free_list, bool wake)
1230 {
1231 struct sk_buff *skb, *tmp;
1232
1233 mt7915_mac_sta_poll(dev);
1234
1235 if (wake)
1236 mt76_set_tx_blocked(&dev->mt76, false);
1237
1238 mt76_worker_schedule(&dev->mt76.tx_worker);
1239
1240 list_for_each_entry_safe(skb, tmp, free_list, list) {
1241 skb_list_del_init(skb);
1242 napi_consume_skb(skb, 1);
1243 }
1244 }
1245
1246 static void
mt7915_mac_tx_free(struct mt7915_dev * dev,void * data,int len)1247 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
1248 {
1249 struct mt7915_tx_free *free = (struct mt7915_tx_free *)data;
1250 struct mt76_dev *mdev = &dev->mt76;
1251 struct mt76_txwi_cache *txwi;
1252 struct ieee80211_sta *sta = NULL;
1253 LIST_HEAD(free_list);
1254 void *end = data + len;
1255 bool v3, wake = false;
1256 u16 total, count = 0;
1257 u32 txd = le32_to_cpu(free->txd);
1258 __le32 *cur_info;
1259
1260 mt7915_mac_tx_free_prepare(dev);
1261
1262 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT);
1263 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4);
1264 if (WARN_ON_ONCE((void *)&free->info[total >> v3] > end))
1265 return;
1266
1267 for (cur_info = &free->info[0]; count < total; cur_info++) {
1268 u32 msdu, info = le32_to_cpu(*cur_info);
1269 u8 i;
1270
1271 /*
1272 * 1'b1: new wcid pair.
1273 * 1'b0: msdu_id with the same 'wcid pair' as above.
1274 */
1275 if (info & MT_TX_FREE_PAIR) {
1276 struct mt7915_sta *msta;
1277 struct mt76_wcid *wcid;
1278 u16 idx;
1279
1280 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
1281 wcid = rcu_dereference(dev->mt76.wcid[idx]);
1282 sta = wcid_to_sta(wcid);
1283 if (!sta)
1284 continue;
1285
1286 msta = container_of(wcid, struct mt7915_sta, wcid);
1287 spin_lock_bh(&dev->sta_poll_lock);
1288 if (list_empty(&msta->poll_list))
1289 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1290 spin_unlock_bh(&dev->sta_poll_lock);
1291 continue;
1292 }
1293
1294 if (v3 && (info & MT_TX_FREE_MPDU_HEADER))
1295 continue;
1296
1297 for (i = 0; i < 1 + v3; i++) {
1298 if (v3) {
1299 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3;
1300 if (msdu == MT_TX_FREE_MSDU_ID_V3)
1301 continue;
1302 } else {
1303 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
1304 }
1305 count++;
1306 txwi = mt76_token_release(mdev, msdu, &wake);
1307 if (!txwi)
1308 continue;
1309
1310 mt7915_txwi_free(dev, txwi, sta, &free_list);
1311 }
1312 }
1313
1314 mt7915_mac_tx_free_done(dev, &free_list, wake);
1315 }
1316
1317 static void
mt7915_mac_tx_free_v0(struct mt7915_dev * dev,void * data,int len)1318 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len)
1319 {
1320 struct mt7915_tx_free *free = (struct mt7915_tx_free *)data;
1321 struct mt76_dev *mdev = &dev->mt76;
1322 __le16 *info = (__le16 *)free->info;
1323 void *end = data + len;
1324 LIST_HEAD(free_list);
1325 bool wake = false;
1326 u8 i, count;
1327
1328 mt7915_mac_tx_free_prepare(dev);
1329
1330 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl));
1331 if (WARN_ON_ONCE((void *)&info[count] > end))
1332 return;
1333
1334 for (i = 0; i < count; i++) {
1335 struct mt76_txwi_cache *txwi;
1336 u16 msdu = le16_to_cpu(info[i]);
1337
1338 txwi = mt76_token_release(mdev, msdu, &wake);
1339 if (!txwi)
1340 continue;
1341
1342 mt7915_txwi_free(dev, txwi, NULL, &free_list);
1343 }
1344
1345 mt7915_mac_tx_free_done(dev, &free_list, wake);
1346 }
1347
1348 static bool
mt7915_mac_add_txs_skb(struct mt7915_dev * dev,struct mt76_wcid * wcid,int pid,__le32 * txs_data,struct mt76_sta_stats * stats)1349 mt7915_mac_add_txs_skb(struct mt7915_dev *dev, struct mt76_wcid *wcid, int pid,
1350 __le32 *txs_data, struct mt76_sta_stats *stats)
1351 {
1352 struct ieee80211_supported_band *sband;
1353 struct mt76_dev *mdev = &dev->mt76;
1354 struct mt76_phy *mphy;
1355 struct ieee80211_tx_info *info;
1356 struct sk_buff_head list;
1357 struct rate_info rate = {};
1358 struct sk_buff *skb;
1359 bool cck = false;
1360 u32 txrate, txs, mode;
1361
1362 mt76_tx_status_lock(mdev, &list);
1363 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list);
1364 if (!skb)
1365 goto out_no_skb;
1366
1367 txs = le32_to_cpu(txs_data[0]);
1368
1369 info = IEEE80211_SKB_CB(skb);
1370 if (!(txs & MT_TXS0_ACK_ERROR_MASK))
1371 info->flags |= IEEE80211_TX_STAT_ACK;
1372
1373 info->status.ampdu_len = 1;
1374 info->status.ampdu_ack_len = !!(info->flags &
1375 IEEE80211_TX_STAT_ACK);
1376
1377 info->status.rates[0].idx = -1;
1378
1379 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1380
1381 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate);
1382 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1;
1383
1384 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss))
1385 stats->tx_nss[rate.nss - 1]++;
1386 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs))
1387 stats->tx_mcs[rate.mcs]++;
1388
1389 mode = FIELD_GET(MT_TX_RATE_MODE, txrate);
1390 switch (mode) {
1391 case MT_PHY_TYPE_CCK:
1392 cck = true;
1393 fallthrough;
1394 case MT_PHY_TYPE_OFDM:
1395 mphy = &dev->mphy;
1396 if (wcid->ext_phy && dev->mt76.phy2)
1397 mphy = dev->mt76.phy2;
1398
1399 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1400 sband = &mphy->sband_5g.sband;
1401 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)
1402 sband = &mphy->sband_6g.sband;
1403 else
1404 sband = &mphy->sband_2g.sband;
1405
1406 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck);
1407 rate.legacy = sband->bitrates[rate.mcs].bitrate;
1408 break;
1409 case MT_PHY_TYPE_HT:
1410 case MT_PHY_TYPE_HT_GF:
1411 if (rate.mcs > 31)
1412 goto out;
1413
1414 rate.flags = RATE_INFO_FLAGS_MCS;
1415 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI)
1416 rate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1417 break;
1418 case MT_PHY_TYPE_VHT:
1419 if (rate.mcs > 9)
1420 goto out;
1421
1422 rate.flags = RATE_INFO_FLAGS_VHT_MCS;
1423 break;
1424 case MT_PHY_TYPE_HE_SU:
1425 case MT_PHY_TYPE_HE_EXT_SU:
1426 case MT_PHY_TYPE_HE_TB:
1427 case MT_PHY_TYPE_HE_MU:
1428 if (rate.mcs > 11)
1429 goto out;
1430
1431 rate.he_gi = wcid->rate.he_gi;
1432 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate);
1433 rate.flags = RATE_INFO_FLAGS_HE_MCS;
1434 break;
1435 default:
1436 goto out;
1437 }
1438
1439 stats->tx_mode[mode]++;
1440
1441 switch (FIELD_GET(MT_TXS0_BW, txs)) {
1442 case IEEE80211_STA_RX_BW_160:
1443 rate.bw = RATE_INFO_BW_160;
1444 stats->tx_bw[3]++;
1445 break;
1446 case IEEE80211_STA_RX_BW_80:
1447 rate.bw = RATE_INFO_BW_80;
1448 stats->tx_bw[2]++;
1449 break;
1450 case IEEE80211_STA_RX_BW_40:
1451 rate.bw = RATE_INFO_BW_40;
1452 stats->tx_bw[1]++;
1453 break;
1454 default:
1455 rate.bw = RATE_INFO_BW_20;
1456 stats->tx_bw[0]++;
1457 break;
1458 }
1459 wcid->rate = rate;
1460
1461 out:
1462 mt76_tx_status_skb_done(mdev, skb, &list);
1463
1464 out_no_skb:
1465 mt76_tx_status_unlock(mdev, &list);
1466
1467 return !!skb;
1468 }
1469
mt7915_mac_add_txs(struct mt7915_dev * dev,void * data)1470 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
1471 {
1472 struct mt7915_sta *msta = NULL;
1473 struct mt76_wcid *wcid;
1474 __le32 *txs_data = data;
1475 u16 wcidx;
1476 u8 pid;
1477
1478 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1)
1479 return;
1480
1481 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
1482 pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
1483
1484 if (pid < MT_PACKET_ID_FIRST)
1485 return;
1486
1487 if (wcidx >= mt7915_wtbl_size(dev))
1488 return;
1489
1490 rcu_read_lock();
1491
1492 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1493 if (!wcid)
1494 goto out;
1495
1496 msta = container_of(wcid, struct mt7915_sta, wcid);
1497
1498 mt7915_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats);
1499
1500 if (!wcid->sta)
1501 goto out;
1502
1503 spin_lock_bh(&dev->sta_poll_lock);
1504 if (list_empty(&msta->poll_list))
1505 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1506 spin_unlock_bh(&dev->sta_poll_lock);
1507
1508 out:
1509 rcu_read_unlock();
1510 }
1511
mt7915_rx_check(struct mt76_dev * mdev,void * data,int len)1512 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
1513 {
1514 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1515 __le32 *rxd = (__le32 *)data;
1516 __le32 *end = (__le32 *)&rxd[len / 4];
1517 enum rx_pkt_type type;
1518
1519 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1520
1521 switch (type) {
1522 case PKT_TYPE_TXRX_NOTIFY:
1523 mt7915_mac_tx_free(dev, data, len);
1524 return false;
1525 case PKT_TYPE_TXRX_NOTIFY_V0:
1526 mt7915_mac_tx_free_v0(dev, data, len);
1527 return false;
1528 case PKT_TYPE_TXS:
1529 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1530 mt7915_mac_add_txs(dev, rxd);
1531 return false;
1532 case PKT_TYPE_RX_FW_MONITOR:
1533 mt7915_debugfs_rx_fw_monitor(dev, data, len);
1534 return false;
1535 default:
1536 return true;
1537 }
1538 }
1539
mt7915_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)1540 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1541 struct sk_buff *skb)
1542 {
1543 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1544 __le32 *rxd = (__le32 *)skb->data;
1545 __le32 *end = (__le32 *)&skb->data[skb->len];
1546 enum rx_pkt_type type;
1547
1548 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1549
1550 switch (type) {
1551 case PKT_TYPE_TXRX_NOTIFY:
1552 mt7915_mac_tx_free(dev, skb->data, skb->len);
1553 napi_consume_skb(skb, 1);
1554 break;
1555 case PKT_TYPE_TXRX_NOTIFY_V0:
1556 mt7915_mac_tx_free_v0(dev, skb->data, skb->len);
1557 napi_consume_skb(skb, 1);
1558 break;
1559 case PKT_TYPE_RX_EVENT:
1560 mt7915_mcu_rx_event(dev, skb);
1561 break;
1562 case PKT_TYPE_TXRXV:
1563 mt7915_mac_fill_rx_vector(dev, skb);
1564 break;
1565 case PKT_TYPE_TXS:
1566 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1567 mt7915_mac_add_txs(dev, rxd);
1568 dev_kfree_skb(skb);
1569 break;
1570 case PKT_TYPE_RX_FW_MONITOR:
1571 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len);
1572 dev_kfree_skb(skb);
1573 break;
1574 case PKT_TYPE_NORMAL:
1575 if (!mt7915_mac_fill_rx(dev, skb)) {
1576 mt76_rx(&dev->mt76, q, skb);
1577 return;
1578 }
1579 fallthrough;
1580 default:
1581 dev_kfree_skb(skb);
1582 break;
1583 }
1584 }
1585
mt7915_tx_complete_skb(struct mt76_dev * mdev,struct mt76_queue_entry * e)1586 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1587 {
1588 if (!e->txwi) {
1589 dev_kfree_skb_any(e->skb);
1590 return;
1591 }
1592
1593 /* error path */
1594 if (e->skb == DMA_DUMMY_DATA) {
1595 struct mt76_txwi_cache *t;
1596 struct mt7915_txp *txp;
1597
1598 txp = mt7915_txwi_to_txp(mdev, e->txwi);
1599 t = mt76_token_put(mdev, le16_to_cpu(txp->token));
1600 e->skb = t ? t->skb : NULL;
1601 }
1602
1603 if (e->skb)
1604 mt76_tx_complete_skb(mdev, e->wcid, e->skb);
1605 }
1606
mt7915_mac_cca_stats_reset(struct mt7915_phy * phy)1607 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
1608 {
1609 struct mt7915_dev *dev = phy->dev;
1610 u32 reg = MT_WF_PHY_RX_CTRL1(phy->band_idx);
1611
1612 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
1613 mt76_set(dev, reg, BIT(11) | BIT(9));
1614 }
1615
mt7915_mac_reset_counters(struct mt7915_phy * phy)1616 void mt7915_mac_reset_counters(struct mt7915_phy *phy)
1617 {
1618 struct mt7915_dev *dev = phy->dev;
1619 int i;
1620
1621 for (i = 0; i < 4; i++) {
1622 mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
1623 mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i));
1624 }
1625
1626 i = 0;
1627 phy->mt76->survey_time = ktime_get_boottime();
1628 if (phy->band_idx)
1629 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
1630
1631 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
1632
1633 /* reset airtime counters */
1634 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->band_idx),
1635 MT_WF_RMAC_MIB_RXTIME_CLR);
1636
1637 mt7915_mcu_get_chan_mib_info(phy, true);
1638 }
1639
mt7915_mac_set_timing(struct mt7915_phy * phy)1640 void mt7915_mac_set_timing(struct mt7915_phy *phy)
1641 {
1642 s16 coverage_class = phy->coverage_class;
1643 struct mt7915_dev *dev = phy->dev;
1644 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
1645 u32 val, reg_offset;
1646 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1647 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1648 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1649 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1650 int offset;
1651 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ);
1652
1653 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1654 return;
1655
1656 if (ext_phy)
1657 coverage_class = max_t(s16, dev->phy.coverage_class,
1658 ext_phy->coverage_class);
1659
1660 mt76_set(dev, MT_ARB_SCR(phy->band_idx),
1661 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1662 udelay(1);
1663
1664 offset = 3 * coverage_class;
1665 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1666 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1667
1668 mt76_wr(dev, MT_TMAC_CDTR(phy->band_idx), cck + reg_offset);
1669 mt76_wr(dev, MT_TMAC_ODTR(phy->band_idx), ofdm + reg_offset);
1670 mt76_wr(dev, MT_TMAC_ICR0(phy->band_idx),
1671 FIELD_PREP(MT_IFS_EIFS_OFDM, a_band ? 84 : 78) |
1672 FIELD_PREP(MT_IFS_RIFS, 2) |
1673 FIELD_PREP(MT_IFS_SIFS, 10) |
1674 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1675
1676 mt76_wr(dev, MT_TMAC_ICR1(phy->band_idx),
1677 FIELD_PREP(MT_IFS_EIFS_CCK, 314));
1678
1679 if (phy->slottime < 20 || a_band)
1680 val = MT7915_CFEND_RATE_DEFAULT;
1681 else
1682 val = MT7915_CFEND_RATE_11B;
1683
1684 mt76_rmw_field(dev, MT_AGG_ACR0(phy->band_idx), MT_AGG_ACR_CFEND_RATE, val);
1685 mt76_clear(dev, MT_ARB_SCR(phy->band_idx),
1686 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1687 }
1688
mt7915_mac_enable_nf(struct mt7915_dev * dev,bool ext_phy)1689 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy)
1690 {
1691 u32 reg;
1692
1693 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(ext_phy) :
1694 MT_WF_PHY_RXTD12_MT7916(ext_phy);
1695 mt76_set(dev, reg,
1696 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |
1697 MT_WF_PHY_RXTD12_IRPI_SW_CLR);
1698
1699 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(ext_phy) :
1700 MT_WF_PHY_RX_CTRL1_MT7916(ext_phy);
1701 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));
1702 }
1703
1704 static u8
mt7915_phy_get_nf(struct mt7915_phy * phy,int idx)1705 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx)
1706 {
1707 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1708 struct mt7915_dev *dev = phy->dev;
1709 u32 val, sum = 0, n = 0;
1710 int nss, i;
1711
1712 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) {
1713 u32 reg = is_mt7915(&dev->mt76) ?
1714 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) :
1715 MT_WF_IRPI_NSS_MT7916(idx, nss);
1716
1717 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1718 val = mt76_rr(dev, reg);
1719 sum += val * nf_power[i];
1720 n += val;
1721 }
1722 }
1723
1724 if (!n)
1725 return 0;
1726
1727 return sum / n;
1728 }
1729
mt7915_update_channel(struct mt76_phy * mphy)1730 void mt7915_update_channel(struct mt76_phy *mphy)
1731 {
1732 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv;
1733 struct mt76_channel_state *state = mphy->chan_state;
1734 int nf;
1735
1736 mt7915_mcu_get_chan_mib_info(phy, false);
1737
1738 nf = mt7915_phy_get_nf(phy, phy->band_idx);
1739 if (!phy->noise)
1740 phy->noise = nf << 4;
1741 else if (nf)
1742 phy->noise += nf - (phy->noise >> 4);
1743
1744 state->noise = -(phy->noise >> 4);
1745 }
1746
1747 static bool
mt7915_wait_reset_state(struct mt7915_dev * dev,u32 state)1748 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1749 {
1750 bool ret;
1751
1752 ret = wait_event_timeout(dev->reset_wait,
1753 (READ_ONCE(dev->reset_state) & state),
1754 MT7915_RESET_TIMEOUT);
1755
1756 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1757 return ret;
1758 }
1759
1760 static void
mt7915_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)1761 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1762 {
1763 struct ieee80211_hw *hw = priv;
1764
1765 switch (vif->type) {
1766 case NL80211_IFTYPE_MESH_POINT:
1767 case NL80211_IFTYPE_ADHOC:
1768 case NL80211_IFTYPE_AP:
1769 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon,
1770 BSS_CHANGED_BEACON_ENABLED);
1771 break;
1772 default:
1773 break;
1774 }
1775 }
1776
1777 static void
mt7915_update_beacons(struct mt7915_dev * dev)1778 mt7915_update_beacons(struct mt7915_dev *dev)
1779 {
1780 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1781 IEEE80211_IFACE_ITER_RESUME_ALL,
1782 mt7915_update_vif_beacon, dev->mt76.hw);
1783
1784 if (!dev->mt76.phy2)
1785 return;
1786
1787 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1788 IEEE80211_IFACE_ITER_RESUME_ALL,
1789 mt7915_update_vif_beacon, dev->mt76.phy2->hw);
1790 }
1791
1792 static void
mt7915_dma_reset(struct mt7915_dev * dev)1793 mt7915_dma_reset(struct mt7915_dev *dev)
1794 {
1795 struct mt76_phy *mphy_ext = dev->mt76.phy2;
1796 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
1797 int i;
1798
1799 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1800 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1801 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1802
1803 if (is_mt7915(&dev->mt76))
1804 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1805 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1806 MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1807 if (dev->hif2) {
1808 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1809 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1810 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1811
1812 if (is_mt7915(&dev->mt76))
1813 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1814 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1815 MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1816 }
1817
1818 usleep_range(1000, 2000);
1819
1820 for (i = 0; i < __MT_TXQ_MAX; i++) {
1821 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1822 if (mphy_ext)
1823 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true);
1824 }
1825
1826 for (i = 0; i < __MT_MCUQ_MAX; i++)
1827 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
1828
1829 mt76_for_each_q_rx(&dev->mt76, i)
1830 mt76_queue_rx_reset(dev, i);
1831
1832 mt76_tx_status_check(&dev->mt76, true);
1833
1834 /* re-init prefetch settings after reset */
1835 mt7915_dma_prefetch(dev);
1836
1837 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1838 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1839 if (is_mt7915(&dev->mt76))
1840 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1841 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1842 MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1843 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1844 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
1845 if (dev->hif2) {
1846 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1847 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1848 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1849
1850 if (is_mt7915(&dev->mt76))
1851 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1852 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1853 MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1854 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1855 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
1856 }
1857 }
1858
mt7915_tx_token_put(struct mt7915_dev * dev)1859 void mt7915_tx_token_put(struct mt7915_dev *dev)
1860 {
1861 struct mt76_txwi_cache *txwi;
1862 int id;
1863
1864 spin_lock_bh(&dev->mt76.token_lock);
1865 idr_for_each_entry(&dev->mt76.token, txwi, id) {
1866 mt7915_txwi_free(dev, txwi, NULL, NULL);
1867 dev->mt76.token_count--;
1868 }
1869 spin_unlock_bh(&dev->mt76.token_lock);
1870 idr_destroy(&dev->mt76.token);
1871 }
1872
1873 /* system error recovery */
mt7915_mac_reset_work(struct work_struct * work)1874 void mt7915_mac_reset_work(struct work_struct *work)
1875 {
1876 struct mt7915_phy *phy2;
1877 struct mt76_phy *ext_phy;
1878 struct mt7915_dev *dev;
1879
1880 dev = container_of(work, struct mt7915_dev, reset_work);
1881 ext_phy = dev->mt76.phy2;
1882 phy2 = ext_phy ? ext_phy->priv : NULL;
1883
1884 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1885 return;
1886
1887 ieee80211_stop_queues(mt76_hw(dev));
1888 if (ext_phy)
1889 ieee80211_stop_queues(ext_phy->hw);
1890
1891 set_bit(MT76_RESET, &dev->mphy.state);
1892 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1893 wake_up(&dev->mt76.mcu.wait);
1894 cancel_delayed_work_sync(&dev->mphy.mac_work);
1895 if (phy2) {
1896 set_bit(MT76_RESET, &phy2->mt76->state);
1897 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1898 }
1899 mt76_worker_disable(&dev->mt76.tx_worker);
1900 napi_disable(&dev->mt76.napi[0]);
1901 napi_disable(&dev->mt76.napi[1]);
1902 napi_disable(&dev->mt76.napi[2]);
1903 napi_disable(&dev->mt76.tx_napi);
1904
1905 mutex_lock(&dev->mt76.mutex);
1906
1907 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1908
1909 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1910 mt7915_dma_reset(dev);
1911
1912 mt7915_tx_token_put(dev);
1913 idr_init(&dev->mt76.token);
1914
1915 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1916 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1917 }
1918
1919 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1920 clear_bit(MT76_RESET, &dev->mphy.state);
1921 if (phy2)
1922 clear_bit(MT76_RESET, &phy2->mt76->state);
1923
1924 local_bh_disable();
1925 napi_enable(&dev->mt76.napi[0]);
1926 napi_schedule(&dev->mt76.napi[0]);
1927
1928 napi_enable(&dev->mt76.napi[1]);
1929 napi_schedule(&dev->mt76.napi[1]);
1930
1931 napi_enable(&dev->mt76.napi[2]);
1932 napi_schedule(&dev->mt76.napi[2]);
1933 local_bh_enable();
1934
1935 tasklet_schedule(&dev->irq_tasklet);
1936
1937 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1938 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1939
1940 mt76_worker_enable(&dev->mt76.tx_worker);
1941
1942 napi_enable(&dev->mt76.tx_napi);
1943 napi_schedule(&dev->mt76.tx_napi);
1944
1945 ieee80211_wake_queues(mt76_hw(dev));
1946 if (ext_phy)
1947 ieee80211_wake_queues(ext_phy->hw);
1948
1949 mutex_unlock(&dev->mt76.mutex);
1950
1951 mt7915_update_beacons(dev);
1952
1953 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1954 MT7915_WATCHDOG_TIME);
1955 if (phy2)
1956 ieee80211_queue_delayed_work(ext_phy->hw,
1957 &phy2->mt76->mac_work,
1958 MT7915_WATCHDOG_TIME);
1959 }
1960
mt7915_mac_update_stats(struct mt7915_phy * phy)1961 void mt7915_mac_update_stats(struct mt7915_phy *phy)
1962 {
1963 struct mt7915_dev *dev = phy->dev;
1964 struct mib_stats *mib = &phy->mib;
1965 int i, aggr0, aggr1, cnt;
1966 u32 val;
1967
1968 cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx));
1969 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
1970 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
1971
1972 cnt = mt76_rr(dev, MT_MIB_SDR4(phy->band_idx));
1973 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);
1974
1975 cnt = mt76_rr(dev, MT_MIB_SDR5(phy->band_idx));
1976 mib->rx_mpdu_cnt += cnt;
1977
1978 cnt = mt76_rr(dev, MT_MIB_SDR6(phy->band_idx));
1979 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt);
1980
1981 cnt = mt76_rr(dev, MT_MIB_SDR7(phy->band_idx));
1982 mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt);
1983
1984 cnt = mt76_rr(dev, MT_MIB_SDR8(phy->band_idx));
1985 mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt);
1986
1987 cnt = mt76_rr(dev, MT_MIB_SDR11(phy->band_idx));
1988 mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt);
1989
1990 cnt = mt76_rr(dev, MT_MIB_SDR12(phy->band_idx));
1991 mib->tx_ampdu_cnt += cnt;
1992
1993 cnt = mt76_rr(dev, MT_MIB_SDR13(phy->band_idx));
1994 mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt);
1995
1996 cnt = mt76_rr(dev, MT_MIB_SDR14(phy->band_idx));
1997 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ?
1998 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) :
1999 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt);
2000
2001 cnt = mt76_rr(dev, MT_MIB_SDR15(phy->band_idx));
2002 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ?
2003 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) :
2004 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt);
2005
2006 cnt = mt76_rr(dev, MT_MIB_SDR22(phy->band_idx));
2007 mib->rx_ampdu_cnt += cnt;
2008
2009 cnt = mt76_rr(dev, MT_MIB_SDR23(phy->band_idx));
2010 mib->rx_ampdu_bytes_cnt += cnt;
2011
2012 cnt = mt76_rr(dev, MT_MIB_SDR24(phy->band_idx));
2013 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ?
2014 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) :
2015 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt);
2016
2017 cnt = mt76_rr(dev, MT_MIB_SDR25(phy->band_idx));
2018 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;
2019
2020 cnt = mt76_rr(dev, MT_MIB_SDR27(phy->band_idx));
2021 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt);
2022
2023 cnt = mt76_rr(dev, MT_MIB_SDR28(phy->band_idx));
2024 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt);
2025
2026 cnt = mt76_rr(dev, MT_MIB_SDR29(phy->band_idx));
2027 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ?
2028 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) :
2029 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt);
2030
2031 cnt = mt76_rr(dev, MT_MIB_SDRVEC(phy->band_idx));
2032 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ?
2033 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) :
2034 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt);
2035
2036 cnt = mt76_rr(dev, MT_MIB_SDR31(phy->band_idx));
2037 mib->rx_ba_cnt += cnt;
2038
2039 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(phy->band_idx));
2040 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
2041
2042 cnt = mt76_rr(dev, MT_MIB_DR8(phy->band_idx));
2043 mib->tx_mu_mpdu_cnt += cnt;
2044
2045 cnt = mt76_rr(dev, MT_MIB_DR9(phy->band_idx));
2046 mib->tx_mu_acked_mpdu_cnt += cnt;
2047
2048 cnt = mt76_rr(dev, MT_MIB_DR11(phy->band_idx));
2049 mib->tx_su_acked_mpdu_cnt += cnt;
2050
2051 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(phy->band_idx));
2052 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt);
2053 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt);
2054 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt);
2055
2056 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
2057 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
2058 mib->tx_amsdu[i] += cnt;
2059 mib->tx_amsdu_cnt += cnt;
2060 }
2061
2062 aggr0 = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
2063 if (is_mt7915(&dev->mt76)) {
2064 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
2065 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 4)));
2066 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
2067 mib->ack_fail_cnt +=
2068 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
2069
2070 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 4)));
2071 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
2072 mib->rts_retries_cnt +=
2073 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
2074
2075 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
2076 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
2077 dev->mt76.aggr_stats[aggr0++] += val >> 16;
2078
2079 val = mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i));
2080 dev->mt76.aggr_stats[aggr1++] += val & 0xffff;
2081 dev->mt76.aggr_stats[aggr1++] += val >> 16;
2082 }
2083
2084 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
2085 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
2086
2087 cnt = mt76_rr(dev, MT_MIB_SDR33(phy->band_idx));
2088 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt);
2089
2090 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx));
2091 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt);
2092 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt);
2093
2094 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx));
2095 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt);
2096 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt);
2097
2098 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx));
2099 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt);
2100 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt);
2101 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt);
2102 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt);
2103 } else {
2104 for (i = 0; i < 2; i++) {
2105 /* rts count */
2106 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 2)));
2107 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val);
2108 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val);
2109
2110 /* rts retry count */
2111 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 2)));
2112 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val);
2113 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val);
2114
2115 /* ba miss count */
2116 val = mt76_rr(dev, MT_MIB_MB_SDR2(phy->band_idx, (i << 2)));
2117 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val);
2118 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val);
2119
2120 /* ack fail count */
2121 val = mt76_rr(dev, MT_MIB_MB_BFTF(phy->band_idx, (i << 2)));
2122 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val);
2123 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val);
2124 }
2125
2126 for (i = 0; i < 8; i++) {
2127 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i));
2128 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val);
2129 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val);
2130 }
2131
2132 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
2133 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
2134 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
2135 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
2136 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
2137
2138 cnt = mt76_rr(dev, MT_MIB_BFCR7(phy->band_idx));
2139 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt);
2140
2141 cnt = mt76_rr(dev, MT_MIB_BFCR2(phy->band_idx));
2142 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt);
2143
2144 cnt = mt76_rr(dev, MT_MIB_BFCR0(phy->band_idx));
2145 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
2146 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
2147 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
2148 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
2149
2150 cnt = mt76_rr(dev, MT_MIB_BFCR1(phy->band_idx));
2151 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
2152 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
2153 }
2154 }
2155
mt7915_mac_severe_check(struct mt7915_phy * phy)2156 static void mt7915_mac_severe_check(struct mt7915_phy *phy)
2157 {
2158 struct mt7915_dev *dev = phy->dev;
2159 bool ext_phy = phy != &dev->phy;
2160 u32 trb;
2161
2162 if (!phy->omac_mask)
2163 return;
2164
2165 /* In rare cases, TRB pointers might be out of sync leads to RMAC
2166 * stopping Rx, so check status periodically to see if TRB hardware
2167 * requires minimal recovery.
2168 */
2169 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->band_idx));
2170
2171 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) !=
2172 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) &&
2173 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) !=
2174 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) &&
2175 trb == phy->trb_ts)
2176 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT,
2177 ext_phy);
2178
2179 phy->trb_ts = trb;
2180 }
2181
mt7915_mac_sta_rc_work(struct work_struct * work)2182 void mt7915_mac_sta_rc_work(struct work_struct *work)
2183 {
2184 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
2185 struct ieee80211_sta *sta;
2186 struct ieee80211_vif *vif;
2187 struct mt7915_sta *msta;
2188 u32 changed;
2189 LIST_HEAD(list);
2190
2191 spin_lock_bh(&dev->sta_poll_lock);
2192 list_splice_init(&dev->sta_rc_list, &list);
2193
2194 while (!list_empty(&list)) {
2195 msta = list_first_entry(&list, struct mt7915_sta, rc_list);
2196 list_del_init(&msta->rc_list);
2197 changed = msta->changed;
2198 msta->changed = 0;
2199 spin_unlock_bh(&dev->sta_poll_lock);
2200
2201 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
2202 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
2203
2204 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
2205 IEEE80211_RC_NSS_CHANGED |
2206 IEEE80211_RC_BW_CHANGED))
2207 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true);
2208
2209 if (changed & IEEE80211_RC_SMPS_CHANGED)
2210 mt7915_mcu_add_smps(dev, vif, sta);
2211
2212 spin_lock_bh(&dev->sta_poll_lock);
2213 }
2214
2215 spin_unlock_bh(&dev->sta_poll_lock);
2216 }
2217
mt7915_mac_work(struct work_struct * work)2218 void mt7915_mac_work(struct work_struct *work)
2219 {
2220 struct mt7915_phy *phy;
2221 struct mt76_phy *mphy;
2222
2223 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
2224 mac_work.work);
2225 phy = mphy->priv;
2226
2227 mutex_lock(&mphy->dev->mutex);
2228
2229 mt76_update_survey(mphy);
2230 if (++mphy->mac_work_count == 5) {
2231 mphy->mac_work_count = 0;
2232
2233 mt7915_mac_update_stats(phy);
2234 mt7915_mac_severe_check(phy);
2235 }
2236
2237 mutex_unlock(&mphy->dev->mutex);
2238
2239 mt76_tx_status_check(mphy->dev, false);
2240
2241 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
2242 MT7915_WATCHDOG_TIME);
2243 }
2244
mt7915_dfs_stop_radar_detector(struct mt7915_phy * phy)2245 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
2246 {
2247 struct mt7915_dev *dev = phy->dev;
2248
2249 if (phy->rdd_state & BIT(0))
2250 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0,
2251 MT_RX_SEL0, 0);
2252 if (phy->rdd_state & BIT(1))
2253 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1,
2254 MT_RX_SEL0, 0);
2255 }
2256
mt7915_dfs_start_rdd(struct mt7915_dev * dev,int chain)2257 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
2258 {
2259 int err, region;
2260
2261 switch (dev->mt76.region) {
2262 case NL80211_DFS_ETSI:
2263 region = 0;
2264 break;
2265 case NL80211_DFS_JP:
2266 region = 2;
2267 break;
2268 case NL80211_DFS_FCC:
2269 default:
2270 region = 1;
2271 break;
2272 }
2273
2274 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain,
2275 MT_RX_SEL0, region);
2276 if (err < 0)
2277 return err;
2278
2279 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain,
2280 MT_RX_SEL0, 1);
2281 }
2282
mt7915_dfs_start_radar_detector(struct mt7915_phy * phy)2283 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
2284 {
2285 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2286 struct mt7915_dev *dev = phy->dev;
2287 int err;
2288
2289 /* start CAC */
2290 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, phy->band_idx,
2291 MT_RX_SEL0, 0);
2292 if (err < 0)
2293 return err;
2294
2295 err = mt7915_dfs_start_rdd(dev, phy->band_idx);
2296 if (err < 0)
2297 return err;
2298
2299 phy->rdd_state |= BIT(phy->band_idx);
2300
2301 if (!is_mt7915(&dev->mt76))
2302 return 0;
2303
2304 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2305 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2306 err = mt7915_dfs_start_rdd(dev, 1);
2307 if (err < 0)
2308 return err;
2309
2310 phy->rdd_state |= BIT(1);
2311 }
2312
2313 return 0;
2314 }
2315
2316 static int
mt7915_dfs_init_radar_specs(struct mt7915_phy * phy)2317 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
2318 {
2319 const struct mt7915_dfs_radar_spec *radar_specs;
2320 struct mt7915_dev *dev = phy->dev;
2321 int err, i;
2322
2323 switch (dev->mt76.region) {
2324 case NL80211_DFS_FCC:
2325 radar_specs = &fcc_radar_specs;
2326 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
2327 if (err < 0)
2328 return err;
2329 break;
2330 case NL80211_DFS_ETSI:
2331 radar_specs = &etsi_radar_specs;
2332 break;
2333 case NL80211_DFS_JP:
2334 radar_specs = &jp_radar_specs;
2335 break;
2336 default:
2337 return -EINVAL;
2338 }
2339
2340 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2341 err = mt7915_mcu_set_radar_th(dev, i,
2342 &radar_specs->radar_pattern[i]);
2343 if (err < 0)
2344 return err;
2345 }
2346
2347 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2348 }
2349
mt7915_dfs_init_radar_detector(struct mt7915_phy * phy)2350 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
2351 {
2352 struct mt7915_dev *dev = phy->dev;
2353 enum mt76_dfs_state dfs_state, prev_state;
2354 int err;
2355
2356 prev_state = phy->mt76->dfs_state;
2357 dfs_state = mt76_phy_dfs_state(phy->mt76);
2358
2359 if (prev_state == dfs_state)
2360 return 0;
2361
2362 if (prev_state == MT_DFS_STATE_UNKNOWN)
2363 mt7915_dfs_stop_radar_detector(phy);
2364
2365 if (dfs_state == MT_DFS_STATE_DISABLED)
2366 goto stop;
2367
2368 if (prev_state <= MT_DFS_STATE_DISABLED) {
2369 err = mt7915_dfs_init_radar_specs(phy);
2370 if (err < 0)
2371 return err;
2372
2373 err = mt7915_dfs_start_radar_detector(phy);
2374 if (err < 0)
2375 return err;
2376
2377 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
2378 }
2379
2380 if (dfs_state == MT_DFS_STATE_CAC)
2381 return 0;
2382
2383 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END,
2384 phy->band_idx, MT_RX_SEL0, 0);
2385 if (err < 0) {
2386 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
2387 return err;
2388 }
2389
2390 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
2391 return 0;
2392
2393 stop:
2394 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START,
2395 phy->band_idx, MT_RX_SEL0, 0);
2396 if (err < 0)
2397 return err;
2398
2399 mt7915_dfs_stop_radar_detector(phy);
2400 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
2401
2402 return 0;
2403 }
2404
2405 static int
mt7915_mac_twt_duration_align(int duration)2406 mt7915_mac_twt_duration_align(int duration)
2407 {
2408 return duration << 8;
2409 }
2410
2411 static u64
mt7915_mac_twt_sched_list_add(struct mt7915_dev * dev,struct mt7915_twt_flow * flow)2412 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev,
2413 struct mt7915_twt_flow *flow)
2414 {
2415 struct mt7915_twt_flow *iter, *iter_next;
2416 u32 duration = flow->duration << 8;
2417 u64 start_tsf;
2418
2419 iter = list_first_entry_or_null(&dev->twt_list,
2420 struct mt7915_twt_flow, list);
2421 if (!iter || !iter->sched || iter->start_tsf > duration) {
2422 /* add flow as first entry in the list */
2423 list_add(&flow->list, &dev->twt_list);
2424 return 0;
2425 }
2426
2427 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) {
2428 start_tsf = iter->start_tsf +
2429 mt7915_mac_twt_duration_align(iter->duration);
2430 if (list_is_last(&iter->list, &dev->twt_list))
2431 break;
2432
2433 if (!iter_next->sched ||
2434 iter_next->start_tsf > start_tsf + duration) {
2435 list_add(&flow->list, &iter->list);
2436 goto out;
2437 }
2438 }
2439
2440 /* add flow as last entry in the list */
2441 list_add_tail(&flow->list, &dev->twt_list);
2442 out:
2443 return start_tsf;
2444 }
2445
mt7915_mac_check_twt_req(struct ieee80211_twt_setup * twt)2446 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt)
2447 {
2448 struct ieee80211_twt_params *twt_agrt;
2449 u64 interval, duration;
2450 u16 mantissa;
2451 u8 exp;
2452
2453 /* only individual agreement supported */
2454 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST)
2455 return -EOPNOTSUPP;
2456
2457 /* only 256us unit supported */
2458 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT)
2459 return -EOPNOTSUPP;
2460
2461 twt_agrt = (struct ieee80211_twt_params *)twt->params;
2462
2463 /* explicit agreement not supported */
2464 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT)))
2465 return -EOPNOTSUPP;
2466
2467 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP,
2468 le16_to_cpu(twt_agrt->req_type));
2469 mantissa = le16_to_cpu(twt_agrt->mantissa);
2470 duration = twt_agrt->min_twt_dur << 8;
2471
2472 interval = (u64)mantissa << exp;
2473 if (interval < duration)
2474 return -EOPNOTSUPP;
2475
2476 return 0;
2477 }
2478
2479 static bool
mt7915_mac_twt_param_equal(struct mt7915_sta * msta,struct ieee80211_twt_params * twt_agrt)2480 mt7915_mac_twt_param_equal(struct mt7915_sta *msta,
2481 struct ieee80211_twt_params *twt_agrt)
2482 {
2483 u16 type = le16_to_cpu(twt_agrt->req_type);
2484 u8 exp;
2485 int i;
2486
2487 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type);
2488 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) {
2489 struct mt7915_twt_flow *f;
2490
2491 if (!(msta->twt.flowid_mask & BIT(i)))
2492 continue;
2493
2494 f = &msta->twt.flow[i];
2495 if (f->duration == twt_agrt->min_twt_dur &&
2496 f->mantissa == twt_agrt->mantissa &&
2497 f->exp == exp &&
2498 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) &&
2499 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) &&
2500 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER))
2501 return true;
2502 }
2503
2504 return false;
2505 }
2506
mt7915_mac_add_twt_setup(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct ieee80211_twt_setup * twt)2507 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
2508 struct ieee80211_sta *sta,
2509 struct ieee80211_twt_setup *twt)
2510 {
2511 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT;
2512 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
2513 struct ieee80211_twt_params *twt_agrt = (void *)twt->params;
2514 u16 req_type = le16_to_cpu(twt_agrt->req_type);
2515 enum ieee80211_twt_setup_cmd sta_setup_cmd;
2516 struct mt7915_dev *dev = mt7915_hw_dev(hw);
2517 struct mt7915_twt_flow *flow;
2518 int flowid, table_id;
2519 u8 exp;
2520
2521 if (mt7915_mac_check_twt_req(twt))
2522 goto out;
2523
2524 mutex_lock(&dev->mt76.mutex);
2525
2526 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT)
2527 goto unlock;
2528
2529 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow))
2530 goto unlock;
2531
2532 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) {
2533 setup_cmd = TWT_SETUP_CMD_DICTATE;
2534 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR;
2535 goto unlock;
2536 }
2537
2538 flowid = ffs(~msta->twt.flowid_mask) - 1;
2539 le16p_replace_bits(&twt_agrt->req_type, flowid,
2540 IEEE80211_TWT_REQTYPE_FLOWID);
2541
2542 table_id = ffs(~dev->twt.table_mask) - 1;
2543 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type);
2544 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type);
2545
2546 if (mt7915_mac_twt_param_equal(msta, twt_agrt))
2547 goto unlock;
2548
2549 flow = &msta->twt.flow[flowid];
2550 memset(flow, 0, sizeof(*flow));
2551 INIT_LIST_HEAD(&flow->list);
2552 flow->wcid = msta->wcid.idx;
2553 flow->table_id = table_id;
2554 flow->id = flowid;
2555 flow->duration = twt_agrt->min_twt_dur;
2556 flow->mantissa = twt_agrt->mantissa;
2557 flow->exp = exp;
2558 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION);
2559 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE);
2560 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER);
2561
2562 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST ||
2563 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) {
2564 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp;
2565 u64 flow_tsf, curr_tsf;
2566 u32 rem;
2567
2568 flow->sched = true;
2569 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow);
2570 curr_tsf = __mt7915_get_tsf(hw, msta->vif);
2571 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem);
2572 flow_tsf = curr_tsf + interval - rem;
2573 twt_agrt->twt = cpu_to_le64(flow_tsf);
2574 } else {
2575 list_add_tail(&flow->list, &dev->twt_list);
2576 }
2577 flow->tsf = le64_to_cpu(twt_agrt->twt);
2578
2579 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD))
2580 goto unlock;
2581
2582 setup_cmd = TWT_SETUP_CMD_ACCEPT;
2583 dev->twt.table_mask |= BIT(table_id);
2584 msta->twt.flowid_mask |= BIT(flowid);
2585 dev->twt.n_agrt++;
2586
2587 unlock:
2588 mutex_unlock(&dev->mt76.mutex);
2589 out:
2590 le16p_replace_bits(&twt_agrt->req_type, setup_cmd,
2591 IEEE80211_TWT_REQTYPE_SETUP_CMD);
2592 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) |
2593 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED);
2594 }
2595
mt7915_mac_twt_teardown_flow(struct mt7915_dev * dev,struct mt7915_sta * msta,u8 flowid)2596 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
2597 struct mt7915_sta *msta,
2598 u8 flowid)
2599 {
2600 struct mt7915_twt_flow *flow;
2601
2602 lockdep_assert_held(&dev->mt76.mutex);
2603
2604 if (flowid >= ARRAY_SIZE(msta->twt.flow))
2605 return;
2606
2607 if (!(msta->twt.flowid_mask & BIT(flowid)))
2608 return;
2609
2610 flow = &msta->twt.flow[flowid];
2611 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow,
2612 MCU_TWT_AGRT_DELETE))
2613 return;
2614
2615 list_del_init(&flow->list);
2616 msta->twt.flowid_mask &= ~BIT(flowid);
2617 dev->twt.table_mask &= ~BIT(flow->table_id);
2618 dev->twt.n_agrt--;
2619 }
2620