1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 
3 /* MDIO support for Mellanox Gigabit Ethernet driver
4  *
5  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
6  */
7 
8 #include <linux/acpi.h>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/ioport.h>
16 #include <linux/irqreturn.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 
24 #include "mlxbf_gige.h"
25 #include "mlxbf_gige_regs.h"
26 
27 #define MLXBF_GIGE_MDIO_GW_OFFSET	0x0
28 #define MLXBF_GIGE_MDIO_CFG_OFFSET	0x4
29 
30 #define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
31 #define MLXBF_GIGE_MDIO_COREPLL_CONST  16384ULL
32 #define MLXBF_GIGE_MDC_CLK_NS          400
33 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4
34 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8
35 #define MLXBF_GIGE_MDIO_CORE_F_SHIFT   0
36 #define MLXBF_GIGE_MDIO_CORE_F_MASK    GENMASK(25, 0)
37 #define MLXBF_GIGE_MDIO_CORE_R_SHIFT   26
38 #define MLXBF_GIGE_MDIO_CORE_R_MASK    GENMASK(31, 26)
39 #define MLXBF_GIGE_MDIO_CORE_OD_SHIFT  0
40 #define MLXBF_GIGE_MDIO_CORE_OD_MASK   GENMASK(3, 0)
41 
42 /* Support clause 22 */
43 #define MLXBF_GIGE_MDIO_CL22_ST1	0x1
44 #define MLXBF_GIGE_MDIO_CL22_WRITE	0x1
45 #define MLXBF_GIGE_MDIO_CL22_READ	0x2
46 
47 /* Busy bit is set by software and cleared by hardware */
48 #define MLXBF_GIGE_MDIO_SET_BUSY	0x1
49 
50 /* MDIO GW register bits */
51 #define MLXBF_GIGE_MDIO_GW_AD_MASK	GENMASK(15, 0)
52 #define MLXBF_GIGE_MDIO_GW_DEVAD_MASK	GENMASK(20, 16)
53 #define MLXBF_GIGE_MDIO_GW_PARTAD_MASK	GENMASK(25, 21)
54 #define MLXBF_GIGE_MDIO_GW_OPCODE_MASK	GENMASK(27, 26)
55 #define MLXBF_GIGE_MDIO_GW_ST1_MASK	GENMASK(28, 28)
56 #define MLXBF_GIGE_MDIO_GW_BUSY_MASK	GENMASK(30, 30)
57 
58 /* MDIO config register bits */
59 #define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK		GENMASK(1, 0)
60 #define MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK		GENMASK(2, 2)
61 #define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK	GENMASK(4, 4)
62 #define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK		GENMASK(15, 8)
63 #define MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK		GENMASK(23, 16)
64 #define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK		GENMASK(31, 24)
65 
66 #define MLXBF_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
67 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
68 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
69 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
70 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
71 
72 #define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30
73 #define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c
74 
75 static struct resource corepll_params[] = {
76 	[MLXBF_GIGE_VERSION_BF2] = {
77 		.start = MLXBF_GIGE_BF2_COREPLL_ADDR,
78 		.end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1,
79 		.name = "COREPLL_RES"
80 	},
81 };
82 
83 /* Returns core clock i1clk in Hz */
calculate_i1clk(struct mlxbf_gige * priv)84 static u64 calculate_i1clk(struct mlxbf_gige *priv)
85 {
86 	u8 core_od, core_r;
87 	u64 freq_output;
88 	u32 reg1, reg2;
89 	u32 core_f;
90 
91 	reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1);
92 	reg2 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2);
93 
94 	core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >>
95 		MLXBF_GIGE_MDIO_CORE_F_SHIFT;
96 	core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >>
97 		MLXBF_GIGE_MDIO_CORE_R_SHIFT;
98 	core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >>
99 		MLXBF_GIGE_MDIO_CORE_OD_SHIFT;
100 
101 	/* Compute PLL output frequency as follow:
102 	 *
103 	 *                                     CORE_F / 16384
104 	 * freq_output = freq_reference * ----------------------------
105 	 *                              (CORE_R + 1) * (CORE_OD + 1)
106 	 */
107 	freq_output = div_u64((MLXBF_GIGE_MDIO_FREQ_REFERENCE * core_f),
108 			      MLXBF_GIGE_MDIO_COREPLL_CONST);
109 	freq_output = div_u64(freq_output, (core_r + 1) * (core_od + 1));
110 
111 	return freq_output;
112 }
113 
114 /* Formula for encoding the MDIO period. The encoded value is
115  * passed to the MDIO config register.
116  *
117  * mdc_clk = 2*(val + 1)*(core clock in sec)
118  *
119  * i1clk is in Hz:
120  * 400 ns = 2*(val + 1)*(1/i1clk)
121  *
122  * val = (((400/10^9) / (1/i1clk) / 2) - 1)
123  * val = (400/2 * i1clk)/10^9 - 1
124  */
mdio_period_map(struct mlxbf_gige * priv)125 static u8 mdio_period_map(struct mlxbf_gige *priv)
126 {
127 	u8 mdio_period;
128 	u64 i1clk;
129 
130 	i1clk = calculate_i1clk(priv);
131 
132 	mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
133 
134 	return mdio_period;
135 }
136 
mlxbf_gige_mdio_create_cmd(u16 data,int phy_add,int phy_reg,u32 opcode)137 static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
138 				      int phy_reg, u32 opcode)
139 {
140 	u32 gw_reg = 0;
141 
142 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data);
143 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg);
144 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add);
145 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode);
146 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_ST1_MASK,
147 			     MLXBF_GIGE_MDIO_CL22_ST1);
148 	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_BUSY_MASK,
149 			     MLXBF_GIGE_MDIO_SET_BUSY);
150 
151 	return gw_reg;
152 }
153 
mlxbf_gige_mdio_read(struct mii_bus * bus,int phy_add,int phy_reg)154 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
155 {
156 	struct mlxbf_gige *priv = bus->priv;
157 	u32 cmd;
158 	int ret;
159 	u32 val;
160 
161 	if (phy_reg & MII_ADDR_C45)
162 		return -EOPNOTSUPP;
163 
164 	/* Send mdio read request */
165 	cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ);
166 
167 	writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
168 
169 	ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
170 					val, !(val & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
171 					5, 1000000);
172 
173 	if (ret) {
174 		writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
175 		return ret;
176 	}
177 
178 	ret = readl(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
179 	/* Only return ad bits of the gw register */
180 	ret &= MLXBF_GIGE_MDIO_GW_AD_MASK;
181 
182 	return ret;
183 }
184 
mlxbf_gige_mdio_write(struct mii_bus * bus,int phy_add,int phy_reg,u16 val)185 static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
186 				 int phy_reg, u16 val)
187 {
188 	struct mlxbf_gige *priv = bus->priv;
189 	u32 temp;
190 	u32 cmd;
191 	int ret;
192 
193 	if (phy_reg & MII_ADDR_C45)
194 		return -EOPNOTSUPP;
195 
196 	/* Send mdio write request */
197 	cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg,
198 					 MLXBF_GIGE_MDIO_CL22_WRITE);
199 	writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
200 
201 	/* If the poll timed out, drop the request */
202 	ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
203 					temp, !(temp & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
204 					5, 1000000);
205 
206 	return ret;
207 }
208 
mlxbf_gige_mdio_cfg(struct mlxbf_gige * priv)209 static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv)
210 {
211 	u8 mdio_period;
212 	u32 val;
213 
214 	mdio_period = mdio_period_map(priv);
215 
216 	val = MLXBF_GIGE_MDIO_CFG_VAL;
217 	val |= FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
218 	writel(val, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
219 }
220 
mlxbf_gige_mdio_probe(struct platform_device * pdev,struct mlxbf_gige * priv)221 int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
222 {
223 	struct device *dev = &pdev->dev;
224 	struct resource *res;
225 	int ret;
226 
227 	priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
228 	if (IS_ERR(priv->mdio_io))
229 		return PTR_ERR(priv->mdio_io);
230 
231 	/* clk resource shared with other drivers so cannot use
232 	 * devm_platform_ioremap_resource
233 	 */
234 	res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK);
235 	if (!res) {
236 		/* For backward compatibility with older ACPI tables, also keep
237 		 * CLK resource internal to the driver.
238 		 */
239 		res = &corepll_params[MLXBF_GIGE_VERSION_BF2];
240 	}
241 
242 	priv->clk_io = devm_ioremap(dev, res->start, resource_size(res));
243 	if (IS_ERR(priv->clk_io))
244 		return PTR_ERR(priv->clk_io);
245 
246 	mlxbf_gige_mdio_cfg(priv);
247 
248 	priv->mdiobus = devm_mdiobus_alloc(dev);
249 	if (!priv->mdiobus) {
250 		dev_err(dev, "Failed to alloc MDIO bus\n");
251 		return -ENOMEM;
252 	}
253 
254 	priv->mdiobus->name = "mlxbf-mdio";
255 	priv->mdiobus->read = mlxbf_gige_mdio_read;
256 	priv->mdiobus->write = mlxbf_gige_mdio_write;
257 	priv->mdiobus->parent = dev;
258 	priv->mdiobus->priv = priv;
259 	snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "%s",
260 		 dev_name(dev));
261 
262 	ret = mdiobus_register(priv->mdiobus);
263 	if (ret)
264 		dev_err(dev, "Failed to register MDIO bus\n");
265 
266 	return ret;
267 }
268 
mlxbf_gige_mdio_remove(struct mlxbf_gige * priv)269 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
270 {
271 	mdiobus_unregister(priv->mdiobus);
272 }
273