1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16
17 #include <linux/pm_domain.h>
18 #include <linux/pm_runtime.h>
19
20 #include <linux/mei.h>
21
22 #include "mei_dev.h"
23 #include "client.h"
24 #include "hw-me-regs.h"
25 #include "hw-me.h"
26
27 /* mei_pci_tbl - PCI Device ID Table */
28 static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
120
121 /* required last entry */
122 {0, }
123 };
124
125 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
126
127 #ifdef CONFIG_PM
128 static inline void mei_me_set_pm_domain(struct mei_device *dev);
129 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
130 #else
mei_me_set_pm_domain(struct mei_device * dev)131 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)132 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
133 #endif /* CONFIG_PM */
134
mei_me_read_fws(const struct mei_device * dev,int where,u32 * val)135 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
136 {
137 struct pci_dev *pdev = to_pci_dev(dev->dev);
138
139 return pci_read_config_dword(pdev, where, val);
140 }
141
142 /**
143 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
144 *
145 * @pdev: PCI device structure
146 * @cfg: per generation config
147 *
148 * Return: true if ME Interface is valid, false otherwise
149 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)150 static bool mei_me_quirk_probe(struct pci_dev *pdev,
151 const struct mei_cfg *cfg)
152 {
153 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
154 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
155 return false;
156 }
157
158 return true;
159 }
160
161 /**
162 * mei_me_probe - Device Initialization Routine
163 *
164 * @pdev: PCI device structure
165 * @ent: entry in kcs_pci_tbl
166 *
167 * Return: 0 on success, <0 on failure.
168 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)169 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
170 {
171 const struct mei_cfg *cfg;
172 struct mei_device *dev;
173 struct mei_me_hw *hw;
174 unsigned int irqflags;
175 int err;
176
177 cfg = mei_me_get_cfg(ent->driver_data);
178 if (!cfg)
179 return -ENODEV;
180
181 if (!mei_me_quirk_probe(pdev, cfg))
182 return -ENODEV;
183
184 /* enable pci dev */
185 err = pcim_enable_device(pdev);
186 if (err) {
187 dev_err(&pdev->dev, "failed to enable pci device.\n");
188 goto end;
189 }
190 /* set PCI host mastering */
191 pci_set_master(pdev);
192 /* pci request regions and mapping IO device memory for mei driver */
193 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
194 if (err) {
195 dev_err(&pdev->dev, "failed to get pci regions.\n");
196 goto end;
197 }
198
199 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
200 if (err) {
201 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
202 goto end;
203 }
204
205 /* allocates and initializes the mei dev structure */
206 dev = mei_me_dev_init(&pdev->dev, cfg);
207 if (!dev) {
208 err = -ENOMEM;
209 goto end;
210 }
211 hw = to_me_hw(dev);
212 hw->mem_addr = pcim_iomap_table(pdev)[0];
213 hw->read_fws = mei_me_read_fws;
214
215 pci_enable_msi(pdev);
216
217 hw->irq = pdev->irq;
218
219 /* request and enable interrupt */
220 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
221
222 err = request_threaded_irq(pdev->irq,
223 mei_me_irq_quick_handler,
224 mei_me_irq_thread_handler,
225 irqflags, KBUILD_MODNAME, dev);
226 if (err) {
227 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
228 pdev->irq);
229 goto end;
230 }
231
232 if (mei_start(dev)) {
233 dev_err(&pdev->dev, "init hw failure.\n");
234 err = -ENODEV;
235 goto release_irq;
236 }
237
238 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
239 pm_runtime_use_autosuspend(&pdev->dev);
240
241 err = mei_register(dev, &pdev->dev);
242 if (err)
243 goto stop;
244
245 pci_set_drvdata(pdev, dev);
246
247 /*
248 * MEI requires to resume from runtime suspend mode
249 * in order to perform link reset flow upon system suspend.
250 */
251 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
252
253 /*
254 * ME maps runtime suspend/resume to D0i states,
255 * hence we need to go around native PCI runtime service which
256 * eventually brings the device into D3cold/hot state,
257 * but the mei device cannot wake up from D3 unlike from D0i3.
258 * To get around the PCI device native runtime pm,
259 * ME uses runtime pm domain handlers which take precedence
260 * over the driver's pm handlers.
261 */
262 mei_me_set_pm_domain(dev);
263
264 if (mei_pg_is_enabled(dev)) {
265 pm_runtime_put_noidle(&pdev->dev);
266 if (hw->d0i3_supported)
267 pm_runtime_allow(&pdev->dev);
268 }
269
270 dev_dbg(&pdev->dev, "initialization successful.\n");
271
272 return 0;
273
274 stop:
275 mei_stop(dev);
276 release_irq:
277 mei_cancel_work(dev);
278 mei_disable_interrupts(dev);
279 free_irq(pdev->irq, dev);
280 end:
281 dev_err(&pdev->dev, "initialization failed.\n");
282 return err;
283 }
284
285 /**
286 * mei_me_shutdown - Device Removal Routine
287 *
288 * @pdev: PCI device structure
289 *
290 * mei_me_shutdown is called from the reboot notifier
291 * it's a simplified version of remove so we go down
292 * faster.
293 */
mei_me_shutdown(struct pci_dev * pdev)294 static void mei_me_shutdown(struct pci_dev *pdev)
295 {
296 struct mei_device *dev;
297
298 dev = pci_get_drvdata(pdev);
299 if (!dev)
300 return;
301
302 dev_dbg(&pdev->dev, "shutdown\n");
303 mei_stop(dev);
304
305 mei_me_unset_pm_domain(dev);
306
307 mei_disable_interrupts(dev);
308 free_irq(pdev->irq, dev);
309 }
310
311 /**
312 * mei_me_remove - Device Removal Routine
313 *
314 * @pdev: PCI device structure
315 *
316 * mei_me_remove is called by the PCI subsystem to alert the driver
317 * that it should release a PCI device.
318 */
mei_me_remove(struct pci_dev * pdev)319 static void mei_me_remove(struct pci_dev *pdev)
320 {
321 struct mei_device *dev;
322
323 dev = pci_get_drvdata(pdev);
324 if (!dev)
325 return;
326
327 if (mei_pg_is_enabled(dev))
328 pm_runtime_get_noresume(&pdev->dev);
329
330 dev_dbg(&pdev->dev, "stop\n");
331 mei_stop(dev);
332
333 mei_me_unset_pm_domain(dev);
334
335 mei_disable_interrupts(dev);
336
337 free_irq(pdev->irq, dev);
338
339 mei_deregister(dev);
340 }
341
342 #ifdef CONFIG_PM_SLEEP
mei_me_pci_suspend(struct device * device)343 static int mei_me_pci_suspend(struct device *device)
344 {
345 struct pci_dev *pdev = to_pci_dev(device);
346 struct mei_device *dev = pci_get_drvdata(pdev);
347
348 if (!dev)
349 return -ENODEV;
350
351 dev_dbg(&pdev->dev, "suspend\n");
352
353 mei_stop(dev);
354
355 mei_disable_interrupts(dev);
356
357 free_irq(pdev->irq, dev);
358 pci_disable_msi(pdev);
359
360 return 0;
361 }
362
mei_me_pci_resume(struct device * device)363 static int mei_me_pci_resume(struct device *device)
364 {
365 struct pci_dev *pdev = to_pci_dev(device);
366 struct mei_device *dev;
367 unsigned int irqflags;
368 int err;
369
370 dev = pci_get_drvdata(pdev);
371 if (!dev)
372 return -ENODEV;
373
374 pci_enable_msi(pdev);
375
376 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
377
378 /* request and enable interrupt */
379 err = request_threaded_irq(pdev->irq,
380 mei_me_irq_quick_handler,
381 mei_me_irq_thread_handler,
382 irqflags, KBUILD_MODNAME, dev);
383
384 if (err) {
385 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
386 pdev->irq);
387 return err;
388 }
389
390 err = mei_restart(dev);
391 if (err)
392 return err;
393
394 /* Start timer if stopped in suspend */
395 schedule_delayed_work(&dev->timer_work, HZ);
396
397 return 0;
398 }
399 #endif /* CONFIG_PM_SLEEP */
400
401 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)402 static int mei_me_pm_runtime_idle(struct device *device)
403 {
404 struct mei_device *dev;
405
406 dev_dbg(device, "rpm: me: runtime_idle\n");
407
408 dev = dev_get_drvdata(device);
409 if (!dev)
410 return -ENODEV;
411 if (mei_write_is_idle(dev))
412 pm_runtime_autosuspend(device);
413
414 return -EBUSY;
415 }
416
mei_me_pm_runtime_suspend(struct device * device)417 static int mei_me_pm_runtime_suspend(struct device *device)
418 {
419 struct mei_device *dev;
420 int ret;
421
422 dev_dbg(device, "rpm: me: runtime suspend\n");
423
424 dev = dev_get_drvdata(device);
425 if (!dev)
426 return -ENODEV;
427
428 mutex_lock(&dev->device_lock);
429
430 if (mei_write_is_idle(dev))
431 ret = mei_me_pg_enter_sync(dev);
432 else
433 ret = -EAGAIN;
434
435 mutex_unlock(&dev->device_lock);
436
437 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
438
439 if (ret && ret != -EAGAIN)
440 schedule_work(&dev->reset_work);
441
442 return ret;
443 }
444
mei_me_pm_runtime_resume(struct device * device)445 static int mei_me_pm_runtime_resume(struct device *device)
446 {
447 struct mei_device *dev;
448 int ret;
449
450 dev_dbg(device, "rpm: me: runtime resume\n");
451
452 dev = dev_get_drvdata(device);
453 if (!dev)
454 return -ENODEV;
455
456 mutex_lock(&dev->device_lock);
457
458 ret = mei_me_pg_exit_sync(dev);
459
460 mutex_unlock(&dev->device_lock);
461
462 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
463
464 if (ret)
465 schedule_work(&dev->reset_work);
466
467 return ret;
468 }
469
470 /**
471 * mei_me_set_pm_domain - fill and set pm domain structure for device
472 *
473 * @dev: mei_device
474 */
mei_me_set_pm_domain(struct mei_device * dev)475 static inline void mei_me_set_pm_domain(struct mei_device *dev)
476 {
477 struct pci_dev *pdev = to_pci_dev(dev->dev);
478
479 if (pdev->dev.bus && pdev->dev.bus->pm) {
480 dev->pg_domain.ops = *pdev->dev.bus->pm;
481
482 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
483 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
484 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
485
486 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
487 }
488 }
489
490 /**
491 * mei_me_unset_pm_domain - clean pm domain structure for device
492 *
493 * @dev: mei_device
494 */
mei_me_unset_pm_domain(struct mei_device * dev)495 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
496 {
497 /* stop using pm callbacks if any */
498 dev_pm_domain_set(dev->dev, NULL);
499 }
500
501 static const struct dev_pm_ops mei_me_pm_ops = {
502 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
503 mei_me_pci_resume)
504 SET_RUNTIME_PM_OPS(
505 mei_me_pm_runtime_suspend,
506 mei_me_pm_runtime_resume,
507 mei_me_pm_runtime_idle)
508 };
509
510 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
511 #else
512 #define MEI_ME_PM_OPS NULL
513 #endif /* CONFIG_PM */
514 /*
515 * PCI driver structure
516 */
517 static struct pci_driver mei_me_driver = {
518 .name = KBUILD_MODNAME,
519 .id_table = mei_me_pci_tbl,
520 .probe = mei_me_probe,
521 .remove = mei_me_remove,
522 .shutdown = mei_me_shutdown,
523 .driver.pm = MEI_ME_PM_OPS,
524 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
525 };
526
527 module_pci_driver(mei_me_driver);
528
529 MODULE_AUTHOR("Intel Corporation");
530 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
531 MODULE_LICENSE("GPL v2");
532