1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #ifndef MLX5_IB_H
8 #define MLX5_IB_H
9
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <rdma/ib_verbs.h>
13 #include <rdma/ib_umem.h>
14 #include <rdma/ib_smi.h>
15 #include <linux/mlx5/driver.h>
16 #include <linux/mlx5/cq.h>
17 #include <linux/mlx5/fs.h>
18 #include <linux/mlx5/qp.h>
19 #include <linux/types.h>
20 #include <linux/mlx5/transobj.h>
21 #include <rdma/ib_user_verbs.h>
22 #include <rdma/mlx5-abi.h>
23 #include <rdma/uverbs_ioctl.h>
24 #include <rdma/mlx5_user_ioctl_cmds.h>
25 #include <rdma/mlx5_user_ioctl_verbs.h>
26
27 #include "srq.h"
28
29 #define mlx5_ib_dbg(_dev, format, arg...) \
30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
31 __LINE__, current->pid, ##arg)
32
33 #define mlx5_ib_err(_dev, format, arg...) \
34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
35 __LINE__, current->pid, ##arg)
36
37 #define mlx5_ib_warn(_dev, format, arg...) \
38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
39 __LINE__, current->pid, ##arg)
40
41 #define MLX5_IB_DEFAULT_UIDX 0xffffff
42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
43
44 static __always_inline unsigned long
__mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,unsigned int pgsz_shift)45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,
46 unsigned int pgsz_shift)
47 {
48 unsigned int largest_pg_shift =
49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift,
50 BITS_PER_LONG - 1);
51
52 /*
53 * Despite a command allowing it, the device does not support lower than
54 * 4k page size.
55 */
56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift);
57 return GENMASK(largest_pg_shift, pgsz_shift);
58 }
59
60 /*
61 * For mkc users, instead of a page_offset the command has a start_iova which
62 * specifies both the page_offset and the on-the-wire IOVA
63 */
64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \
65 ib_umem_find_best_pgsz(umem, \
66 __mlx5_log_page_size_to_bitmap( \
67 __mlx5_bit_sz(typ, log_pgsz_fld), \
68 pgsz_shift), \
69 iova)
70
71 static __always_inline unsigned long
__mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,unsigned int offset_shift)72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,
73 unsigned int offset_shift)
74 {
75 unsigned int largest_offset_shift =
76 min_t(unsigned long, page_offset_bits - 1 + offset_shift,
77 BITS_PER_LONG - 1);
78
79 return GENMASK(largest_offset_shift, offset_shift);
80 }
81
82 /*
83 * QP/CQ/WQ/etc type commands take a page offset that satisifies:
84 * page_offset_quantized * (page_size/scale) = page_offset
85 * Which restricts allowed page sizes to ones that satisify the above.
86 */
87 unsigned long __mlx5_umem_find_best_quantized_pgoff(
88 struct ib_umem *umem, unsigned long pgsz_bitmap,
89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
90 unsigned int *page_offset_quantized);
91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \
92 pgsz_shift, page_offset_fld, \
93 scale, page_offset_quantized) \
94 __mlx5_umem_find_best_quantized_pgoff( \
95 umem, \
96 __mlx5_log_page_size_to_bitmap( \
97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
98 __mlx5_bit_sz(typ, page_offset_fld), \
99 GENMASK(31, order_base_2(scale)), scale, \
100 page_offset_quantized)
101
102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \
103 pgsz_shift, page_offset_fld, \
104 scale, page_offset_quantized) \
105 __mlx5_umem_find_best_quantized_pgoff( \
106 umem, \
107 __mlx5_log_page_size_to_bitmap( \
108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \
110 page_offset_quantized)
111
112 enum {
113 MLX5_IB_MMAP_OFFSET_START = 9,
114 MLX5_IB_MMAP_OFFSET_END = 255,
115 };
116
117 enum {
118 MLX5_IB_MMAP_CMD_SHIFT = 8,
119 MLX5_IB_MMAP_CMD_MASK = 0xff,
120 };
121
122 enum {
123 MLX5_RES_SCAT_DATA32_CQE = 0x1,
124 MLX5_RES_SCAT_DATA64_CQE = 0x2,
125 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
126 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
127 };
128
129 enum mlx5_ib_mad_ifc_flags {
130 MLX5_MAD_IFC_IGNORE_MKEY = 1,
131 MLX5_MAD_IFC_IGNORE_BKEY = 2,
132 MLX5_MAD_IFC_NET_VIEW = 4,
133 };
134
135 enum {
136 MLX5_CROSS_CHANNEL_BFREG = 0,
137 };
138
139 enum {
140 MLX5_CQE_VERSION_V0,
141 MLX5_CQE_VERSION_V1,
142 };
143
144 enum {
145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
146 MLX5_TM_MAX_SGE = 1,
147 };
148
149 enum {
150 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
151 MLX5_IB_INVALID_BFREG = BIT(31),
152 };
153
154 enum {
155 MLX5_MAX_MEMIC_PAGES = 0x100,
156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
157 };
158
159 enum {
160 MLX5_MEMIC_BASE_ALIGN = 6,
161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
162 };
163
164 enum mlx5_ib_mmap_type {
165 MLX5_IB_MMAP_TYPE_MEMIC = 1,
166 MLX5_IB_MMAP_TYPE_VAR = 2,
167 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
168 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
169 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5,
170 };
171
172 struct mlx5_bfreg_info {
173 u32 *sys_pages;
174 int num_low_latency_bfregs;
175 unsigned int *count;
176
177 /*
178 * protect bfreg allocation data structs
179 */
180 struct mutex lock;
181 u32 ver;
182 u8 lib_uar_4k : 1;
183 u8 lib_uar_dyn : 1;
184 u32 num_sys_pages;
185 u32 num_static_sys_pages;
186 u32 total_num_bfregs;
187 u32 num_dyn_bfregs;
188 };
189
190 struct mlx5_ib_ucontext {
191 struct ib_ucontext ibucontext;
192 struct list_head db_page_list;
193
194 /* protect doorbell record alloc/free
195 */
196 struct mutex db_page_mutex;
197 struct mlx5_bfreg_info bfregi;
198 u8 cqe_version;
199 /* Transport Domain number */
200 u32 tdn;
201
202 u64 lib_caps;
203 u16 devx_uid;
204 /* For RoCE LAG TX affinity */
205 atomic_t tx_port_affinity;
206 };
207
to_mucontext(struct ib_ucontext * ibucontext)208 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
209 {
210 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
211 }
212
213 struct mlx5_ib_pd {
214 struct ib_pd ibpd;
215 u32 pdn;
216 u16 uid;
217 };
218
219 enum {
220 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
221 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
222 MLX5_IB_FLOW_ACTION_DECAP,
223 };
224
225 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
226 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
227 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
228 #error "Invalid number of bypass priorities"
229 #endif
230 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
231
232 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
233 #define MLX5_IB_NUM_SNIFFER_FTS 2
234 #define MLX5_IB_NUM_EGRESS_FTS 1
235 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS
236 struct mlx5_ib_flow_prio {
237 struct mlx5_flow_table *flow_table;
238 unsigned int refcount;
239 };
240
241 struct mlx5_ib_flow_handler {
242 struct list_head list;
243 struct ib_flow ibflow;
244 struct mlx5_ib_flow_prio *prio;
245 struct mlx5_flow_handle *rule;
246 struct ib_counters *ibcounters;
247 struct mlx5_ib_dev *dev;
248 struct mlx5_ib_flow_matcher *flow_matcher;
249 };
250
251 struct mlx5_ib_flow_matcher {
252 struct mlx5_ib_match_params matcher_mask;
253 int mask_len;
254 enum mlx5_ib_flow_type flow_type;
255 enum mlx5_flow_namespace_type ns_type;
256 u16 priority;
257 struct mlx5_core_dev *mdev;
258 atomic_t usecnt;
259 u8 match_criteria_enable;
260 };
261
262 struct mlx5_ib_pp {
263 u16 index;
264 struct mlx5_core_dev *mdev;
265 };
266
267 enum mlx5_ib_optional_counter_type {
268 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS,
269 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS,
270 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS,
271
272 MLX5_IB_OPCOUNTER_MAX,
273 };
274
275 struct mlx5_ib_flow_db {
276 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
277 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
278 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
279 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
280 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS];
281 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
282 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
283 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX];
284 struct mlx5_flow_table *lag_demux_ft;
285 /* Protect flow steering bypass flow tables
286 * when add/del flow rules.
287 * only single add/removal of flow steering rule could be done
288 * simultaneously.
289 */
290 struct mutex lock;
291 };
292
293 /* Use macros here so that don't have to duplicate
294 * enum ib_qp_type for low-level driver
295 */
296
297 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
298 /*
299 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
300 * creates the actual hardware QP.
301 */
302 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
303 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
304 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
305 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
306
307 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
308 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
309 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
310 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
311 #define MLX5_IB_UPD_XLT_PD BIT(4)
312 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
313 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
314
315 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
316 *
317 * These flags are intended for internal use by the mlx5_ib driver, and they
318 * rely on the range reserved for that use in the ib_qp_create_flags enum.
319 */
320 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
321 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
322
323 struct wr_list {
324 u16 opcode;
325 u16 next;
326 };
327
328 enum mlx5_ib_rq_flags {
329 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
330 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
331 };
332
333 struct mlx5_ib_wq {
334 struct mlx5_frag_buf_ctrl fbc;
335 u64 *wrid;
336 u32 *wr_data;
337 struct wr_list *w_list;
338 unsigned *wqe_head;
339 u16 unsig_count;
340
341 /* serialize post to the work queue
342 */
343 spinlock_t lock;
344 int wqe_cnt;
345 int max_post;
346 int max_gs;
347 int offset;
348 int wqe_shift;
349 unsigned head;
350 unsigned tail;
351 u16 cur_post;
352 u16 last_poll;
353 void *cur_edge;
354 };
355
356 enum mlx5_ib_wq_flags {
357 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
358 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
359 };
360
361 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
362 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
363 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
364 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
365 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
366
367 struct mlx5_ib_rwq {
368 struct ib_wq ibwq;
369 struct mlx5_core_qp core_qp;
370 u32 rq_num_pas;
371 u32 log_rq_stride;
372 u32 log_rq_size;
373 u32 rq_page_offset;
374 u32 log_page_size;
375 u32 log_num_strides;
376 u32 two_byte_shift_en;
377 u32 single_stride_log_num_of_bytes;
378 struct ib_umem *umem;
379 size_t buf_size;
380 unsigned int page_shift;
381 struct mlx5_db db;
382 u32 user_index;
383 u32 wqe_count;
384 u32 wqe_shift;
385 int wq_sig;
386 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
387 };
388
389 struct mlx5_ib_rwq_ind_table {
390 struct ib_rwq_ind_table ib_rwq_ind_tbl;
391 u32 rqtn;
392 u16 uid;
393 };
394
395 struct mlx5_ib_ubuffer {
396 struct ib_umem *umem;
397 int buf_size;
398 u64 buf_addr;
399 };
400
401 struct mlx5_ib_qp_base {
402 struct mlx5_ib_qp *container_mibqp;
403 struct mlx5_core_qp mqp;
404 struct mlx5_ib_ubuffer ubuffer;
405 };
406
407 struct mlx5_ib_qp_trans {
408 struct mlx5_ib_qp_base base;
409 u16 xrcdn;
410 u32 alt_port;
411 u8 atomic_rd_en;
412 u8 resp_depth;
413 };
414
415 struct mlx5_ib_rss_qp {
416 u32 tirn;
417 };
418
419 struct mlx5_ib_rq {
420 struct mlx5_ib_qp_base base;
421 struct mlx5_ib_wq *rq;
422 struct mlx5_ib_ubuffer ubuffer;
423 struct mlx5_db *doorbell;
424 u32 tirn;
425 u8 state;
426 u32 flags;
427 };
428
429 struct mlx5_ib_sq {
430 struct mlx5_ib_qp_base base;
431 struct mlx5_ib_wq *sq;
432 struct mlx5_ib_ubuffer ubuffer;
433 struct mlx5_db *doorbell;
434 struct mlx5_flow_handle *flow_rule;
435 u32 tisn;
436 u8 state;
437 };
438
439 struct mlx5_ib_raw_packet_qp {
440 struct mlx5_ib_sq sq;
441 struct mlx5_ib_rq rq;
442 };
443
444 struct mlx5_bf {
445 int buf_size;
446 unsigned long offset;
447 struct mlx5_sq_bfreg *bfreg;
448 };
449
450 struct mlx5_ib_dct {
451 struct mlx5_core_dct mdct;
452 u32 *in;
453 };
454
455 struct mlx5_ib_gsi_qp {
456 struct ib_qp *rx_qp;
457 u32 port_num;
458 struct ib_qp_cap cap;
459 struct ib_cq *cq;
460 struct mlx5_ib_gsi_wr *outstanding_wrs;
461 u32 outstanding_pi, outstanding_ci;
462 int num_qps;
463 /* Protects access to the tx_qps. Post send operations synchronize
464 * with tx_qp creation in setup_qp(). Also protects the
465 * outstanding_wrs array and indices.
466 */
467 spinlock_t lock;
468 struct ib_qp **tx_qps;
469 };
470
471 struct mlx5_ib_qp {
472 struct ib_qp ibqp;
473 union {
474 struct mlx5_ib_qp_trans trans_qp;
475 struct mlx5_ib_raw_packet_qp raw_packet_qp;
476 struct mlx5_ib_rss_qp rss_qp;
477 struct mlx5_ib_dct dct;
478 struct mlx5_ib_gsi_qp gsi;
479 };
480 struct mlx5_frag_buf buf;
481
482 struct mlx5_db db;
483 struct mlx5_ib_wq rq;
484
485 u8 sq_signal_bits;
486 u8 next_fence;
487 struct mlx5_ib_wq sq;
488
489 /* serialize qp state modifications
490 */
491 struct mutex mutex;
492 /* cached variant of create_flags from struct ib_qp_init_attr */
493 u32 flags;
494 u32 port;
495 u8 state;
496 int max_inline_data;
497 struct mlx5_bf bf;
498 u8 has_rq:1;
499 u8 is_rss:1;
500
501 /* only for user space QPs. For kernel
502 * we have it from the bf object
503 */
504 int bfregn;
505
506 struct list_head qps_list;
507 struct list_head cq_recv_list;
508 struct list_head cq_send_list;
509 struct mlx5_rate_limit rl;
510 u32 underlay_qpn;
511 u32 flags_en;
512 /*
513 * IB/core doesn't store low-level QP types, so
514 * store both MLX and IBTA types in the field below.
515 */
516 enum ib_qp_type type;
517 /* A flag to indicate if there's a new counter is configured
518 * but not take effective
519 */
520 u32 counter_pending;
521 u16 gsi_lag_port;
522 };
523
524 struct mlx5_ib_cq_buf {
525 struct mlx5_frag_buf_ctrl fbc;
526 struct mlx5_frag_buf frag_buf;
527 struct ib_umem *umem;
528 int cqe_size;
529 int nent;
530 };
531
532 enum mlx5_ib_cq_pr_flags {
533 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
534 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1,
535 };
536
537 struct mlx5_ib_cq {
538 struct ib_cq ibcq;
539 struct mlx5_core_cq mcq;
540 struct mlx5_ib_cq_buf buf;
541 struct mlx5_db db;
542
543 /* serialize access to the CQ
544 */
545 spinlock_t lock;
546
547 /* protect resize cq
548 */
549 struct mutex resize_mutex;
550 struct mlx5_ib_cq_buf *resize_buf;
551 struct ib_umem *resize_umem;
552 int cqe_size;
553 struct list_head list_send_qp;
554 struct list_head list_recv_qp;
555 u32 create_flags;
556 struct list_head wc_list;
557 enum ib_cq_notify_flags notify_flags;
558 struct work_struct notify_work;
559 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
560 };
561
562 struct mlx5_ib_wc {
563 struct ib_wc wc;
564 struct list_head list;
565 };
566
567 struct mlx5_ib_srq {
568 struct ib_srq ibsrq;
569 struct mlx5_core_srq msrq;
570 struct mlx5_frag_buf buf;
571 struct mlx5_db db;
572 struct mlx5_frag_buf_ctrl fbc;
573 u64 *wrid;
574 /* protect SRQ hanlding
575 */
576 spinlock_t lock;
577 int head;
578 int tail;
579 u16 wqe_ctr;
580 struct ib_umem *umem;
581 /* serialize arming a SRQ
582 */
583 struct mutex mutex;
584 int wq_sig;
585 };
586
587 struct mlx5_ib_xrcd {
588 struct ib_xrcd ibxrcd;
589 u32 xrcdn;
590 };
591
592 enum mlx5_ib_mtt_access_flags {
593 MLX5_IB_MTT_READ = (1 << 0),
594 MLX5_IB_MTT_WRITE = (1 << 1),
595 };
596
597 struct mlx5_user_mmap_entry {
598 struct rdma_user_mmap_entry rdma_entry;
599 u8 mmap_flag;
600 u64 address;
601 u32 page_idx;
602 };
603
604 enum mlx5_mkey_type {
605 MLX5_MKEY_MR = 1,
606 MLX5_MKEY_MW,
607 MLX5_MKEY_INDIRECT_DEVX,
608 };
609
610 struct mlx5_ib_mkey {
611 u32 key;
612 enum mlx5_mkey_type type;
613 unsigned int ndescs;
614 struct wait_queue_head wait;
615 refcount_t usecount;
616 };
617
618 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
619
620 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
621 IB_ACCESS_REMOTE_WRITE |\
622 IB_ACCESS_REMOTE_READ |\
623 IB_ACCESS_REMOTE_ATOMIC |\
624 IB_ZERO_BASED)
625
626 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
627 IB_ACCESS_REMOTE_WRITE |\
628 IB_ACCESS_REMOTE_READ |\
629 IB_ZERO_BASED)
630
631 #define mlx5_update_odp_stats(mr, counter_name, value) \
632 atomic64_add(value, &((mr)->odp_stats.counter_name))
633
634 struct mlx5_ib_mr {
635 struct ib_mr ibmr;
636 struct mlx5_ib_mkey mmkey;
637
638 /* User MR data */
639 struct mlx5_cache_ent *cache_ent;
640 /* Everything after cache_ent is zero'd when MR allocated */
641 struct ib_umem *umem;
642
643 union {
644 /* Used only while the MR is in the cache */
645 struct {
646 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
647 struct mlx5_async_work cb_work;
648 /* Cache list element */
649 struct list_head list;
650 };
651
652 /* Used only by kernel MRs (umem == NULL) */
653 struct {
654 void *descs;
655 void *descs_alloc;
656 dma_addr_t desc_map;
657 int max_descs;
658 int desc_size;
659 int access_mode;
660
661 /* For Kernel IB_MR_TYPE_INTEGRITY */
662 struct mlx5_core_sig_ctx *sig;
663 struct mlx5_ib_mr *pi_mr;
664 struct mlx5_ib_mr *klm_mr;
665 struct mlx5_ib_mr *mtt_mr;
666 u64 data_iova;
667 u64 pi_iova;
668 int meta_ndescs;
669 int meta_length;
670 int data_length;
671 };
672
673 /* Used only by User MRs (umem != NULL) */
674 struct {
675 unsigned int page_shift;
676 /* Current access_flags */
677 int access_flags;
678
679 /* For User ODP */
680 struct mlx5_ib_mr *parent;
681 struct xarray implicit_children;
682 union {
683 struct work_struct work;
684 } odp_destroy;
685 struct ib_odp_counters odp_stats;
686 bool is_odp_implicit;
687 };
688 };
689 };
690
691 /* Zero the fields in the mr that are variant depending on usage */
mlx5_clear_mr(struct mlx5_ib_mr * mr)692 static inline void mlx5_clear_mr(struct mlx5_ib_mr *mr)
693 {
694 memset_after(mr, 0, cache_ent);
695 }
696
is_odp_mr(struct mlx5_ib_mr * mr)697 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
698 {
699 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
700 mr->umem->is_odp;
701 }
702
is_dmabuf_mr(struct mlx5_ib_mr * mr)703 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr)
704 {
705 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
706 mr->umem->is_dmabuf;
707 }
708
709 struct mlx5_ib_mw {
710 struct ib_mw ibmw;
711 struct mlx5_ib_mkey mmkey;
712 };
713
714 struct mlx5_ib_umr_context {
715 struct ib_cqe cqe;
716 enum ib_wc_status status;
717 struct completion done;
718 };
719
720 enum {
721 MLX5_UMR_STATE_UNINIT,
722 MLX5_UMR_STATE_ACTIVE,
723 MLX5_UMR_STATE_RECOVER,
724 MLX5_UMR_STATE_ERR,
725 };
726
727 struct umr_common {
728 struct ib_pd *pd;
729 struct ib_cq *cq;
730 struct ib_qp *qp;
731 /* Protects from UMR QP overflow
732 */
733 struct semaphore sem;
734 /* Protects from using UMR while the UMR is not active
735 */
736 struct mutex lock;
737 unsigned int state;
738 };
739
740 struct mlx5_cache_ent {
741 struct list_head head;
742 /* sync access to the cahce entry
743 */
744 spinlock_t lock;
745
746
747 char name[4];
748 u32 order;
749 u32 access_mode;
750 u32 page;
751 unsigned int ndescs;
752
753 u8 disabled:1;
754 u8 fill_to_high_water:1;
755
756 /*
757 * - available_mrs is the length of list head, ie the number of MRs
758 * available for immediate allocation.
759 * - total_mrs is available_mrs plus all in use MRs that could be
760 * returned to the cache.
761 * - limit is the low water mark for available_mrs, 2* limit is the
762 * upper water mark.
763 * - pending is the number of MRs currently being created
764 */
765 u32 total_mrs;
766 u32 available_mrs;
767 u32 limit;
768 u32 pending;
769
770 /* Statistics */
771 u32 miss;
772
773 struct mlx5_ib_dev *dev;
774 struct delayed_work dwork;
775 };
776
777 struct mlx5_mr_cache {
778 struct workqueue_struct *wq;
779 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
780 struct dentry *root;
781 unsigned long last_add;
782 };
783
784 struct mlx5_ib_port_resources {
785 struct mlx5_ib_gsi_qp *gsi;
786 struct work_struct pkey_change_work;
787 };
788
789 struct mlx5_ib_resources {
790 struct ib_cq *c0;
791 u32 xrcdn0;
792 u32 xrcdn1;
793 struct ib_pd *p0;
794 struct ib_srq *s0;
795 struct ib_srq *s1;
796 struct mlx5_ib_port_resources ports[2];
797 };
798
799 #define MAX_OPFC_RULES 2
800
801 struct mlx5_ib_op_fc {
802 struct mlx5_fc *fc;
803 struct mlx5_flow_handle *rule[MAX_OPFC_RULES];
804 };
805
806 struct mlx5_ib_counters {
807 struct rdma_stat_desc *descs;
808 size_t *offsets;
809 u32 num_q_counters;
810 u32 num_cong_counters;
811 u32 num_ext_ppcnt_counters;
812 u32 num_op_counters;
813 u16 set_id;
814 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX];
815 };
816
817 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num,
818 struct mlx5_ib_op_fc *opfc,
819 enum mlx5_ib_optional_counter_type type);
820
821 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev,
822 struct mlx5_ib_op_fc *opfc,
823 enum mlx5_ib_optional_counter_type type);
824
825 struct mlx5_ib_multiport_info;
826
827 struct mlx5_ib_multiport {
828 struct mlx5_ib_multiport_info *mpi;
829 /* To be held when accessing the multiport info */
830 spinlock_t mpi_lock;
831 };
832
833 struct mlx5_roce {
834 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
835 * netdev pointer
836 */
837 rwlock_t netdev_lock;
838 struct net_device *netdev;
839 struct notifier_block nb;
840 atomic_t tx_port_affinity;
841 enum ib_port_state last_port_state;
842 struct mlx5_ib_dev *dev;
843 u32 native_port_num;
844 };
845
846 struct mlx5_ib_port {
847 struct mlx5_ib_counters cnts;
848 struct mlx5_ib_multiport mp;
849 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
850 struct mlx5_roce roce;
851 struct mlx5_eswitch_rep *rep;
852 };
853
854 struct mlx5_ib_dbg_param {
855 int offset;
856 struct mlx5_ib_dev *dev;
857 struct dentry *dentry;
858 u32 port_num;
859 };
860
861 enum mlx5_ib_dbg_cc_types {
862 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
863 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
864 MLX5_IB_DBG_CC_RP_TIME_RESET,
865 MLX5_IB_DBG_CC_RP_BYTE_RESET,
866 MLX5_IB_DBG_CC_RP_THRESHOLD,
867 MLX5_IB_DBG_CC_RP_AI_RATE,
868 MLX5_IB_DBG_CC_RP_MAX_RATE,
869 MLX5_IB_DBG_CC_RP_HAI_RATE,
870 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
871 MLX5_IB_DBG_CC_RP_MIN_RATE,
872 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
873 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
874 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
875 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
876 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
877 MLX5_IB_DBG_CC_RP_GD,
878 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
879 MLX5_IB_DBG_CC_NP_CNP_DSCP,
880 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
881 MLX5_IB_DBG_CC_NP_CNP_PRIO,
882 MLX5_IB_DBG_CC_MAX,
883 };
884
885 struct mlx5_ib_dbg_cc_params {
886 struct dentry *root;
887 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
888 };
889
890 enum {
891 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
892 };
893
894 struct mlx5_ib_delay_drop {
895 struct mlx5_ib_dev *dev;
896 struct work_struct delay_drop_work;
897 /* serialize setting of delay drop */
898 struct mutex lock;
899 u32 timeout;
900 bool activate;
901 atomic_t events_cnt;
902 atomic_t rqs_cnt;
903 struct dentry *dir_debugfs;
904 };
905
906 enum mlx5_ib_stages {
907 MLX5_IB_STAGE_INIT,
908 MLX5_IB_STAGE_FS,
909 MLX5_IB_STAGE_CAPS,
910 MLX5_IB_STAGE_NON_DEFAULT_CB,
911 MLX5_IB_STAGE_ROCE,
912 MLX5_IB_STAGE_QP,
913 MLX5_IB_STAGE_SRQ,
914 MLX5_IB_STAGE_DEVICE_RESOURCES,
915 MLX5_IB_STAGE_DEVICE_NOTIFIER,
916 MLX5_IB_STAGE_ODP,
917 MLX5_IB_STAGE_COUNTERS,
918 MLX5_IB_STAGE_CONG_DEBUGFS,
919 MLX5_IB_STAGE_UAR,
920 MLX5_IB_STAGE_BFREG,
921 MLX5_IB_STAGE_PRE_IB_REG_UMR,
922 MLX5_IB_STAGE_WHITELIST_UID,
923 MLX5_IB_STAGE_IB_REG,
924 MLX5_IB_STAGE_POST_IB_REG_UMR,
925 MLX5_IB_STAGE_DELAY_DROP,
926 MLX5_IB_STAGE_RESTRACK,
927 MLX5_IB_STAGE_MAX,
928 };
929
930 struct mlx5_ib_stage {
931 int (*init)(struct mlx5_ib_dev *dev);
932 void (*cleanup)(struct mlx5_ib_dev *dev);
933 };
934
935 #define STAGE_CREATE(_stage, _init, _cleanup) \
936 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
937
938 struct mlx5_ib_profile {
939 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
940 };
941
942 struct mlx5_ib_multiport_info {
943 struct list_head list;
944 struct mlx5_ib_dev *ibdev;
945 struct mlx5_core_dev *mdev;
946 struct notifier_block mdev_events;
947 struct completion unref_comp;
948 u64 sys_image_guid;
949 u32 mdev_refcnt;
950 bool is_master;
951 bool unaffiliate;
952 };
953
954 struct mlx5_ib_flow_action {
955 struct ib_flow_action ib_action;
956 union {
957 struct {
958 u64 ib_flags;
959 struct mlx5_accel_esp_xfrm *ctx;
960 } esp_aes_gcm;
961 struct {
962 struct mlx5_ib_dev *dev;
963 u32 sub_type;
964 union {
965 struct mlx5_modify_hdr *modify_hdr;
966 struct mlx5_pkt_reformat *pkt_reformat;
967 };
968 } flow_action_raw;
969 };
970 };
971
972 struct mlx5_dm {
973 struct mlx5_core_dev *dev;
974 /* This lock is used to protect the access to the shared
975 * allocation map when concurrent requests by different
976 * processes are handled.
977 */
978 spinlock_t lock;
979 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
980 };
981
982 struct mlx5_read_counters_attr {
983 struct mlx5_fc *hw_cntrs_hndl;
984 u64 *out;
985 u32 flags;
986 };
987
988 enum mlx5_ib_counters_type {
989 MLX5_IB_COUNTERS_FLOW,
990 };
991
992 struct mlx5_ib_mcounters {
993 struct ib_counters ibcntrs;
994 enum mlx5_ib_counters_type type;
995 /* number of counters supported for this counters type */
996 u32 counters_num;
997 struct mlx5_fc *hw_cntrs_hndl;
998 /* read function for this counters type */
999 int (*read_counters)(struct ib_device *ibdev,
1000 struct mlx5_read_counters_attr *read_attr);
1001 /* max index set as part of create_flow */
1002 u32 cntrs_max_index;
1003 /* number of counters data entries (<description,index> pair) */
1004 u32 ncounters;
1005 /* counters data array for descriptions and indexes */
1006 struct mlx5_ib_flow_counters_desc *counters_data;
1007 /* protects access to mcounters internal data */
1008 struct mutex mcntrs_mutex;
1009 };
1010
1011 static inline struct mlx5_ib_mcounters *
to_mcounters(struct ib_counters * ibcntrs)1012 to_mcounters(struct ib_counters *ibcntrs)
1013 {
1014 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
1015 }
1016
1017 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
1018 bool is_egress,
1019 struct mlx5_flow_act *action);
1020 struct mlx5_ib_lb_state {
1021 /* protect the user_td */
1022 struct mutex mutex;
1023 u32 user_td;
1024 int qps;
1025 bool enabled;
1026 };
1027
1028 struct mlx5_ib_pf_eq {
1029 struct notifier_block irq_nb;
1030 struct mlx5_ib_dev *dev;
1031 struct mlx5_eq *core;
1032 struct work_struct work;
1033 spinlock_t lock; /* Pagefaults spinlock */
1034 struct workqueue_struct *wq;
1035 mempool_t *pool;
1036 };
1037
1038 struct mlx5_devx_event_table {
1039 struct mlx5_nb devx_nb;
1040 /* serialize updating the event_xa */
1041 struct mutex event_xa_lock;
1042 struct xarray event_xa;
1043 };
1044
1045 struct mlx5_var_table {
1046 /* serialize updating the bitmap */
1047 struct mutex bitmap_lock;
1048 unsigned long *bitmap;
1049 u64 hw_start_addr;
1050 u32 stride_size;
1051 u64 num_var_hw_entries;
1052 };
1053
1054 struct mlx5_port_caps {
1055 bool has_smi;
1056 u8 ext_port_cap;
1057 };
1058
1059 struct mlx5_ib_dev {
1060 struct ib_device ib_dev;
1061 struct mlx5_core_dev *mdev;
1062 struct notifier_block mdev_events;
1063 int num_ports;
1064 /* serialize update of capability mask
1065 */
1066 struct mutex cap_mask_mutex;
1067 u8 ib_active:1;
1068 u8 is_rep:1;
1069 u8 lag_active:1;
1070 u8 wc_support:1;
1071 u8 fill_delay;
1072 struct umr_common umrc;
1073 /* sync used page count stats
1074 */
1075 struct mlx5_ib_resources devr;
1076
1077 atomic_t mkey_var;
1078 struct mlx5_mr_cache cache;
1079 struct timer_list delay_timer;
1080 /* Prevents soft lock on massive reg MRs */
1081 struct mutex slow_path_mutex;
1082 struct ib_odp_caps odp_caps;
1083 u64 odp_max_size;
1084 struct mutex odp_eq_mutex;
1085 struct mlx5_ib_pf_eq odp_pf_eq;
1086
1087 struct xarray odp_mkeys;
1088
1089 u32 null_mkey;
1090 struct mlx5_ib_flow_db *flow_db;
1091 /* protect resources needed as part of reset flow */
1092 spinlock_t reset_flow_resource_lock;
1093 struct list_head qp_list;
1094 /* Array with num_ports elements */
1095 struct mlx5_ib_port *port;
1096 struct mlx5_sq_bfreg bfreg;
1097 struct mlx5_sq_bfreg wc_bfreg;
1098 struct mlx5_sq_bfreg fp_bfreg;
1099 struct mlx5_ib_delay_drop delay_drop;
1100 const struct mlx5_ib_profile *profile;
1101
1102 struct mlx5_ib_lb_state lb;
1103 u8 umr_fence;
1104 struct list_head ib_dev_list;
1105 u64 sys_image_guid;
1106 struct mlx5_dm dm;
1107 u16 devx_whitelist_uid;
1108 struct mlx5_srq_table srq_table;
1109 struct mlx5_qp_table qp_table;
1110 struct mlx5_async_ctx async_ctx;
1111 struct mlx5_devx_event_table devx_event_table;
1112 struct mlx5_var_table var_table;
1113
1114 struct xarray sig_mrs;
1115 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
1116 u16 pkey_table_len;
1117 u8 lag_ports;
1118 };
1119
to_mibcq(struct mlx5_core_cq * mcq)1120 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1121 {
1122 return container_of(mcq, struct mlx5_ib_cq, mcq);
1123 }
1124
to_mxrcd(struct ib_xrcd * ibxrcd)1125 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1126 {
1127 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1128 }
1129
to_mdev(struct ib_device * ibdev)1130 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1131 {
1132 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1133 }
1134
mr_to_mdev(struct mlx5_ib_mr * mr)1135 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr)
1136 {
1137 return to_mdev(mr->ibmr.device);
1138 }
1139
mlx5_udata_to_mdev(struct ib_udata * udata)1140 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1141 {
1142 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1143 udata, struct mlx5_ib_ucontext, ibucontext);
1144
1145 return to_mdev(context->ibucontext.device);
1146 }
1147
to_mcq(struct ib_cq * ibcq)1148 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1149 {
1150 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1151 }
1152
to_mibqp(struct mlx5_core_qp * mqp)1153 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1154 {
1155 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1156 }
1157
to_mibrwq(struct mlx5_core_qp * core_qp)1158 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1159 {
1160 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1161 }
1162
to_mpd(struct ib_pd * ibpd)1163 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1164 {
1165 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1166 }
1167
to_msrq(struct ib_srq * ibsrq)1168 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1169 {
1170 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1171 }
1172
to_mqp(struct ib_qp * ibqp)1173 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1174 {
1175 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1176 }
1177
to_mrwq(struct ib_wq * ibwq)1178 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1179 {
1180 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1181 }
1182
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)1183 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1184 {
1185 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1186 }
1187
to_mibsrq(struct mlx5_core_srq * msrq)1188 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1189 {
1190 return container_of(msrq, struct mlx5_ib_srq, msrq);
1191 }
1192
to_mmr(struct ib_mr * ibmr)1193 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1194 {
1195 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1196 }
1197
to_mmw(struct ib_mw * ibmw)1198 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1199 {
1200 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1201 }
1202
1203 static inline struct mlx5_ib_flow_action *
to_mflow_act(struct ib_flow_action * ibact)1204 to_mflow_act(struct ib_flow_action *ibact)
1205 {
1206 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1207 }
1208
1209 static inline struct mlx5_user_mmap_entry *
to_mmmap(struct rdma_user_mmap_entry * rdma_entry)1210 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1211 {
1212 return container_of(rdma_entry,
1213 struct mlx5_user_mmap_entry, rdma_entry);
1214 }
1215
1216 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1217 struct mlx5_db *db);
1218 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1219 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1220 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1221 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1222 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1223 struct ib_udata *udata);
1224 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
mlx5_ib_destroy_ah(struct ib_ah * ah,u32 flags)1225 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1226 {
1227 return 0;
1228 }
1229 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1230 struct ib_udata *udata);
1231 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1232 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1233 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1234 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1235 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1236 const struct ib_recv_wr **bad_wr);
1237 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1238 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1239 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
1240 struct ib_udata *udata);
1241 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1242 int attr_mask, struct ib_udata *udata);
1243 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1244 struct ib_qp_init_attr *qp_init_attr);
1245 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1246 void mlx5_ib_drain_sq(struct ib_qp *qp);
1247 void mlx5_ib_drain_rq(struct ib_qp *qp);
1248 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1249 size_t buflen, size_t *bc);
1250 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1251 size_t buflen, size_t *bc);
1252 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1253 size_t buflen, size_t *bc);
1254 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1255 struct ib_udata *udata);
1256 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1257 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1258 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1259 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1260 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1261 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1262 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1263 u64 virt_addr, int access_flags,
1264 struct ib_udata *udata);
1265 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
1266 u64 length, u64 virt_addr,
1267 int fd, int access_flags,
1268 struct ib_udata *udata);
1269 int mlx5_ib_advise_mr(struct ib_pd *pd,
1270 enum ib_uverbs_advise_mr_advice advice,
1271 u32 flags,
1272 struct ib_sge *sg_list,
1273 u32 num_sge,
1274 struct uverbs_attr_bundle *attrs);
1275 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1276 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1277 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1278 int access_flags);
1279 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1280 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr);
1281 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1282 u64 length, u64 virt_addr, int access_flags,
1283 struct ib_pd *pd, struct ib_udata *udata);
1284 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1285 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1286 u32 max_num_sg);
1287 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1288 u32 max_num_sg,
1289 u32 max_num_meta_sg);
1290 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1291 unsigned int *sg_offset);
1292 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1293 int data_sg_nents, unsigned int *data_sg_offset,
1294 struct scatterlist *meta_sg, int meta_sg_nents,
1295 unsigned int *meta_sg_offset);
1296 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,
1297 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1298 const struct ib_mad *in, struct ib_mad *out,
1299 size_t *out_mad_size, u16 *out_mad_pkey_index);
1300 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1301 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1302 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port);
1303 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1304 __be64 *sys_image_guid);
1305 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1306 u16 *max_pkeys);
1307 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1308 u32 *vendor_id);
1309 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1310 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1311 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index,
1312 u16 *pkey);
1313 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index,
1314 union ib_gid *gid);
1315 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port,
1316 struct ib_port_attr *props);
1317 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1318 struct ib_port_attr *props);
1319 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
1320 u64 access_flags);
1321 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1322 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1323 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1324 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1325
1326 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1327 struct mlx5_cache_ent *ent,
1328 int access_flags);
1329
1330 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1331 struct ib_mr_status *mr_status);
1332 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1333 struct ib_wq_init_attr *init_attr,
1334 struct ib_udata *udata);
1335 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1336 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1337 u32 wq_attr_mask, struct ib_udata *udata);
1338 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1339 struct ib_rwq_ind_table_init_attr *init_attr,
1340 struct ib_udata *udata);
1341 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1342 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1343 struct ib_dm_mr_attr *attr,
1344 struct uverbs_attr_bundle *attrs);
1345
1346 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1347 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1348 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq);
1349 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1350 int __init mlx5_ib_odp_init(void);
1351 void mlx5_ib_odp_cleanup(void);
1352 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1353 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1354 struct mlx5_ib_mr *mr, int flags);
1355
1356 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1357 enum ib_uverbs_advise_mr_advice advice,
1358 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1359 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr);
1360 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr);
1361 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1362 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5r_odp_create_eq(struct mlx5_ib_dev * dev,struct mlx5_ib_pf_eq * eq)1363 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev,
1364 struct mlx5_ib_pf_eq *eq)
1365 {
1366 return 0;
1367 }
mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev * ibdev)1368 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
mlx5_ib_odp_init(void)1369 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)1370 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent * ent)1371 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
mlx5_odp_populate_xlt(void * xlt,size_t idx,size_t nentries,struct mlx5_ib_mr * mr,int flags)1372 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1373 struct mlx5_ib_mr *mr, int flags) {}
1374
1375 static inline int
mlx5_ib_advise_mr_prefetch(struct ib_pd * pd,enum ib_uverbs_advise_mr_advice advice,u32 flags,struct ib_sge * sg_list,u32 num_sge)1376 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1377 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1378 struct ib_sge *sg_list, u32 num_sge)
1379 {
1380 return -EOPNOTSUPP;
1381 }
mlx5_ib_init_odp_mr(struct mlx5_ib_mr * mr)1382 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
1383 {
1384 return -EOPNOTSUPP;
1385 }
mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr * mr)1386 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
1387 {
1388 return -EOPNOTSUPP;
1389 }
1390 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1391
1392 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1393
1394 /* Needed for rep profile */
1395 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1396 const struct mlx5_ib_profile *profile,
1397 int stage);
1398 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
1399 const struct mlx5_ib_profile *profile);
1400
1401 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1402 u32 port, struct ifla_vf_info *info);
1403 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1404 u32 port, int state);
1405 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1406 u32 port, struct ifla_vf_stats *stats);
1407 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port,
1408 struct ifla_vf_guid *node_guid,
1409 struct ifla_vf_guid *port_guid);
1410 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port,
1411 u64 guid, int type);
1412
1413 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1414 const struct ib_gid_attr *attr);
1415
1416 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1417 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1418
1419 /* GSI QP helper functions */
1420 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1421 struct ib_qp_init_attr *attr);
1422 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1423 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1424 int attr_mask);
1425 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1426 int qp_attr_mask,
1427 struct ib_qp_init_attr *qp_init_attr);
1428 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1429 const struct ib_send_wr **bad_wr);
1430 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1431 const struct ib_recv_wr **bad_wr);
1432 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1433
1434 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1435
1436 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1437 int bfregn);
1438 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1439 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1440 u32 ib_port_num,
1441 u32 *native_port_num);
1442 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1443 u32 port_num);
1444
1445 extern const struct uapi_definition mlx5_ib_devx_defs[];
1446 extern const struct uapi_definition mlx5_ib_flow_defs[];
1447 extern const struct uapi_definition mlx5_ib_qos_defs[];
1448 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1449
is_qp1(enum ib_qp_type qp_type)1450 static inline int is_qp1(enum ib_qp_type qp_type)
1451 {
1452 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1453 }
1454
check_cq_create_flags(u32 flags)1455 static inline u32 check_cq_create_flags(u32 flags)
1456 {
1457 /*
1458 * It returns non-zero value for unsupported CQ
1459 * create flags, otherwise it returns zero.
1460 */
1461 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1462 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1463 }
1464
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1465 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1466 u32 *user_index)
1467 {
1468 if (cqe_version) {
1469 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1470 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1471 return -EINVAL;
1472 *user_index = cmd_uidx;
1473 } else {
1474 *user_index = MLX5_IB_DEFAULT_UIDX;
1475 }
1476
1477 return 0;
1478 }
1479
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1480 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1481 struct mlx5_ib_create_qp *ucmd,
1482 int inlen,
1483 u32 *user_index)
1484 {
1485 u8 cqe_version = ucontext->cqe_version;
1486
1487 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1488 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1489 return 0;
1490
1491 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1492 return -EINVAL;
1493
1494 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1495 }
1496
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1497 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1498 struct mlx5_ib_create_srq *ucmd,
1499 int inlen,
1500 u32 *user_index)
1501 {
1502 u8 cqe_version = ucontext->cqe_version;
1503
1504 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1505 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1506 return 0;
1507
1508 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1509 return -EINVAL;
1510
1511 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1512 }
1513
get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1514 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1515 {
1516 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1517 MLX5_UARS_IN_PAGE : 1;
1518 }
1519
1520 extern void *xlt_emergency_page;
1521
1522 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1523 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1524 bool dyn_bfreg);
1525
mlx5r_store_odp_mkey(struct mlx5_ib_dev * dev,struct mlx5_ib_mkey * mmkey)1526 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev,
1527 struct mlx5_ib_mkey *mmkey)
1528 {
1529 refcount_set(&mmkey->usecount, 1);
1530
1531 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key),
1532 mmkey, GFP_KERNEL));
1533 }
1534
1535 /* deref an mkey that can participate in ODP flow */
mlx5r_deref_odp_mkey(struct mlx5_ib_mkey * mmkey)1536 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey)
1537 {
1538 if (refcount_dec_and_test(&mmkey->usecount))
1539 wake_up(&mmkey->wait);
1540 }
1541
1542 /* deref an mkey that can participate in ODP flow and wait for relese */
mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey * mmkey)1543 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey)
1544 {
1545 mlx5r_deref_odp_mkey(mmkey);
1546 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0);
1547 }
1548
1549 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1550
mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev * dev)1551 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1552 {
1553 return dev->lag_active ||
1554 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1555 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1556 }
1557
rt_supported(int ts_cap)1558 static inline bool rt_supported(int ts_cap)
1559 {
1560 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME ||
1561 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;
1562 }
1563 #endif /* MLX5_IB_H */
1564