1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor.
4 *
5 * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
6 *
7 * TODO:
8 * - Support for power management
9 * - Support events and interrupts
10 * - Create channel for step count
11 * - Create channel for sensor time
12 */
13
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/device.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/trigger_consumer.h>
27 #include <linux/iio/triggered_buffer.h>
28
29 #include "bma400.h"
30
31 /*
32 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may
33 * be selected with the acc_range bits of the ACC_CONFIG1 register.
34 * NB: This buffer is populated in the device init.
35 */
36 static int bma400_scales[8];
37
38 /*
39 * See the ACC_CONFIG1 section of the datasheet.
40 * NB: This buffer is populated in the device init.
41 */
42 static int bma400_sample_freqs[14];
43
44 static const int bma400_osr_range[] = { 0, 1, 3 };
45
46 /* See the ACC_CONFIG0 section of the datasheet */
47 enum bma400_power_mode {
48 POWER_MODE_SLEEP = 0x00,
49 POWER_MODE_LOW = 0x01,
50 POWER_MODE_NORMAL = 0x02,
51 POWER_MODE_INVALID = 0x03,
52 };
53
54 enum bma400_scan {
55 BMA400_ACCL_X,
56 BMA400_ACCL_Y,
57 BMA400_ACCL_Z,
58 BMA400_TEMP,
59 };
60
61 struct bma400_sample_freq {
62 int hz;
63 int uhz;
64 };
65
66 struct bma400_data {
67 struct device *dev;
68 struct regmap *regmap;
69 struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS];
70 struct mutex mutex; /* data register lock */
71 struct iio_mount_matrix orientation;
72 enum bma400_power_mode power_mode;
73 struct bma400_sample_freq sample_freq;
74 int oversampling_ratio;
75 int scale;
76 struct iio_trigger *trig;
77 /* Correct time stamp alignment */
78 struct {
79 __le16 buff[3];
80 u8 temperature;
81 s64 ts __aligned(8);
82 } buffer __aligned(IIO_DMA_MINALIGN);
83 __le16 status;
84 };
85
bma400_is_writable_reg(struct device * dev,unsigned int reg)86 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg)
87 {
88 switch (reg) {
89 case BMA400_CHIP_ID_REG:
90 case BMA400_ERR_REG:
91 case BMA400_STATUS_REG:
92 case BMA400_X_AXIS_LSB_REG:
93 case BMA400_X_AXIS_MSB_REG:
94 case BMA400_Y_AXIS_LSB_REG:
95 case BMA400_Y_AXIS_MSB_REG:
96 case BMA400_Z_AXIS_LSB_REG:
97 case BMA400_Z_AXIS_MSB_REG:
98 case BMA400_SENSOR_TIME0:
99 case BMA400_SENSOR_TIME1:
100 case BMA400_SENSOR_TIME2:
101 case BMA400_EVENT_REG:
102 case BMA400_INT_STAT0_REG:
103 case BMA400_INT_STAT1_REG:
104 case BMA400_INT_STAT2_REG:
105 case BMA400_TEMP_DATA_REG:
106 case BMA400_FIFO_LENGTH0_REG:
107 case BMA400_FIFO_LENGTH1_REG:
108 case BMA400_FIFO_DATA_REG:
109 case BMA400_STEP_CNT0_REG:
110 case BMA400_STEP_CNT1_REG:
111 case BMA400_STEP_CNT3_REG:
112 case BMA400_STEP_STAT_REG:
113 return false;
114 default:
115 return true;
116 }
117 }
118
bma400_is_volatile_reg(struct device * dev,unsigned int reg)119 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg)
120 {
121 switch (reg) {
122 case BMA400_ERR_REG:
123 case BMA400_STATUS_REG:
124 case BMA400_X_AXIS_LSB_REG:
125 case BMA400_X_AXIS_MSB_REG:
126 case BMA400_Y_AXIS_LSB_REG:
127 case BMA400_Y_AXIS_MSB_REG:
128 case BMA400_Z_AXIS_LSB_REG:
129 case BMA400_Z_AXIS_MSB_REG:
130 case BMA400_SENSOR_TIME0:
131 case BMA400_SENSOR_TIME1:
132 case BMA400_SENSOR_TIME2:
133 case BMA400_EVENT_REG:
134 case BMA400_INT_STAT0_REG:
135 case BMA400_INT_STAT1_REG:
136 case BMA400_INT_STAT2_REG:
137 case BMA400_TEMP_DATA_REG:
138 case BMA400_FIFO_LENGTH0_REG:
139 case BMA400_FIFO_LENGTH1_REG:
140 case BMA400_FIFO_DATA_REG:
141 case BMA400_STEP_CNT0_REG:
142 case BMA400_STEP_CNT1_REG:
143 case BMA400_STEP_CNT3_REG:
144 case BMA400_STEP_STAT_REG:
145 return true;
146 default:
147 return false;
148 }
149 }
150
151 const struct regmap_config bma400_regmap_config = {
152 .reg_bits = 8,
153 .val_bits = 8,
154 .max_register = BMA400_CMD_REG,
155 .cache_type = REGCACHE_RBTREE,
156 .writeable_reg = bma400_is_writable_reg,
157 .volatile_reg = bma400_is_volatile_reg,
158 };
159 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400);
160
161 static const struct iio_mount_matrix *
bma400_accel_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)162 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev,
163 const struct iio_chan_spec *chan)
164 {
165 struct bma400_data *data = iio_priv(indio_dev);
166
167 return &data->orientation;
168 }
169
170 static const struct iio_chan_spec_ext_info bma400_ext_info[] = {
171 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix),
172 { }
173 };
174
175 #define BMA400_ACC_CHANNEL(_index, _axis) { \
176 .type = IIO_ACCEL, \
177 .modified = 1, \
178 .channel2 = IIO_MOD_##_axis, \
179 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
180 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
181 BIT(IIO_CHAN_INFO_SCALE) | \
182 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
183 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
184 BIT(IIO_CHAN_INFO_SCALE) | \
185 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
186 .ext_info = bma400_ext_info, \
187 .scan_index = _index, \
188 .scan_type = { \
189 .sign = 's', \
190 .realbits = 12, \
191 .storagebits = 16, \
192 .endianness = IIO_LE, \
193 }, \
194 }
195
196 static const struct iio_chan_spec bma400_channels[] = {
197 BMA400_ACC_CHANNEL(0, X),
198 BMA400_ACC_CHANNEL(1, Y),
199 BMA400_ACC_CHANNEL(2, Z),
200 {
201 .type = IIO_TEMP,
202 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
203 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
204 .scan_index = 3,
205 .scan_type = {
206 .sign = 's',
207 .realbits = 8,
208 .storagebits = 8,
209 .endianness = IIO_LE,
210 },
211 },
212 IIO_CHAN_SOFT_TIMESTAMP(4),
213 };
214
bma400_get_temp_reg(struct bma400_data * data,int * val,int * val2)215 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2)
216 {
217 unsigned int raw_temp;
218 int host_temp;
219 int ret;
220
221 if (data->power_mode == POWER_MODE_SLEEP)
222 return -EBUSY;
223
224 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp);
225 if (ret)
226 return ret;
227
228 host_temp = sign_extend32(raw_temp, 7);
229 /*
230 * The formula for the TEMP_DATA register in the datasheet
231 * is: x * 0.5 + 23
232 */
233 *val = (host_temp >> 1) + 23;
234 *val2 = (host_temp & 0x1) * 500000;
235 return IIO_VAL_INT_PLUS_MICRO;
236 }
237
bma400_get_accel_reg(struct bma400_data * data,const struct iio_chan_spec * chan,int * val)238 static int bma400_get_accel_reg(struct bma400_data *data,
239 const struct iio_chan_spec *chan,
240 int *val)
241 {
242 __le16 raw_accel;
243 int lsb_reg;
244 int ret;
245
246 if (data->power_mode == POWER_MODE_SLEEP)
247 return -EBUSY;
248
249 switch (chan->channel2) {
250 case IIO_MOD_X:
251 lsb_reg = BMA400_X_AXIS_LSB_REG;
252 break;
253 case IIO_MOD_Y:
254 lsb_reg = BMA400_Y_AXIS_LSB_REG;
255 break;
256 case IIO_MOD_Z:
257 lsb_reg = BMA400_Z_AXIS_LSB_REG;
258 break;
259 default:
260 dev_err(data->dev, "invalid axis channel modifier\n");
261 return -EINVAL;
262 }
263
264 /* bulk read two registers, with the base being the LSB register */
265 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel,
266 sizeof(raw_accel));
267 if (ret)
268 return ret;
269
270 *val = sign_extend32(le16_to_cpu(raw_accel), 11);
271 return IIO_VAL_INT;
272 }
273
bma400_output_data_rate_from_raw(int raw,unsigned int * val,unsigned int * val2)274 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val,
275 unsigned int *val2)
276 {
277 *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw);
278 if (raw > BMA400_ACC_ODR_MIN_RAW)
279 *val2 = 0;
280 else
281 *val2 = 500000;
282 }
283
bma400_get_accel_output_data_rate(struct bma400_data * data)284 static int bma400_get_accel_output_data_rate(struct bma400_data *data)
285 {
286 unsigned int val;
287 unsigned int odr;
288 int ret;
289
290 switch (data->power_mode) {
291 case POWER_MODE_LOW:
292 /*
293 * Runs at a fixed rate in low-power mode. See section 4.3
294 * in the datasheet.
295 */
296 bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW,
297 &data->sample_freq.hz,
298 &data->sample_freq.uhz);
299 return 0;
300 case POWER_MODE_NORMAL:
301 /*
302 * In normal mode the ODR can be found in the ACC_CONFIG1
303 * register.
304 */
305 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
306 if (ret)
307 goto error;
308
309 odr = val & BMA400_ACC_ODR_MASK;
310 if (odr < BMA400_ACC_ODR_MIN_RAW ||
311 odr > BMA400_ACC_ODR_MAX_RAW) {
312 ret = -EINVAL;
313 goto error;
314 }
315
316 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz,
317 &data->sample_freq.uhz);
318 return 0;
319 case POWER_MODE_SLEEP:
320 data->sample_freq.hz = 0;
321 data->sample_freq.uhz = 0;
322 return 0;
323 default:
324 ret = 0;
325 goto error;
326 }
327 error:
328 data->sample_freq.hz = -1;
329 data->sample_freq.uhz = -1;
330 return ret;
331 }
332
bma400_set_accel_output_data_rate(struct bma400_data * data,int hz,int uhz)333 static int bma400_set_accel_output_data_rate(struct bma400_data *data,
334 int hz, int uhz)
335 {
336 unsigned int idx;
337 unsigned int odr;
338 unsigned int val;
339 int ret;
340
341 if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) {
342 if (uhz || hz > BMA400_ACC_ODR_MAX_HZ)
343 return -EINVAL;
344
345 /* Note this works because MIN_WHOLE_HZ is odd */
346 idx = __ffs(hz);
347
348 if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ)
349 return -EINVAL;
350
351 idx += BMA400_ACC_ODR_MIN_RAW + 1;
352 } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) {
353 idx = BMA400_ACC_ODR_MIN_RAW;
354 } else {
355 return -EINVAL;
356 }
357
358 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
359 if (ret)
360 return ret;
361
362 /* preserve the range and normal mode osr */
363 odr = (~BMA400_ACC_ODR_MASK & val) | idx;
364
365 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr);
366 if (ret)
367 return ret;
368
369 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz,
370 &data->sample_freq.uhz);
371 return 0;
372 }
373
bma400_get_accel_oversampling_ratio(struct bma400_data * data)374 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data)
375 {
376 unsigned int val;
377 unsigned int osr;
378 int ret;
379
380 /*
381 * The oversampling ratio is stored in a different register
382 * based on the power-mode. In normal mode the OSR is stored
383 * in ACC_CONFIG1. In low-power mode it is stored in
384 * ACC_CONFIG0.
385 */
386 switch (data->power_mode) {
387 case POWER_MODE_LOW:
388 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
389 if (ret) {
390 data->oversampling_ratio = -1;
391 return ret;
392 }
393
394 osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT;
395
396 data->oversampling_ratio = osr;
397 return 0;
398 case POWER_MODE_NORMAL:
399 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
400 if (ret) {
401 data->oversampling_ratio = -1;
402 return ret;
403 }
404
405 osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT;
406
407 data->oversampling_ratio = osr;
408 return 0;
409 case POWER_MODE_SLEEP:
410 data->oversampling_ratio = 0;
411 return 0;
412 default:
413 data->oversampling_ratio = -1;
414 return -EINVAL;
415 }
416 }
417
bma400_set_accel_oversampling_ratio(struct bma400_data * data,int val)418 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data,
419 int val)
420 {
421 unsigned int acc_config;
422 int ret;
423
424 if (val & ~BMA400_TWO_BITS_MASK)
425 return -EINVAL;
426
427 /*
428 * The oversampling ratio is stored in a different register
429 * based on the power-mode.
430 */
431 switch (data->power_mode) {
432 case POWER_MODE_LOW:
433 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG,
434 &acc_config);
435 if (ret)
436 return ret;
437
438 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
439 (acc_config & ~BMA400_LP_OSR_MASK) |
440 (val << BMA400_LP_OSR_SHIFT));
441 if (ret) {
442 dev_err(data->dev, "Failed to write out OSR\n");
443 return ret;
444 }
445
446 data->oversampling_ratio = val;
447 return 0;
448 case POWER_MODE_NORMAL:
449 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG,
450 &acc_config);
451 if (ret)
452 return ret;
453
454 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
455 (acc_config & ~BMA400_NP_OSR_MASK) |
456 (val << BMA400_NP_OSR_SHIFT));
457 if (ret) {
458 dev_err(data->dev, "Failed to write out OSR\n");
459 return ret;
460 }
461
462 data->oversampling_ratio = val;
463 return 0;
464 default:
465 return -EINVAL;
466 }
467 return ret;
468 }
469
bma400_accel_scale_to_raw(struct bma400_data * data,unsigned int val)470 static int bma400_accel_scale_to_raw(struct bma400_data *data,
471 unsigned int val)
472 {
473 int raw;
474
475 if (val == 0)
476 return -EINVAL;
477
478 /* Note this works because BMA400_SCALE_MIN is odd */
479 raw = __ffs(val);
480
481 if (val >> raw != BMA400_SCALE_MIN)
482 return -EINVAL;
483
484 return raw;
485 }
486
bma400_get_accel_scale(struct bma400_data * data)487 static int bma400_get_accel_scale(struct bma400_data *data)
488 {
489 unsigned int raw_scale;
490 unsigned int val;
491 int ret;
492
493 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
494 if (ret)
495 return ret;
496
497 raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT;
498 if (raw_scale > BMA400_TWO_BITS_MASK)
499 return -EINVAL;
500
501 data->scale = BMA400_SCALE_MIN << raw_scale;
502
503 return 0;
504 }
505
bma400_set_accel_scale(struct bma400_data * data,unsigned int val)506 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val)
507 {
508 unsigned int acc_config;
509 int raw;
510 int ret;
511
512 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config);
513 if (ret)
514 return ret;
515
516 raw = bma400_accel_scale_to_raw(data, val);
517 if (raw < 0)
518 return raw;
519
520 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
521 (acc_config & ~BMA400_ACC_SCALE_MASK) |
522 (raw << BMA400_SCALE_SHIFT));
523 if (ret)
524 return ret;
525
526 data->scale = val;
527 return 0;
528 }
529
bma400_get_power_mode(struct bma400_data * data)530 static int bma400_get_power_mode(struct bma400_data *data)
531 {
532 unsigned int val;
533 int ret;
534
535 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val);
536 if (ret) {
537 dev_err(data->dev, "Failed to read status register\n");
538 return ret;
539 }
540
541 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK;
542 return 0;
543 }
544
bma400_set_power_mode(struct bma400_data * data,enum bma400_power_mode mode)545 static int bma400_set_power_mode(struct bma400_data *data,
546 enum bma400_power_mode mode)
547 {
548 unsigned int val;
549 int ret;
550
551 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
552 if (ret)
553 return ret;
554
555 if (data->power_mode == mode)
556 return 0;
557
558 if (mode == POWER_MODE_INVALID)
559 return -EINVAL;
560
561 /* Preserve the low-power oversample ratio etc */
562 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
563 mode | (val & ~BMA400_TWO_BITS_MASK));
564 if (ret) {
565 dev_err(data->dev, "Failed to write to power-mode\n");
566 return ret;
567 }
568
569 data->power_mode = mode;
570
571 /*
572 * Update our cached osr and odr based on the new
573 * power-mode.
574 */
575 bma400_get_accel_output_data_rate(data);
576 bma400_get_accel_oversampling_ratio(data);
577 return 0;
578 }
579
bma400_init_tables(void)580 static void bma400_init_tables(void)
581 {
582 int raw;
583 int i;
584
585 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) {
586 raw = (i / 2) + 5;
587 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i],
588 &bma400_sample_freqs[i + 1]);
589 }
590
591 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) {
592 raw = i / 2;
593 bma400_scales[i] = 0;
594 bma400_scales[i + 1] = BMA400_SCALE_MIN << raw;
595 }
596 }
597
bma400_regulators_disable(void * data_ptr)598 static void bma400_regulators_disable(void *data_ptr)
599 {
600 struct bma400_data *data = data_ptr;
601
602 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
603 }
604
bma400_power_disable(void * data_ptr)605 static void bma400_power_disable(void *data_ptr)
606 {
607 struct bma400_data *data = data_ptr;
608 int ret;
609
610 mutex_lock(&data->mutex);
611 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP);
612 mutex_unlock(&data->mutex);
613 if (ret)
614 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n",
615 ERR_PTR(ret));
616 }
617
bma400_init(struct bma400_data * data)618 static int bma400_init(struct bma400_data *data)
619 {
620 unsigned int val;
621 int ret;
622
623 /* Try to read chip_id register. It must return 0x90. */
624 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
625 if (ret) {
626 dev_err(data->dev, "Failed to read chip id register\n");
627 return ret;
628 }
629
630 if (val != BMA400_ID_REG_VAL) {
631 dev_err(data->dev, "Chip ID mismatch\n");
632 return -ENODEV;
633 }
634
635 data->regulators[BMA400_VDD_REGULATOR].supply = "vdd";
636 data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio";
637 ret = devm_regulator_bulk_get(data->dev,
638 ARRAY_SIZE(data->regulators),
639 data->regulators);
640 if (ret) {
641 if (ret != -EPROBE_DEFER)
642 dev_err(data->dev,
643 "Failed to get regulators: %d\n",
644 ret);
645
646 return ret;
647 }
648 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
649 data->regulators);
650 if (ret) {
651 dev_err(data->dev, "Failed to enable regulators: %d\n",
652 ret);
653 return ret;
654 }
655
656 ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data);
657 if (ret)
658 return ret;
659
660 ret = bma400_get_power_mode(data);
661 if (ret) {
662 dev_err(data->dev, "Failed to get the initial power-mode\n");
663 return ret;
664 }
665
666 if (data->power_mode != POWER_MODE_NORMAL) {
667 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL);
668 if (ret) {
669 dev_err(data->dev, "Failed to wake up the device\n");
670 return ret;
671 }
672 /*
673 * TODO: The datasheet waits 1500us here in the example, but
674 * lists 2/ODR as the wakeup time.
675 */
676 usleep_range(1500, 2000);
677 }
678
679 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data);
680 if (ret)
681 return ret;
682
683 bma400_init_tables();
684
685 ret = bma400_get_accel_output_data_rate(data);
686 if (ret)
687 return ret;
688
689 ret = bma400_get_accel_oversampling_ratio(data);
690 if (ret)
691 return ret;
692
693 ret = bma400_get_accel_scale(data);
694 if (ret)
695 return ret;
696
697 /* Configure INT1 pin to open drain */
698 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06);
699 if (ret)
700 return ret;
701 /*
702 * Once the interrupt engine is supported we might use the
703 * data_src_reg, but for now ensure this is set to the
704 * variable ODR filter selectable by the sample frequency
705 * channel.
706 */
707 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00);
708 }
709
bma400_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)710 static int bma400_read_raw(struct iio_dev *indio_dev,
711 struct iio_chan_spec const *chan, int *val,
712 int *val2, long mask)
713 {
714 struct bma400_data *data = iio_priv(indio_dev);
715 int ret;
716
717 switch (mask) {
718 case IIO_CHAN_INFO_PROCESSED:
719 mutex_lock(&data->mutex);
720 ret = bma400_get_temp_reg(data, val, val2);
721 mutex_unlock(&data->mutex);
722 return ret;
723 case IIO_CHAN_INFO_RAW:
724 mutex_lock(&data->mutex);
725 ret = bma400_get_accel_reg(data, chan, val);
726 mutex_unlock(&data->mutex);
727 return ret;
728 case IIO_CHAN_INFO_SAMP_FREQ:
729 switch (chan->type) {
730 case IIO_ACCEL:
731 if (data->sample_freq.hz < 0)
732 return -EINVAL;
733
734 *val = data->sample_freq.hz;
735 *val2 = data->sample_freq.uhz;
736 return IIO_VAL_INT_PLUS_MICRO;
737 case IIO_TEMP:
738 /*
739 * Runs at a fixed sampling frequency. See Section 4.4
740 * of the datasheet.
741 */
742 *val = 6;
743 *val2 = 250000;
744 return IIO_VAL_INT_PLUS_MICRO;
745 default:
746 return -EINVAL;
747 }
748 case IIO_CHAN_INFO_SCALE:
749 *val = 0;
750 *val2 = data->scale;
751 return IIO_VAL_INT_PLUS_MICRO;
752 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
753 /*
754 * TODO: We could avoid this logic and returning -EINVAL here if
755 * we set both the low-power and normal mode OSR registers when
756 * we configure the device.
757 */
758 if (data->oversampling_ratio < 0)
759 return -EINVAL;
760
761 *val = data->oversampling_ratio;
762 return IIO_VAL_INT;
763 default:
764 return -EINVAL;
765 }
766 }
767
bma400_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)768 static int bma400_read_avail(struct iio_dev *indio_dev,
769 struct iio_chan_spec const *chan,
770 const int **vals, int *type, int *length,
771 long mask)
772 {
773 switch (mask) {
774 case IIO_CHAN_INFO_SCALE:
775 *type = IIO_VAL_INT_PLUS_MICRO;
776 *vals = bma400_scales;
777 *length = ARRAY_SIZE(bma400_scales);
778 return IIO_AVAIL_LIST;
779 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
780 *type = IIO_VAL_INT;
781 *vals = bma400_osr_range;
782 *length = ARRAY_SIZE(bma400_osr_range);
783 return IIO_AVAIL_RANGE;
784 case IIO_CHAN_INFO_SAMP_FREQ:
785 *type = IIO_VAL_INT_PLUS_MICRO;
786 *vals = bma400_sample_freqs;
787 *length = ARRAY_SIZE(bma400_sample_freqs);
788 return IIO_AVAIL_LIST;
789 default:
790 return -EINVAL;
791 }
792 }
793
bma400_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)794 static int bma400_write_raw(struct iio_dev *indio_dev,
795 struct iio_chan_spec const *chan, int val, int val2,
796 long mask)
797 {
798 struct bma400_data *data = iio_priv(indio_dev);
799 int ret;
800
801 switch (mask) {
802 case IIO_CHAN_INFO_SAMP_FREQ:
803 /*
804 * The sample frequency is readonly for the temperature
805 * register and a fixed value in low-power mode.
806 */
807 if (chan->type != IIO_ACCEL)
808 return -EINVAL;
809
810 mutex_lock(&data->mutex);
811 ret = bma400_set_accel_output_data_rate(data, val, val2);
812 mutex_unlock(&data->mutex);
813 return ret;
814 case IIO_CHAN_INFO_SCALE:
815 if (val != 0 ||
816 val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX)
817 return -EINVAL;
818
819 mutex_lock(&data->mutex);
820 ret = bma400_set_accel_scale(data, val2);
821 mutex_unlock(&data->mutex);
822 return ret;
823 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
824 mutex_lock(&data->mutex);
825 ret = bma400_set_accel_oversampling_ratio(data, val);
826 mutex_unlock(&data->mutex);
827 return ret;
828 default:
829 return -EINVAL;
830 }
831 }
832
bma400_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)833 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev,
834 struct iio_chan_spec const *chan,
835 long mask)
836 {
837 switch (mask) {
838 case IIO_CHAN_INFO_SAMP_FREQ:
839 return IIO_VAL_INT_PLUS_MICRO;
840 case IIO_CHAN_INFO_SCALE:
841 return IIO_VAL_INT_PLUS_MICRO;
842 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
843 return IIO_VAL_INT;
844 default:
845 return -EINVAL;
846 }
847 }
848
bma400_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)849 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig,
850 bool state)
851 {
852 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
853 struct bma400_data *data = iio_priv(indio_dev);
854 int ret;
855
856 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG,
857 BMA400_INT_DRDY_MSK,
858 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
859 if (ret)
860 return ret;
861
862 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG,
863 BMA400_INT_DRDY_MSK,
864 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
865 }
866
867 static const unsigned long bma400_avail_scan_masks[] = {
868 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z),
869 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z)
870 | BIT(BMA400_TEMP),
871 0
872 };
873
874 static const struct iio_info bma400_info = {
875 .read_raw = bma400_read_raw,
876 .read_avail = bma400_read_avail,
877 .write_raw = bma400_write_raw,
878 .write_raw_get_fmt = bma400_write_raw_get_fmt,
879 };
880
881 static const struct iio_trigger_ops bma400_trigger_ops = {
882 .set_trigger_state = &bma400_data_rdy_trigger_set_state,
883 .validate_device = &iio_trigger_validate_own_device,
884 };
885
bma400_trigger_handler(int irq,void * p)886 static irqreturn_t bma400_trigger_handler(int irq, void *p)
887 {
888 struct iio_poll_func *pf = p;
889 struct iio_dev *indio_dev = pf->indio_dev;
890 struct bma400_data *data = iio_priv(indio_dev);
891 int ret, temp;
892
893 /* Lock to protect the data->buffer */
894 mutex_lock(&data->mutex);
895
896 /* bulk read six registers, with the base being the LSB register */
897 ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG,
898 &data->buffer.buff, sizeof(data->buffer.buff));
899 if (ret)
900 goto unlock_err;
901
902 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) {
903 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp);
904 if (ret)
905 goto unlock_err;
906
907 data->buffer.temperature = temp;
908 }
909
910 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
911 iio_get_time_ns(indio_dev));
912
913 mutex_unlock(&data->mutex);
914 iio_trigger_notify_done(indio_dev->trig);
915 return IRQ_HANDLED;
916
917 unlock_err:
918 mutex_unlock(&data->mutex);
919 return IRQ_NONE;
920 }
921
bma400_interrupt(int irq,void * private)922 static irqreturn_t bma400_interrupt(int irq, void *private)
923 {
924 struct iio_dev *indio_dev = private;
925 struct bma400_data *data = iio_priv(indio_dev);
926 int ret;
927
928 /* Lock to protect the data->status */
929 mutex_lock(&data->mutex);
930 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG,
931 &data->status,
932 sizeof(data->status));
933 /*
934 * if none of the bit is set in the status register then it is
935 * spurious interrupt.
936 */
937 if (ret || !data->status)
938 goto unlock_err;
939
940 if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) {
941 mutex_unlock(&data->mutex);
942 iio_trigger_poll_chained(data->trig);
943 return IRQ_HANDLED;
944 }
945
946 unlock_err:
947 mutex_unlock(&data->mutex);
948 return IRQ_NONE;
949 }
950
bma400_probe(struct device * dev,struct regmap * regmap,int irq,const char * name)951 int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
952 const char *name)
953 {
954 struct iio_dev *indio_dev;
955 struct bma400_data *data;
956 int ret;
957
958 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
959 if (!indio_dev)
960 return -ENOMEM;
961
962 data = iio_priv(indio_dev);
963 data->regmap = regmap;
964 data->dev = dev;
965
966 ret = bma400_init(data);
967 if (ret)
968 return ret;
969
970 ret = iio_read_mount_matrix(dev, &data->orientation);
971 if (ret)
972 return ret;
973
974 mutex_init(&data->mutex);
975 indio_dev->name = name;
976 indio_dev->info = &bma400_info;
977 indio_dev->channels = bma400_channels;
978 indio_dev->num_channels = ARRAY_SIZE(bma400_channels);
979 indio_dev->available_scan_masks = bma400_avail_scan_masks;
980 indio_dev->modes = INDIO_DIRECT_MODE;
981
982 if (irq > 0) {
983 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
984 indio_dev->name,
985 iio_device_id(indio_dev));
986 if (!data->trig)
987 return -ENOMEM;
988
989 data->trig->ops = &bma400_trigger_ops;
990 iio_trigger_set_drvdata(data->trig, indio_dev);
991
992 ret = devm_iio_trigger_register(data->dev, data->trig);
993 if (ret)
994 return dev_err_probe(data->dev, ret,
995 "iio trigger register fail\n");
996
997 indio_dev->trig = iio_trigger_get(data->trig);
998 ret = devm_request_threaded_irq(dev, irq, NULL,
999 &bma400_interrupt,
1000 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1001 indio_dev->name, indio_dev);
1002 if (ret)
1003 return dev_err_probe(data->dev, ret,
1004 "request irq %d failed\n", irq);
1005 }
1006
1007 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1008 &bma400_trigger_handler, NULL);
1009 if (ret)
1010 return dev_err_probe(data->dev, ret,
1011 "iio triggered buffer setup failed\n");
1012
1013 return devm_iio_device_register(dev, indio_dev);
1014 }
1015 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400);
1016
1017 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>");
1018 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core");
1019 MODULE_LICENSE("GPL");
1020