1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4 *
5 * Copyright (c) 2010 Ericsson AB.
6 *
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8 *
9 * JC42.4 compliant temperature sensors are typically used on memory modules.
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/slab.h>
16 #include <linux/jiffies.h>
17 #include <linux/i2c.h>
18 #include <linux/hwmon.h>
19 #include <linux/err.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22
23 /* Addresses to scan */
24 static const unsigned short normal_i2c[] = {
25 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
26
27 /* JC42 registers. All registers are 16 bit. */
28 #define JC42_REG_CAP 0x00
29 #define JC42_REG_CONFIG 0x01
30 #define JC42_REG_TEMP_UPPER 0x02
31 #define JC42_REG_TEMP_LOWER 0x03
32 #define JC42_REG_TEMP_CRITICAL 0x04
33 #define JC42_REG_TEMP 0x05
34 #define JC42_REG_MANID 0x06
35 #define JC42_REG_DEVICEID 0x07
36 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
37
38 /* Status bits in temperature register */
39 #define JC42_ALARM_CRIT_BIT 15
40 #define JC42_ALARM_MAX_BIT 14
41 #define JC42_ALARM_MIN_BIT 13
42
43 /* Configuration register defines */
44 #define JC42_CFG_CRIT_ONLY (1 << 2)
45 #define JC42_CFG_TCRIT_LOCK (1 << 6)
46 #define JC42_CFG_EVENT_LOCK (1 << 7)
47 #define JC42_CFG_SHUTDOWN (1 << 8)
48 #define JC42_CFG_HYST_SHIFT 9
49 #define JC42_CFG_HYST_MASK (0x03 << 9)
50
51 /* Capabilities */
52 #define JC42_CAP_RANGE (1 << 2)
53
54 /* Manufacturer IDs */
55 #define ADT_MANID 0x11d4 /* Analog Devices */
56 #define ATMEL_MANID 0x001f /* Atmel */
57 #define ATMEL_MANID2 0x1114 /* Atmel */
58 #define MAX_MANID 0x004d /* Maxim */
59 #define IDT_MANID 0x00b3 /* IDT */
60 #define MCP_MANID 0x0054 /* Microchip */
61 #define NXP_MANID 0x1131 /* NXP Semiconductors */
62 #define ONS_MANID 0x1b09 /* ON Semiconductor */
63 #define STM_MANID 0x104a /* ST Microelectronics */
64 #define GT_MANID 0x1c68 /* Giantec */
65 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
66 #define SI_MANID 0x1c85 /* Seiko Instruments */
67
68 /* SMBUS register */
69 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
70
71 /* Supported chips */
72
73 /* Analog Devices */
74 #define ADT7408_DEVID 0x0801
75 #define ADT7408_DEVID_MASK 0xffff
76
77 /* Atmel */
78 #define AT30TS00_DEVID 0x8201
79 #define AT30TS00_DEVID_MASK 0xffff
80
81 #define AT30TSE004_DEVID 0x2200
82 #define AT30TSE004_DEVID_MASK 0xffff
83
84 /* Giantec */
85 #define GT30TS00_DEVID 0x2200
86 #define GT30TS00_DEVID_MASK 0xff00
87
88 #define GT34TS02_DEVID 0x3300
89 #define GT34TS02_DEVID_MASK 0xff00
90
91 /* IDT */
92 #define TSE2004_DEVID 0x2200
93 #define TSE2004_DEVID_MASK 0xff00
94
95 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
96 #define TS3000_DEVID_MASK 0xff00
97
98 #define TS3001_DEVID 0x3000
99 #define TS3001_DEVID_MASK 0xff00
100
101 /* Maxim */
102 #define MAX6604_DEVID 0x3e00
103 #define MAX6604_DEVID_MASK 0xffff
104
105 /* Microchip */
106 #define MCP9804_DEVID 0x0200
107 #define MCP9804_DEVID_MASK 0xfffc
108
109 #define MCP9808_DEVID 0x0400
110 #define MCP9808_DEVID_MASK 0xfffc
111
112 #define MCP98242_DEVID 0x2000
113 #define MCP98242_DEVID_MASK 0xfffc
114
115 #define MCP98243_DEVID 0x2100
116 #define MCP98243_DEVID_MASK 0xfffc
117
118 #define MCP98244_DEVID 0x2200
119 #define MCP98244_DEVID_MASK 0xfffc
120
121 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
122 #define MCP9843_DEVID_MASK 0xfffe
123
124 /* NXP */
125 #define SE97_DEVID 0xa200
126 #define SE97_DEVID_MASK 0xfffc
127
128 #define SE98_DEVID 0xa100
129 #define SE98_DEVID_MASK 0xfffc
130
131 /* ON Semiconductor */
132 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
133 #define CAT6095_DEVID_MASK 0xffe0
134
135 #define CAT34TS02C_DEVID 0x0a00
136 #define CAT34TS02C_DEVID_MASK 0xfff0
137
138 #define CAT34TS04_DEVID 0x2200
139 #define CAT34TS04_DEVID_MASK 0xfff0
140
141 #define N34TS04_DEVID 0x2230
142 #define N34TS04_DEVID_MASK 0xfff0
143
144 /* ST Microelectronics */
145 #define STTS424_DEVID 0x0101
146 #define STTS424_DEVID_MASK 0xffff
147
148 #define STTS424E_DEVID 0x0000
149 #define STTS424E_DEVID_MASK 0xfffe
150
151 #define STTS2002_DEVID 0x0300
152 #define STTS2002_DEVID_MASK 0xffff
153
154 #define STTS2004_DEVID 0x2201
155 #define STTS2004_DEVID_MASK 0xffff
156
157 #define STTS3000_DEVID 0x0200
158 #define STTS3000_DEVID_MASK 0xffff
159
160 /* Seiko Instruments */
161 #define S34TS04A_DEVID 0x2221
162 #define S34TS04A_DEVID_MASK 0xffff
163
164 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
165
166 struct jc42_chips {
167 u16 manid;
168 u16 devid;
169 u16 devid_mask;
170 };
171
172 static struct jc42_chips jc42_chips[] = {
173 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
174 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
175 { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
176 { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
177 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
178 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
179 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
180 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
181 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
182 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
183 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
184 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
185 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
186 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
187 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
188 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
189 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
190 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
191 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
192 { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
193 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
194 { SI_MANID, S34TS04A_DEVID, S34TS04A_DEVID_MASK },
195 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
196 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
197 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
198 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
199 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
200 };
201
202 enum temp_index {
203 t_input = 0,
204 t_crit,
205 t_min,
206 t_max,
207 t_num_temp
208 };
209
210 static const u8 temp_regs[t_num_temp] = {
211 [t_input] = JC42_REG_TEMP,
212 [t_crit] = JC42_REG_TEMP_CRITICAL,
213 [t_min] = JC42_REG_TEMP_LOWER,
214 [t_max] = JC42_REG_TEMP_UPPER,
215 };
216
217 /* Each client has this additional data */
218 struct jc42_data {
219 struct i2c_client *client;
220 struct mutex update_lock; /* protect register access */
221 bool extended; /* true if extended range supported */
222 bool valid;
223 unsigned long last_updated; /* In jiffies */
224 u16 orig_config; /* original configuration */
225 u16 config; /* current configuration */
226 u16 temp[t_num_temp];/* Temperatures */
227 };
228
229 #define JC42_TEMP_MIN_EXTENDED (-40000)
230 #define JC42_TEMP_MIN 0
231 #define JC42_TEMP_MAX 125000
232
jc42_temp_to_reg(long temp,bool extended)233 static u16 jc42_temp_to_reg(long temp, bool extended)
234 {
235 int ntemp = clamp_val(temp,
236 extended ? JC42_TEMP_MIN_EXTENDED :
237 JC42_TEMP_MIN, JC42_TEMP_MAX);
238
239 /* convert from 0.001 to 0.0625 resolution */
240 return (ntemp * 2 / 125) & 0x1fff;
241 }
242
jc42_temp_from_reg(s16 reg)243 static int jc42_temp_from_reg(s16 reg)
244 {
245 reg = sign_extend32(reg, 12);
246
247 /* convert from 0.0625 to 0.001 resolution */
248 return reg * 125 / 2;
249 }
250
jc42_update_device(struct device * dev)251 static struct jc42_data *jc42_update_device(struct device *dev)
252 {
253 struct jc42_data *data = dev_get_drvdata(dev);
254 struct i2c_client *client = data->client;
255 struct jc42_data *ret = data;
256 int i, val;
257
258 mutex_lock(&data->update_lock);
259
260 if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
261 for (i = 0; i < t_num_temp; i++) {
262 val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
263 if (val < 0) {
264 ret = ERR_PTR(val);
265 goto abort;
266 }
267 data->temp[i] = val;
268 }
269 data->last_updated = jiffies;
270 data->valid = true;
271 }
272 abort:
273 mutex_unlock(&data->update_lock);
274 return ret;
275 }
276
jc42_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)277 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
278 u32 attr, int channel, long *val)
279 {
280 struct jc42_data *data = jc42_update_device(dev);
281 int temp, hyst;
282
283 if (IS_ERR(data))
284 return PTR_ERR(data);
285
286 switch (attr) {
287 case hwmon_temp_input:
288 *val = jc42_temp_from_reg(data->temp[t_input]);
289 return 0;
290 case hwmon_temp_min:
291 *val = jc42_temp_from_reg(data->temp[t_min]);
292 return 0;
293 case hwmon_temp_max:
294 *val = jc42_temp_from_reg(data->temp[t_max]);
295 return 0;
296 case hwmon_temp_crit:
297 *val = jc42_temp_from_reg(data->temp[t_crit]);
298 return 0;
299 case hwmon_temp_max_hyst:
300 temp = jc42_temp_from_reg(data->temp[t_max]);
301 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
302 >> JC42_CFG_HYST_SHIFT];
303 *val = temp - hyst;
304 return 0;
305 case hwmon_temp_crit_hyst:
306 temp = jc42_temp_from_reg(data->temp[t_crit]);
307 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
308 >> JC42_CFG_HYST_SHIFT];
309 *val = temp - hyst;
310 return 0;
311 case hwmon_temp_min_alarm:
312 *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
313 return 0;
314 case hwmon_temp_max_alarm:
315 *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
316 return 0;
317 case hwmon_temp_crit_alarm:
318 *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
319 return 0;
320 default:
321 return -EOPNOTSUPP;
322 }
323 }
324
jc42_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)325 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
326 u32 attr, int channel, long val)
327 {
328 struct jc42_data *data = dev_get_drvdata(dev);
329 struct i2c_client *client = data->client;
330 int diff, hyst;
331 int ret;
332
333 mutex_lock(&data->update_lock);
334
335 switch (attr) {
336 case hwmon_temp_min:
337 data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
338 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
339 data->temp[t_min]);
340 break;
341 case hwmon_temp_max:
342 data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
343 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
344 data->temp[t_max]);
345 break;
346 case hwmon_temp_crit:
347 data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
348 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
349 data->temp[t_crit]);
350 break;
351 case hwmon_temp_crit_hyst:
352 /*
353 * JC42.4 compliant chips only support four hysteresis values.
354 * Pick best choice and go from there.
355 */
356 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
357 : JC42_TEMP_MIN) - 6000,
358 JC42_TEMP_MAX);
359 diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
360 hyst = 0;
361 if (diff > 0) {
362 if (diff < 2250)
363 hyst = 1; /* 1.5 degrees C */
364 else if (diff < 4500)
365 hyst = 2; /* 3.0 degrees C */
366 else
367 hyst = 3; /* 6.0 degrees C */
368 }
369 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
370 (hyst << JC42_CFG_HYST_SHIFT);
371 ret = i2c_smbus_write_word_swapped(data->client,
372 JC42_REG_CONFIG,
373 data->config);
374 break;
375 default:
376 ret = -EOPNOTSUPP;
377 break;
378 }
379
380 mutex_unlock(&data->update_lock);
381
382 return ret;
383 }
384
jc42_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)385 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
386 u32 attr, int channel)
387 {
388 const struct jc42_data *data = _data;
389 unsigned int config = data->config;
390 umode_t mode = 0444;
391
392 switch (attr) {
393 case hwmon_temp_min:
394 case hwmon_temp_max:
395 if (!(config & JC42_CFG_EVENT_LOCK))
396 mode |= 0200;
397 break;
398 case hwmon_temp_crit:
399 if (!(config & JC42_CFG_TCRIT_LOCK))
400 mode |= 0200;
401 break;
402 case hwmon_temp_crit_hyst:
403 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
404 mode |= 0200;
405 break;
406 case hwmon_temp_input:
407 case hwmon_temp_max_hyst:
408 case hwmon_temp_min_alarm:
409 case hwmon_temp_max_alarm:
410 case hwmon_temp_crit_alarm:
411 break;
412 default:
413 mode = 0;
414 break;
415 }
416 return mode;
417 }
418
419 /* Return 0 if detection is successful, -ENODEV otherwise */
jc42_detect(struct i2c_client * client,struct i2c_board_info * info)420 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
421 {
422 struct i2c_adapter *adapter = client->adapter;
423 int i, config, cap, manid, devid;
424
425 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
426 I2C_FUNC_SMBUS_WORD_DATA))
427 return -ENODEV;
428
429 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
430 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
431 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
432 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
433
434 if (cap < 0 || config < 0 || manid < 0 || devid < 0)
435 return -ENODEV;
436
437 if ((cap & 0xff00) || (config & 0xf800))
438 return -ENODEV;
439
440 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
441 struct jc42_chips *chip = &jc42_chips[i];
442 if (manid == chip->manid &&
443 (devid & chip->devid_mask) == chip->devid) {
444 strlcpy(info->type, "jc42", I2C_NAME_SIZE);
445 return 0;
446 }
447 }
448 return -ENODEV;
449 }
450
451 static const struct hwmon_channel_info *jc42_info[] = {
452 HWMON_CHANNEL_INFO(chip,
453 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
454 HWMON_CHANNEL_INFO(temp,
455 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
456 HWMON_T_CRIT | HWMON_T_MAX_HYST |
457 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
458 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
459 NULL
460 };
461
462 static const struct hwmon_ops jc42_hwmon_ops = {
463 .is_visible = jc42_is_visible,
464 .read = jc42_read,
465 .write = jc42_write,
466 };
467
468 static const struct hwmon_chip_info jc42_chip_info = {
469 .ops = &jc42_hwmon_ops,
470 .info = jc42_info,
471 };
472
jc42_probe(struct i2c_client * client)473 static int jc42_probe(struct i2c_client *client)
474 {
475 struct device *dev = &client->dev;
476 struct device *hwmon_dev;
477 struct jc42_data *data;
478 int config, cap;
479
480 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
481 if (!data)
482 return -ENOMEM;
483
484 data->client = client;
485 i2c_set_clientdata(client, data);
486 mutex_init(&data->update_lock);
487
488 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
489 if (cap < 0)
490 return cap;
491
492 data->extended = !!(cap & JC42_CAP_RANGE);
493
494 if (device_property_read_bool(dev, "smbus-timeout-disable")) {
495 int smbus;
496
497 /*
498 * Not all chips support this register, but from a
499 * quick read of various datasheets no chip appears
500 * incompatible with the below attempt to disable
501 * the timeout. And the whole thing is opt-in...
502 */
503 smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
504 if (smbus < 0)
505 return smbus;
506 i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
507 smbus | SMBUS_STMOUT);
508 }
509
510 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
511 if (config < 0)
512 return config;
513
514 data->orig_config = config;
515 if (config & JC42_CFG_SHUTDOWN) {
516 config &= ~JC42_CFG_SHUTDOWN;
517 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
518 }
519 data->config = config;
520
521 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
522 data, &jc42_chip_info,
523 NULL);
524 return PTR_ERR_OR_ZERO(hwmon_dev);
525 }
526
jc42_remove(struct i2c_client * client)527 static int jc42_remove(struct i2c_client *client)
528 {
529 struct jc42_data *data = i2c_get_clientdata(client);
530
531 /* Restore original configuration except hysteresis */
532 if ((data->config & ~JC42_CFG_HYST_MASK) !=
533 (data->orig_config & ~JC42_CFG_HYST_MASK)) {
534 int config;
535
536 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
537 | (data->config & JC42_CFG_HYST_MASK);
538 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
539 }
540 return 0;
541 }
542
543 #ifdef CONFIG_PM
544
jc42_suspend(struct device * dev)545 static int jc42_suspend(struct device *dev)
546 {
547 struct jc42_data *data = dev_get_drvdata(dev);
548
549 data->config |= JC42_CFG_SHUTDOWN;
550 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
551 data->config);
552 return 0;
553 }
554
jc42_resume(struct device * dev)555 static int jc42_resume(struct device *dev)
556 {
557 struct jc42_data *data = dev_get_drvdata(dev);
558
559 data->config &= ~JC42_CFG_SHUTDOWN;
560 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
561 data->config);
562 return 0;
563 }
564
565 static const struct dev_pm_ops jc42_dev_pm_ops = {
566 .suspend = jc42_suspend,
567 .resume = jc42_resume,
568 };
569
570 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
571 #else
572 #define JC42_DEV_PM_OPS NULL
573 #endif /* CONFIG_PM */
574
575 static const struct i2c_device_id jc42_id[] = {
576 { "jc42", 0 },
577 { }
578 };
579 MODULE_DEVICE_TABLE(i2c, jc42_id);
580
581 #ifdef CONFIG_OF
582 static const struct of_device_id jc42_of_ids[] = {
583 { .compatible = "jedec,jc-42.4-temp", },
584 { }
585 };
586 MODULE_DEVICE_TABLE(of, jc42_of_ids);
587 #endif
588
589 static struct i2c_driver jc42_driver = {
590 .class = I2C_CLASS_SPD | I2C_CLASS_HWMON,
591 .driver = {
592 .name = "jc42",
593 .pm = JC42_DEV_PM_OPS,
594 .of_match_table = of_match_ptr(jc42_of_ids),
595 },
596 .probe_new = jc42_probe,
597 .remove = jc42_remove,
598 .id_table = jc42_id,
599 .detect = jc42_detect,
600 .address_list = normal_i2c,
601 };
602
603 module_i2c_driver(jc42_driver);
604
605 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
606 MODULE_DESCRIPTION("JC42 driver");
607 MODULE_LICENSE("GPL");
608