1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2016 Maxime Ripard
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_encoder.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
23 #include <drm/drm_print.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_simple_kms_helper.h>
26
27 #include "sun4i_backend.h"
28 #include "sun4i_crtc.h"
29 #include "sun4i_drv.h"
30 #include "sun4i_hdmi.h"
31
32 static inline struct sun4i_hdmi *
drm_encoder_to_sun4i_hdmi(struct drm_encoder * encoder)33 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
34 {
35 return container_of(encoder, struct sun4i_hdmi,
36 encoder);
37 }
38
39 static inline struct sun4i_hdmi *
drm_connector_to_sun4i_hdmi(struct drm_connector * connector)40 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
41 {
42 return container_of(connector, struct sun4i_hdmi,
43 connector);
44 }
45
sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi * hdmi,struct drm_display_mode * mode)46 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
47 struct drm_display_mode *mode)
48 {
49 struct hdmi_avi_infoframe frame;
50 u8 buffer[17];
51 int i, ret;
52
53 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
54 &hdmi->connector, mode);
55 if (ret < 0) {
56 DRM_ERROR("Failed to get infoframes from mode\n");
57 return ret;
58 }
59
60 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
61 if (ret < 0) {
62 DRM_ERROR("Failed to pack infoframes\n");
63 return ret;
64 }
65
66 for (i = 0; i < sizeof(buffer); i++)
67 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
68
69 return 0;
70 }
71
sun4i_hdmi_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)72 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
73 struct drm_crtc_state *crtc_state,
74 struct drm_connector_state *conn_state)
75 {
76 struct drm_display_mode *mode = &crtc_state->mode;
77
78 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
79 return -EINVAL;
80
81 return 0;
82 }
83
sun4i_hdmi_disable(struct drm_encoder * encoder)84 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
85 {
86 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
87 u32 val;
88
89 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
90
91 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
92 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
93 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
94
95 clk_disable_unprepare(hdmi->tmds_clk);
96 }
97
sun4i_hdmi_enable(struct drm_encoder * encoder)98 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
99 {
100 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
101 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
102 struct drm_display_info *display = &hdmi->connector.display_info;
103 u32 val = 0;
104
105 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
106
107 clk_prepare_enable(hdmi->tmds_clk);
108
109 sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
110 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
112 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
113
114 val = SUN4I_HDMI_VID_CTRL_ENABLE;
115 if (display->is_hdmi)
116 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
117
118 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
119 }
120
sun4i_hdmi_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)121 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
122 struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode)
124 {
125 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
126 unsigned int x, y;
127 u32 val;
128
129 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
130 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
131
132 /* Set input sync enable */
133 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
134 hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
135
136 /*
137 * Setup output pad (?) controls
138 *
139 * This is done here instead of at probe/bind time because
140 * the controller seems to toggle some of the bits on its own.
141 *
142 * We can't just initialize the register there, we need to
143 * protect the clock bits that have already been read out and
144 * cached by the clock framework.
145 */
146 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
147 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
148 val |= hdmi->variant->pad_ctrl1_init_val;
149 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
150 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
151
152 /* Setup timing registers */
153 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
154 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
155 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
156
157 x = mode->htotal - mode->hsync_start;
158 y = mode->vtotal - mode->vsync_start;
159 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
160 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
161
162 x = mode->hsync_start - mode->hdisplay;
163 y = mode->vsync_start - mode->vdisplay;
164 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
165 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
166
167 x = mode->hsync_end - mode->hsync_start;
168 y = mode->vsync_end - mode->vsync_start;
169 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
170 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
171
172 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
173 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
174 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
175
176 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
177 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
178
179 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
180 }
181
sun4i_hdmi_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)182 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
183 const struct drm_display_mode *mode)
184 {
185 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
186 unsigned long rate = mode->clock * 1000;
187 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
188 long rounded_rate;
189
190 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
191 if (rate > 165000000)
192 return MODE_CLOCK_HIGH;
193 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
194 if (rounded_rate > 0 &&
195 max_t(unsigned long, rounded_rate, rate) -
196 min_t(unsigned long, rounded_rate, rate) < diff)
197 return MODE_OK;
198 return MODE_NOCLOCK;
199 }
200
201 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
202 .atomic_check = sun4i_hdmi_atomic_check,
203 .disable = sun4i_hdmi_disable,
204 .enable = sun4i_hdmi_enable,
205 .mode_set = sun4i_hdmi_mode_set,
206 .mode_valid = sun4i_hdmi_mode_valid,
207 };
208
sun4i_hdmi_get_modes(struct drm_connector * connector)209 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
210 {
211 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
212 struct edid *edid;
213 int ret;
214
215 edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
216 if (!edid)
217 return 0;
218
219 DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
220 connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
221
222 drm_connector_update_edid_property(connector, edid);
223 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
224 ret = drm_add_edid_modes(connector, edid);
225 kfree(edid);
226
227 return ret;
228 }
229
sun4i_hdmi_get_ddc(struct device * dev)230 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev)
231 {
232 struct device_node *phandle, *remote;
233 struct i2c_adapter *ddc;
234
235 remote = of_graph_get_remote_node(dev->of_node, 1, -1);
236 if (!remote)
237 return ERR_PTR(-EINVAL);
238
239 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0);
240 of_node_put(remote);
241 if (!phandle)
242 return ERR_PTR(-ENODEV);
243
244 ddc = of_get_i2c_adapter_by_node(phandle);
245 of_node_put(phandle);
246 if (!ddc)
247 return ERR_PTR(-EPROBE_DEFER);
248
249 return ddc;
250 }
251
252 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
253 .get_modes = sun4i_hdmi_get_modes,
254 };
255
256 static enum drm_connector_status
sun4i_hdmi_connector_detect(struct drm_connector * connector,bool force)257 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
258 {
259 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
260 unsigned long reg;
261
262 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
263 if (!(reg & SUN4I_HDMI_HPD_HIGH)) {
264 cec_phys_addr_invalidate(hdmi->cec_adap);
265 return connector_status_disconnected;
266 }
267
268 return connector_status_connected;
269 }
270
271 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
272 .detect = sun4i_hdmi_connector_detect,
273 .fill_modes = drm_helper_probe_single_connector_modes,
274 .destroy = drm_connector_cleanup,
275 .reset = drm_atomic_helper_connector_reset,
276 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
277 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
278 };
279
280 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
sun4i_hdmi_cec_pin_read(struct cec_adapter * adap)281 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
282 {
283 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
284
285 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
286 }
287
sun4i_hdmi_cec_pin_low(struct cec_adapter * adap)288 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
289 {
290 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
291
292 /* Start driving the CEC pin low */
293 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
294 }
295
sun4i_hdmi_cec_pin_high(struct cec_adapter * adap)296 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
297 {
298 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
299
300 /*
301 * Stop driving the CEC pin, the pull up will take over
302 * unless another CEC device is driving the pin low.
303 */
304 writel(0, hdmi->base + SUN4I_HDMI_CEC);
305 }
306
307 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
308 .read = sun4i_hdmi_cec_pin_read,
309 .low = sun4i_hdmi_cec_pin_low,
310 .high = sun4i_hdmi_cec_pin_high,
311 };
312 #endif
313
314 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))
315 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
316
317 /* Only difference from sun5i is AMP is 4 instead of 6 */
318 static const struct sun4i_hdmi_variant sun4i_variant = {
319 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
320 SUN4I_HDMI_PAD_CTRL0_CKEN |
321 SUN4I_HDMI_PAD_CTRL0_PWENG |
322 SUN4I_HDMI_PAD_CTRL0_PWEND |
323 SUN4I_HDMI_PAD_CTRL0_PWENC |
324 SUN4I_HDMI_PAD_CTRL0_LDODEN |
325 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
326 SUN4I_HDMI_PAD_CTRL0_BIASEN,
327 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
328 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
329 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
330 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
331 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
332 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
333 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
334 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
335 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
336 SUN4I_HDMI_PLL_CTRL_CS(7) |
337 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
338 SUN4I_HDMI_PLL_CTRL_S(7) |
339 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
340 SUN4I_HDMI_PLL_CTRL_SDIV2 |
341 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
342 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
343 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
344 SUN4I_HDMI_PLL_CTRL_BWS |
345 SUN4I_HDMI_PLL_CTRL_PLL_EN,
346
347 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
348 .ddc_clk_pre_divider = 2,
349 .ddc_clk_m_offset = 1,
350
351 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
352 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
353 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
354 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
355 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
356 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
357 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
358 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
359 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
360 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
361 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
362 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
363 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
364
365 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
366 .ddc_fifo_has_dir = true,
367 };
368
369 static const struct sun4i_hdmi_variant sun5i_variant = {
370 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
371 SUN4I_HDMI_PAD_CTRL0_CKEN |
372 SUN4I_HDMI_PAD_CTRL0_PWENG |
373 SUN4I_HDMI_PAD_CTRL0_PWEND |
374 SUN4I_HDMI_PAD_CTRL0_PWENC |
375 SUN4I_HDMI_PAD_CTRL0_LDODEN |
376 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
377 SUN4I_HDMI_PAD_CTRL0_BIASEN,
378 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
379 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
380 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
381 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
382 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
383 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
384 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
385 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
386 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
387 SUN4I_HDMI_PLL_CTRL_CS(7) |
388 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
389 SUN4I_HDMI_PLL_CTRL_S(7) |
390 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
391 SUN4I_HDMI_PLL_CTRL_SDIV2 |
392 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
393 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
394 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
395 SUN4I_HDMI_PLL_CTRL_BWS |
396 SUN4I_HDMI_PLL_CTRL_PLL_EN,
397
398 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
399 .ddc_clk_pre_divider = 2,
400 .ddc_clk_m_offset = 1,
401
402 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
403 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
404 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
405 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
406 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
407 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
408 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
409 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
410 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
411 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
412 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
413 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
414 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
415
416 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
417 .ddc_fifo_has_dir = true,
418 };
419
420 static const struct sun4i_hdmi_variant sun6i_variant = {
421 .has_ddc_parent_clk = true,
422 .has_reset_control = true,
423 .pad_ctrl0_init_val = 0xff |
424 SUN4I_HDMI_PAD_CTRL0_TXEN |
425 SUN4I_HDMI_PAD_CTRL0_CKEN |
426 SUN4I_HDMI_PAD_CTRL0_PWENG |
427 SUN4I_HDMI_PAD_CTRL0_PWEND |
428 SUN4I_HDMI_PAD_CTRL0_PWENC |
429 SUN4I_HDMI_PAD_CTRL0_LDODEN |
430 SUN4I_HDMI_PAD_CTRL0_LDOCEN,
431 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
432 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
433 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
434 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
435 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
436 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
437 SUN4I_HDMI_PAD_CTRL1_PWSDT |
438 SUN4I_HDMI_PAD_CTRL1_PWSCK |
439 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
440 SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
441 SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
442 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
443 SUN4I_HDMI_PLL_CTRL_CS(3) |
444 SUN4I_HDMI_PLL_CTRL_CP_S(10) |
445 SUN4I_HDMI_PLL_CTRL_S(4) |
446 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
447 SUN4I_HDMI_PLL_CTRL_SDIV2 |
448 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
449 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
450 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
451 SUN4I_HDMI_PLL_CTRL_PLL_EN,
452
453 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
454 .ddc_clk_pre_divider = 1,
455 .ddc_clk_m_offset = 2,
456
457 .tmds_clk_div_offset = 1,
458
459 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
460 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
461 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
462 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
463 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
464 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
465 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
466 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
467 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
468 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
469 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
470 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
471 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
472
473 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
474 .ddc_fifo_thres_incl = true,
475 };
476
477 static const struct regmap_config sun4i_hdmi_regmap_config = {
478 .reg_bits = 32,
479 .val_bits = 32,
480 .reg_stride = 4,
481 .max_register = 0x580,
482 };
483
sun4i_hdmi_bind(struct device * dev,struct device * master,void * data)484 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
485 void *data)
486 {
487 struct platform_device *pdev = to_platform_device(dev);
488 struct drm_device *drm = data;
489 struct cec_connector_info conn_info;
490 struct sun4i_drv *drv = drm->dev_private;
491 struct sun4i_hdmi *hdmi;
492 u32 reg;
493 int ret;
494
495 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
496 if (!hdmi)
497 return -ENOMEM;
498 dev_set_drvdata(dev, hdmi);
499 hdmi->dev = dev;
500 hdmi->drv = drv;
501
502 hdmi->variant = of_device_get_match_data(dev);
503 if (!hdmi->variant)
504 return -EINVAL;
505
506 hdmi->base = devm_platform_ioremap_resource(pdev, 0);
507 if (IS_ERR(hdmi->base)) {
508 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
509 return PTR_ERR(hdmi->base);
510 }
511
512 if (hdmi->variant->has_reset_control) {
513 hdmi->reset = devm_reset_control_get(dev, NULL);
514 if (IS_ERR(hdmi->reset)) {
515 dev_err(dev, "Couldn't get the HDMI reset control\n");
516 return PTR_ERR(hdmi->reset);
517 }
518
519 ret = reset_control_deassert(hdmi->reset);
520 if (ret) {
521 dev_err(dev, "Couldn't deassert HDMI reset\n");
522 return ret;
523 }
524 }
525
526 hdmi->bus_clk = devm_clk_get(dev, "ahb");
527 if (IS_ERR(hdmi->bus_clk)) {
528 dev_err(dev, "Couldn't get the HDMI bus clock\n");
529 ret = PTR_ERR(hdmi->bus_clk);
530 goto err_assert_reset;
531 }
532 clk_prepare_enable(hdmi->bus_clk);
533
534 hdmi->mod_clk = devm_clk_get(dev, "mod");
535 if (IS_ERR(hdmi->mod_clk)) {
536 dev_err(dev, "Couldn't get the HDMI mod clock\n");
537 ret = PTR_ERR(hdmi->mod_clk);
538 goto err_disable_bus_clk;
539 }
540 clk_prepare_enable(hdmi->mod_clk);
541
542 hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
543 if (IS_ERR(hdmi->pll0_clk)) {
544 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
545 ret = PTR_ERR(hdmi->pll0_clk);
546 goto err_disable_mod_clk;
547 }
548
549 hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
550 if (IS_ERR(hdmi->pll1_clk)) {
551 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
552 ret = PTR_ERR(hdmi->pll1_clk);
553 goto err_disable_mod_clk;
554 }
555
556 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
557 &sun4i_hdmi_regmap_config);
558 if (IS_ERR(hdmi->regmap)) {
559 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
560 ret = PTR_ERR(hdmi->regmap);
561 goto err_disable_mod_clk;
562 }
563
564 ret = sun4i_tmds_create(hdmi);
565 if (ret) {
566 dev_err(dev, "Couldn't create the TMDS clock\n");
567 goto err_disable_mod_clk;
568 }
569
570 if (hdmi->variant->has_ddc_parent_clk) {
571 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
572 if (IS_ERR(hdmi->ddc_parent_clk)) {
573 dev_err(dev, "Couldn't get the HDMI DDC clock\n");
574 ret = PTR_ERR(hdmi->ddc_parent_clk);
575 goto err_disable_mod_clk;
576 }
577 } else {
578 hdmi->ddc_parent_clk = hdmi->tmds_clk;
579 }
580
581 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
582
583 writel(hdmi->variant->pad_ctrl0_init_val,
584 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
585
586 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
587 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
588 reg |= hdmi->variant->pll_ctrl_init_val;
589 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
590
591 ret = sun4i_hdmi_i2c_create(dev, hdmi);
592 if (ret) {
593 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
594 goto err_disable_mod_clk;
595 }
596
597 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
598 if (IS_ERR(hdmi->ddc_i2c)) {
599 ret = PTR_ERR(hdmi->ddc_i2c);
600 if (ret == -ENODEV)
601 hdmi->ddc_i2c = NULL;
602 else
603 goto err_del_i2c_adapter;
604 }
605
606 drm_encoder_helper_add(&hdmi->encoder,
607 &sun4i_hdmi_helper_funcs);
608 ret = drm_simple_encoder_init(drm, &hdmi->encoder,
609 DRM_MODE_ENCODER_TMDS);
610 if (ret) {
611 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
612 goto err_put_ddc_i2c;
613 }
614
615 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
616 dev->of_node);
617 if (!hdmi->encoder.possible_crtcs) {
618 ret = -EPROBE_DEFER;
619 goto err_put_ddc_i2c;
620 }
621
622 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
623 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
624 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO);
625 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
626 if (ret < 0)
627 goto err_cleanup_connector;
628 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
629 hdmi->base + SUN4I_HDMI_CEC);
630 #endif
631
632 drm_connector_helper_add(&hdmi->connector,
633 &sun4i_hdmi_connector_helper_funcs);
634 ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
635 &sun4i_hdmi_connector_funcs,
636 DRM_MODE_CONNECTOR_HDMIA,
637 hdmi->ddc_i2c);
638 if (ret) {
639 dev_err(dev,
640 "Couldn't initialise the HDMI connector\n");
641 goto err_cleanup_connector;
642 }
643 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector);
644 cec_s_conn_info(hdmi->cec_adap, &conn_info);
645
646 /* There is no HPD interrupt, so we need to poll the controller */
647 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
648 DRM_CONNECTOR_POLL_DISCONNECT;
649
650 ret = cec_register_adapter(hdmi->cec_adap, dev);
651 if (ret < 0)
652 goto err_cleanup_connector;
653 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
654
655 return 0;
656
657 err_cleanup_connector:
658 cec_delete_adapter(hdmi->cec_adap);
659 drm_encoder_cleanup(&hdmi->encoder);
660 err_put_ddc_i2c:
661 i2c_put_adapter(hdmi->ddc_i2c);
662 err_del_i2c_adapter:
663 i2c_del_adapter(hdmi->i2c);
664 err_disable_mod_clk:
665 clk_disable_unprepare(hdmi->mod_clk);
666 err_disable_bus_clk:
667 clk_disable_unprepare(hdmi->bus_clk);
668 err_assert_reset:
669 reset_control_assert(hdmi->reset);
670 return ret;
671 }
672
sun4i_hdmi_unbind(struct device * dev,struct device * master,void * data)673 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
674 void *data)
675 {
676 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
677
678 cec_unregister_adapter(hdmi->cec_adap);
679 i2c_del_adapter(hdmi->i2c);
680 i2c_put_adapter(hdmi->ddc_i2c);
681 clk_disable_unprepare(hdmi->mod_clk);
682 clk_disable_unprepare(hdmi->bus_clk);
683 }
684
685 static const struct component_ops sun4i_hdmi_ops = {
686 .bind = sun4i_hdmi_bind,
687 .unbind = sun4i_hdmi_unbind,
688 };
689
sun4i_hdmi_probe(struct platform_device * pdev)690 static int sun4i_hdmi_probe(struct platform_device *pdev)
691 {
692 return component_add(&pdev->dev, &sun4i_hdmi_ops);
693 }
694
sun4i_hdmi_remove(struct platform_device * pdev)695 static int sun4i_hdmi_remove(struct platform_device *pdev)
696 {
697 component_del(&pdev->dev, &sun4i_hdmi_ops);
698
699 return 0;
700 }
701
702 static const struct of_device_id sun4i_hdmi_of_table[] = {
703 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
704 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
705 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
706 { }
707 };
708 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
709
710 static struct platform_driver sun4i_hdmi_driver = {
711 .probe = sun4i_hdmi_probe,
712 .remove = sun4i_hdmi_remove,
713 .driver = {
714 .name = "sun4i-hdmi",
715 .of_match_table = sun4i_hdmi_of_table,
716 },
717 };
718 module_platform_driver(sun4i_hdmi_driver);
719
720 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
721 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
722 MODULE_LICENSE("GPL");
723