1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "channv50.h"
23
24 #include <subdev/timer.h>
25
26 static const struct nv50_disp_mthd_list
27 gv100_disp_core_mthd_base = {
28 .mthd = 0x0000,
29 .addr = 0x000000,
30 .data = {
31 { 0x0200, 0x680200 },
32 { 0x0208, 0x680208 },
33 { 0x020c, 0x68020c },
34 { 0x0210, 0x680210 },
35 { 0x0214, 0x680214 },
36 { 0x0218, 0x680218 },
37 { 0x021c, 0x68021c },
38 {}
39 }
40 };
41
42 static const struct nv50_disp_mthd_list
43 gv100_disp_core_mthd_sor = {
44 .mthd = 0x0020,
45 .addr = 0x000020,
46 .data = {
47 { 0x0300, 0x680300 },
48 { 0x0304, 0x680304 },
49 { 0x0308, 0x680308 },
50 { 0x030c, 0x68030c },
51 {}
52 }
53 };
54
55 static const struct nv50_disp_mthd_list
56 gv100_disp_core_mthd_wndw = {
57 .mthd = 0x0080,
58 .addr = 0x000080,
59 .data = {
60 { 0x1000, 0x681000 },
61 { 0x1004, 0x681004 },
62 { 0x1008, 0x681008 },
63 { 0x100c, 0x68100c },
64 { 0x1010, 0x681010 },
65 {}
66 }
67 };
68
69 static const struct nv50_disp_mthd_list
70 gv100_disp_core_mthd_head = {
71 .mthd = 0x0400,
72 .addr = 0x000400,
73 .data = {
74 { 0x2000, 0x682000 },
75 { 0x2004, 0x682004 },
76 { 0x2008, 0x682008 },
77 { 0x200c, 0x68200c },
78 { 0x2014, 0x682014 },
79 { 0x2018, 0x682018 },
80 { 0x201c, 0x68201c },
81 { 0x2020, 0x682020 },
82 { 0x2028, 0x682028 },
83 { 0x202c, 0x68202c },
84 { 0x2030, 0x682030 },
85 { 0x2038, 0x682038 },
86 { 0x203c, 0x68203c },
87 { 0x2048, 0x682048 },
88 { 0x204c, 0x68204c },
89 { 0x2050, 0x682050 },
90 { 0x2054, 0x682054 },
91 { 0x2058, 0x682058 },
92 { 0x205c, 0x68205c },
93 { 0x2060, 0x682060 },
94 { 0x2064, 0x682064 },
95 { 0x2068, 0x682068 },
96 { 0x206c, 0x68206c },
97 { 0x2070, 0x682070 },
98 { 0x2074, 0x682074 },
99 { 0x2078, 0x682078 },
100 { 0x207c, 0x68207c },
101 { 0x2080, 0x682080 },
102 { 0x2088, 0x682088 },
103 { 0x2090, 0x682090 },
104 { 0x209c, 0x68209c },
105 { 0x20a0, 0x6820a0 },
106 { 0x20a4, 0x6820a4 },
107 { 0x20a8, 0x6820a8 },
108 { 0x20ac, 0x6820ac },
109 { 0x2180, 0x682180 },
110 { 0x2184, 0x682184 },
111 { 0x218c, 0x68218c },
112 { 0x2194, 0x682194 },
113 { 0x2198, 0x682198 },
114 { 0x219c, 0x68219c },
115 { 0x21a0, 0x6821a0 },
116 { 0x21a4, 0x6821a4 },
117 { 0x2214, 0x682214 },
118 { 0x2218, 0x682218 },
119 {}
120 }
121 };
122
123 static const struct nv50_disp_chan_mthd
124 gv100_disp_core_mthd = {
125 .name = "Core",
126 .addr = 0x000000,
127 .prev = 0x008000,
128 .data = {
129 { "Global", 1, &gv100_disp_core_mthd_base },
130 { "SOR", 4, &gv100_disp_core_mthd_sor },
131 { "WINDOW", 8, &gv100_disp_core_mthd_wndw },
132 { "HEAD", 4, &gv100_disp_core_mthd_head },
133 {}
134 }
135 };
136
137 static int
gv100_disp_core_idle(struct nv50_disp_chan * chan)138 gv100_disp_core_idle(struct nv50_disp_chan *chan)
139 {
140 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
141 nvkm_msec(device, 2000,
142 u32 stat = nvkm_rd32(device, 0x610630);
143 if ((stat & 0x001f0000) == 0x000b0000)
144 return 0;
145 );
146 return -EBUSY;
147 }
148
149 static u64
gv100_disp_core_user(struct nv50_disp_chan * chan,u64 * psize)150 gv100_disp_core_user(struct nv50_disp_chan *chan, u64 *psize)
151 {
152 *psize = 0x10000;
153 return 0x680000;
154 }
155
156 static void
gv100_disp_core_intr(struct nv50_disp_chan * chan,bool en)157 gv100_disp_core_intr(struct nv50_disp_chan *chan, bool en)
158 {
159 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
160 const u32 mask = 0x00000001;
161 const u32 data = en ? mask : 0;
162 nvkm_mask(device, 0x611dac, mask, data);
163 }
164
165 static void
gv100_disp_core_fini(struct nv50_disp_chan * chan)166 gv100_disp_core_fini(struct nv50_disp_chan *chan)
167 {
168 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
169 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000);
170 gv100_disp_core_idle(chan);
171 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000);
172 chan->suspend_put = nvkm_rd32(device, 0x680000);
173 }
174
175 static int
gv100_disp_core_init(struct nv50_disp_chan * chan)176 gv100_disp_core_init(struct nv50_disp_chan *chan)
177 {
178 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
179 struct nvkm_device *device = subdev->device;
180
181 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push));
182 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push));
183 nvkm_wr32(device, 0x610b28, 0x00000001);
184 nvkm_wr32(device, 0x610b2c, 0x00000040);
185
186 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010);
187 nvkm_wr32(device, 0x680000, chan->suspend_put);
188 nvkm_wr32(device, 0x6104e0, 0x00000013);
189 return gv100_disp_core_idle(chan);
190 }
191
192 static const struct nv50_disp_chan_func
193 gv100_disp_core = {
194 .init = gv100_disp_core_init,
195 .fini = gv100_disp_core_fini,
196 .intr = gv100_disp_core_intr,
197 .user = gv100_disp_core_user,
198 .bind = gv100_disp_dmac_bind,
199 };
200
201 int
gv100_disp_core_new(const struct nvkm_oclass * oclass,void * argv,u32 argc,struct nv50_disp * disp,struct nvkm_object ** pobject)202 gv100_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
203 struct nv50_disp *disp, struct nvkm_object **pobject)
204 {
205 return nv50_disp_core_new_(&gv100_disp_core, &gv100_disp_core_mthd,
206 disp, 0, oclass, argv, argc, pobject);
207 }
208