1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/delay.h>
8
9 #include <drm/drm_vblank.h>
10
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
17
mdp4_hw_init(struct msm_kms * kms)18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 struct drm_device *dev = mdp4_kms->dev;
22 u32 dmap_cfg, vg_cfg;
23 unsigned long clk;
24
25 pm_runtime_get_sync(dev->dev);
26
27 if (mdp4_kms->rev > 1) {
28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
30 }
31
32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
33
34 /* max read pending cmd config, 3 pending requests: */
35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
36
37 clk = clk_get_rate(mdp4_kms->clk);
38
39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
42 } else {
43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
45 }
46
47 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
48
49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
51
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
56
57 if (mdp4_kms->rev >= 2)
58 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
60
61 /* disable CSC matrix / YUV by default: */
62 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
64 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
65 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
66 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
68
69 if (mdp4_kms->rev > 1)
70 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
71
72 pm_runtime_put_sync(dev->dev);
73
74 return 0;
75 }
76
mdp4_enable_commit(struct msm_kms * kms)77 static void mdp4_enable_commit(struct msm_kms *kms)
78 {
79 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
80 mdp4_enable(mdp4_kms);
81 }
82
mdp4_disable_commit(struct msm_kms * kms)83 static void mdp4_disable_commit(struct msm_kms *kms)
84 {
85 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
86 mdp4_disable(mdp4_kms);
87 }
88
mdp4_prepare_commit(struct msm_kms * kms,struct drm_atomic_state * state)89 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
90 {
91 }
92
mdp4_flush_commit(struct msm_kms * kms,unsigned crtc_mask)93 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
94 {
95 /* TODO */
96 }
97
mdp4_wait_flush(struct msm_kms * kms,unsigned crtc_mask)98 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
99 {
100 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
101 struct drm_crtc *crtc;
102
103 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
104 mdp4_crtc_wait_for_commit_done(crtc);
105 }
106
mdp4_complete_commit(struct msm_kms * kms,unsigned crtc_mask)107 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
108 {
109 }
110
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)111 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
112 struct drm_encoder *encoder)
113 {
114 /* if we had >1 encoder, we'd need something more clever: */
115 switch (encoder->encoder_type) {
116 case DRM_MODE_ENCODER_TMDS:
117 return mdp4_dtv_round_pixclk(encoder, rate);
118 case DRM_MODE_ENCODER_LVDS:
119 case DRM_MODE_ENCODER_DSI:
120 default:
121 return rate;
122 }
123 }
124
mdp4_destroy(struct msm_kms * kms)125 static void mdp4_destroy(struct msm_kms *kms)
126 {
127 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
128 struct device *dev = mdp4_kms->dev->dev;
129 struct msm_gem_address_space *aspace = kms->aspace;
130
131 if (mdp4_kms->blank_cursor_iova)
132 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
133 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
134
135 if (aspace) {
136 aspace->mmu->funcs->detach(aspace->mmu);
137 msm_gem_address_space_put(aspace);
138 }
139
140 if (mdp4_kms->rpm_enabled)
141 pm_runtime_disable(dev);
142
143 mdp_kms_destroy(&mdp4_kms->base);
144
145 kfree(mdp4_kms);
146 }
147
148 static const struct mdp_kms_funcs kms_funcs = {
149 .base = {
150 .hw_init = mdp4_hw_init,
151 .irq_preinstall = mdp4_irq_preinstall,
152 .irq_postinstall = mdp4_irq_postinstall,
153 .irq_uninstall = mdp4_irq_uninstall,
154 .irq = mdp4_irq,
155 .enable_vblank = mdp4_enable_vblank,
156 .disable_vblank = mdp4_disable_vblank,
157 .enable_commit = mdp4_enable_commit,
158 .disable_commit = mdp4_disable_commit,
159 .prepare_commit = mdp4_prepare_commit,
160 .flush_commit = mdp4_flush_commit,
161 .wait_flush = mdp4_wait_flush,
162 .complete_commit = mdp4_complete_commit,
163 .get_format = mdp_get_format,
164 .round_pixclk = mdp4_round_pixclk,
165 .destroy = mdp4_destroy,
166 },
167 .set_irqmask = mdp4_set_irqmask,
168 };
169
mdp4_disable(struct mdp4_kms * mdp4_kms)170 int mdp4_disable(struct mdp4_kms *mdp4_kms)
171 {
172 DBG("");
173
174 clk_disable_unprepare(mdp4_kms->clk);
175 clk_disable_unprepare(mdp4_kms->pclk);
176 clk_disable_unprepare(mdp4_kms->lut_clk);
177 clk_disable_unprepare(mdp4_kms->axi_clk);
178
179 return 0;
180 }
181
mdp4_enable(struct mdp4_kms * mdp4_kms)182 int mdp4_enable(struct mdp4_kms *mdp4_kms)
183 {
184 DBG("");
185
186 clk_prepare_enable(mdp4_kms->clk);
187 clk_prepare_enable(mdp4_kms->pclk);
188 clk_prepare_enable(mdp4_kms->lut_clk);
189 clk_prepare_enable(mdp4_kms->axi_clk);
190
191 return 0;
192 }
193
194
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)195 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
196 int intf_type)
197 {
198 struct drm_device *dev = mdp4_kms->dev;
199 struct msm_drm_private *priv = dev->dev_private;
200 struct drm_encoder *encoder;
201 struct drm_connector *connector;
202 struct device_node *panel_node;
203 int dsi_id;
204 int ret;
205
206 switch (intf_type) {
207 case DRM_MODE_ENCODER_LVDS:
208 /*
209 * bail out early if there is no panel node (no need to
210 * initialize LCDC encoder and LVDS connector)
211 */
212 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
213 if (!panel_node)
214 return 0;
215
216 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
217 if (IS_ERR(encoder)) {
218 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
219 of_node_put(panel_node);
220 return PTR_ERR(encoder);
221 }
222
223 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
224 encoder->possible_crtcs = 1 << DMA_P;
225
226 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
227 if (IS_ERR(connector)) {
228 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
229 of_node_put(panel_node);
230 return PTR_ERR(connector);
231 }
232
233 break;
234 case DRM_MODE_ENCODER_TMDS:
235 encoder = mdp4_dtv_encoder_init(dev);
236 if (IS_ERR(encoder)) {
237 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
238 return PTR_ERR(encoder);
239 }
240
241 /* DTV can be hooked to DMA_E: */
242 encoder->possible_crtcs = 1 << 1;
243
244 if (priv->hdmi) {
245 /* Construct bridge/connector for HDMI: */
246 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
247 if (ret) {
248 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
249 return ret;
250 }
251 }
252
253 break;
254 case DRM_MODE_ENCODER_DSI:
255 /* only DSI1 supported for now */
256 dsi_id = 0;
257
258 if (!priv->dsi[dsi_id])
259 break;
260
261 encoder = mdp4_dsi_encoder_init(dev);
262 if (IS_ERR(encoder)) {
263 ret = PTR_ERR(encoder);
264 DRM_DEV_ERROR(dev->dev,
265 "failed to construct DSI encoder: %d\n", ret);
266 return ret;
267 }
268
269 /* TODO: Add DMA_S later? */
270 encoder->possible_crtcs = 1 << DMA_P;
271
272 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
273 if (ret) {
274 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
275 ret);
276 return ret;
277 }
278
279 break;
280 default:
281 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
282 return -EINVAL;
283 }
284
285 return 0;
286 }
287
modeset_init(struct mdp4_kms * mdp4_kms)288 static int modeset_init(struct mdp4_kms *mdp4_kms)
289 {
290 struct drm_device *dev = mdp4_kms->dev;
291 struct msm_drm_private *priv = dev->dev_private;
292 struct drm_plane *plane;
293 struct drm_crtc *crtc;
294 int i, ret;
295 static const enum mdp4_pipe rgb_planes[] = {
296 RGB1, RGB2,
297 };
298 static const enum mdp4_pipe vg_planes[] = {
299 VG1, VG2,
300 };
301 static const enum mdp4_dma mdp4_crtcs[] = {
302 DMA_P, DMA_E,
303 };
304 static const char * const mdp4_crtc_names[] = {
305 "DMA_P", "DMA_E",
306 };
307 static const int mdp4_intfs[] = {
308 DRM_MODE_ENCODER_LVDS,
309 DRM_MODE_ENCODER_DSI,
310 DRM_MODE_ENCODER_TMDS,
311 };
312
313 /* construct non-private planes: */
314 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
315 plane = mdp4_plane_init(dev, vg_planes[i], false);
316 if (IS_ERR(plane)) {
317 DRM_DEV_ERROR(dev->dev,
318 "failed to construct plane for VG%d\n", i + 1);
319 ret = PTR_ERR(plane);
320 goto fail;
321 }
322 }
323
324 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
325 plane = mdp4_plane_init(dev, rgb_planes[i], true);
326 if (IS_ERR(plane)) {
327 DRM_DEV_ERROR(dev->dev,
328 "failed to construct plane for RGB%d\n", i + 1);
329 ret = PTR_ERR(plane);
330 goto fail;
331 }
332
333 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
334 mdp4_crtcs[i]);
335 if (IS_ERR(crtc)) {
336 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
337 mdp4_crtc_names[i]);
338 ret = PTR_ERR(crtc);
339 goto fail;
340 }
341
342 priv->crtcs[priv->num_crtcs++] = crtc;
343 }
344
345 /*
346 * we currently set up two relatively fixed paths:
347 *
348 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
349 * or
350 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
351 *
352 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
353 */
354
355 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
356 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
357 if (ret) {
358 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
359 i, ret);
360 goto fail;
361 }
362 }
363
364 return 0;
365
366 fail:
367 return ret;
368 }
369
read_mdp_hw_revision(struct mdp4_kms * mdp4_kms,u32 * major,u32 * minor)370 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
371 u32 *major, u32 *minor)
372 {
373 struct drm_device *dev = mdp4_kms->dev;
374 u32 version;
375
376 mdp4_enable(mdp4_kms);
377 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
378 mdp4_disable(mdp4_kms);
379
380 *major = FIELD(version, MDP4_VERSION_MAJOR);
381 *minor = FIELD(version, MDP4_VERSION_MINOR);
382
383 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
384 }
385
mdp4_kms_init(struct drm_device * dev)386 static int mdp4_kms_init(struct drm_device *dev)
387 {
388 struct platform_device *pdev = to_platform_device(dev->dev);
389 struct mdp4_platform_config *config = mdp4_get_config(pdev);
390 struct msm_drm_private *priv = dev->dev_private;
391 struct mdp4_kms *mdp4_kms;
392 struct msm_kms *kms = NULL;
393 struct msm_gem_address_space *aspace;
394 int irq, ret;
395 u32 major, minor;
396
397 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
398 if (!mdp4_kms) {
399 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
400 return -ENOMEM;
401 }
402
403 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
404 if (ret) {
405 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
406 goto fail;
407 }
408
409 priv->kms = &mdp4_kms->base.base;
410 kms = priv->kms;
411
412 mdp4_kms->dev = dev;
413
414 mdp4_kms->mmio = msm_ioremap(pdev, NULL);
415 if (IS_ERR(mdp4_kms->mmio)) {
416 ret = PTR_ERR(mdp4_kms->mmio);
417 goto fail;
418 }
419
420 irq = platform_get_irq(pdev, 0);
421 if (irq < 0) {
422 ret = irq;
423 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
424 goto fail;
425 }
426
427 kms->irq = irq;
428
429 /* NOTE: driver for this regulator still missing upstream.. use
430 * _get_exclusive() and ignore the error if it does not exist
431 * (and hope that the bootloader left it on for us)
432 */
433 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
434 if (IS_ERR(mdp4_kms->vdd))
435 mdp4_kms->vdd = NULL;
436
437 if (mdp4_kms->vdd) {
438 ret = regulator_enable(mdp4_kms->vdd);
439 if (ret) {
440 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
441 goto fail;
442 }
443 }
444
445 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
446 if (IS_ERR(mdp4_kms->clk)) {
447 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
448 ret = PTR_ERR(mdp4_kms->clk);
449 goto fail;
450 }
451
452 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
453 if (IS_ERR(mdp4_kms->pclk))
454 mdp4_kms->pclk = NULL;
455
456 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
457 if (IS_ERR(mdp4_kms->axi_clk)) {
458 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
459 ret = PTR_ERR(mdp4_kms->axi_clk);
460 goto fail;
461 }
462
463 clk_set_rate(mdp4_kms->clk, config->max_clk);
464
465 read_mdp_hw_revision(mdp4_kms, &major, &minor);
466
467 if (major != 4) {
468 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
469 major, minor);
470 ret = -ENXIO;
471 goto fail;
472 }
473
474 mdp4_kms->rev = minor;
475
476 if (mdp4_kms->rev >= 2) {
477 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
478 if (IS_ERR(mdp4_kms->lut_clk)) {
479 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
480 ret = PTR_ERR(mdp4_kms->lut_clk);
481 goto fail;
482 }
483 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
484 }
485
486 pm_runtime_enable(dev->dev);
487 mdp4_kms->rpm_enabled = true;
488
489 /* make sure things are off before attaching iommu (bootloader could
490 * have left things on, in which case we'll start getting faults if
491 * we don't disable):
492 */
493 mdp4_enable(mdp4_kms);
494 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
495 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
496 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
497 mdp4_disable(mdp4_kms);
498 mdelay(16);
499
500 if (config->iommu) {
501 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
502 config->iommu);
503
504 aspace = msm_gem_address_space_create(mmu,
505 "mdp4", 0x1000, 0x100000000 - 0x1000);
506
507 if (IS_ERR(aspace)) {
508 if (!IS_ERR(mmu))
509 mmu->funcs->destroy(mmu);
510 ret = PTR_ERR(aspace);
511 goto fail;
512 }
513
514 kms->aspace = aspace;
515 } else {
516 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
517 "contig buffers for scanout\n");
518 aspace = NULL;
519 }
520
521 ret = modeset_init(mdp4_kms);
522 if (ret) {
523 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
524 goto fail;
525 }
526
527 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
528 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
529 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
530 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
531 mdp4_kms->blank_cursor_bo = NULL;
532 goto fail;
533 }
534
535 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
536 &mdp4_kms->blank_cursor_iova);
537 if (ret) {
538 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
539 goto fail;
540 }
541
542 dev->mode_config.min_width = 0;
543 dev->mode_config.min_height = 0;
544 dev->mode_config.max_width = 2048;
545 dev->mode_config.max_height = 2048;
546
547 return 0;
548
549 fail:
550 if (kms)
551 mdp4_destroy(kms);
552
553 return ret;
554 }
555
mdp4_get_config(struct platform_device * dev)556 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
557 {
558 static struct mdp4_platform_config config = {};
559
560 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
561 config.max_clk = 266667000;
562 config.iommu = iommu_domain_alloc(&platform_bus_type);
563
564 return &config;
565 }
566
567 static const struct dev_pm_ops mdp4_pm_ops = {
568 .prepare = msm_pm_prepare,
569 .complete = msm_pm_complete,
570 };
571
mdp4_probe(struct platform_device * pdev)572 static int mdp4_probe(struct platform_device *pdev)
573 {
574 return msm_drv_probe(&pdev->dev, mdp4_kms_init);
575 }
576
mdp4_remove(struct platform_device * pdev)577 static int mdp4_remove(struct platform_device *pdev)
578 {
579 component_master_del(&pdev->dev, &msm_drm_ops);
580
581 return 0;
582 }
583
584 static const struct of_device_id mdp4_dt_match[] = {
585 { .compatible = "qcom,mdp4" },
586 { /* sentinel */ }
587 };
588 MODULE_DEVICE_TABLE(of, mdp4_dt_match);
589
590 static struct platform_driver mdp4_platform_driver = {
591 .probe = mdp4_probe,
592 .remove = mdp4_remove,
593 .shutdown = msm_drv_shutdown,
594 .driver = {
595 .name = "mdp4",
596 .of_match_table = mdp4_dt_match,
597 .pm = &mdp4_pm_ops,
598 },
599 };
600
msm_mdp4_register(void)601 void __init msm_mdp4_register(void)
602 {
603 platform_driver_register(&mdp4_platform_driver);
604 }
605
msm_mdp4_unregister(void)606 void __exit msm_mdp4_unregister(void)
607 {
608 platform_driver_unregister(&mdp4_platform_driver);
609 }
610