1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <drm/drm_color_mgmt.h>
26 #include <drm/drm_drv.h>
27 #include <drm/i915_pciids.h>
28
29 #include "i915_driver.h"
30 #include "i915_drv.h"
31 #include "i915_pci.h"
32 #include "i915_reg.h"
33
34 #define PLATFORM(x) .platform = (x)
35 #define GEN(x) \
36 .graphics.ver = (x), \
37 .media.ver = (x), \
38 .display.ver = (x)
39
40 #define I845_PIPE_OFFSETS \
41 .pipe_offsets = { \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
43 }, \
44 .trans_offsets = { \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
46 }
47
48 #define I9XX_PIPE_OFFSETS \
49 .pipe_offsets = { \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
52 }, \
53 .trans_offsets = { \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
56 }
57
58 #define IVB_PIPE_OFFSETS \
59 .pipe_offsets = { \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
63 }, \
64 .trans_offsets = { \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
68 }
69
70 #define HSW_PIPE_OFFSETS \
71 .pipe_offsets = { \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
76 }, \
77 .trans_offsets = { \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
82 }
83
84 #define CHV_PIPE_OFFSETS \
85 .pipe_offsets = { \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
89 }, \
90 .trans_offsets = { \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
94 }
95
96 #define I845_CURSOR_OFFSETS \
97 .cursor_offsets = { \
98 [PIPE_A] = CURSOR_A_OFFSET, \
99 }
100
101 #define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
105 }
106
107 #define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
112 }
113
114 #define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
119 }
120
121 #define TGL_CURSOR_OFFSETS \
122 .cursor_offsets = { \
123 [PIPE_A] = CURSOR_A_OFFSET, \
124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
127 }
128
129 #define I9XX_COLORS \
130 .color = { .gamma_lut_size = 256 }
131 #define I965_COLORS \
132 .color = { .gamma_lut_size = 129, \
133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
134 }
135 #define ILK_COLORS \
136 .color = { .gamma_lut_size = 1024 }
137 #define IVB_COLORS \
138 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
139 #define CHV_COLORS \
140 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
141 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143 }
144 #define GLK_COLORS \
145 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
147 DRM_COLOR_LUT_EQUAL_CHANNELS, \
148 }
149 #define ICL_COLORS \
150 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
151 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
152 DRM_COLOR_LUT_EQUAL_CHANNELS, \
153 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
154 }
155
156 /* Keep in gen based order, and chronological order within a gen */
157
158 #define GEN_DEFAULT_PAGE_SIZES \
159 .page_sizes = I915_GTT_PAGE_SIZE_4K
160
161 #define GEN_DEFAULT_REGIONS \
162 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
163
164 #define I830_FEATURES \
165 GEN(2), \
166 .is_mobile = 1, \
167 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
168 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
169 .display.has_overlay = 1, \
170 .display.cursor_needs_physical = 1, \
171 .display.overlay_needs_physical = 1, \
172 .display.has_gmch = 1, \
173 .gpu_reset_clobbers_display = true, \
174 .hws_needs_physical = 1, \
175 .unfenced_needs_alignment = 1, \
176 .platform_engine_mask = BIT(RCS0), \
177 .has_snoop = true, \
178 .has_coherent_ggtt = false, \
179 .dma_mask_size = 32, \
180 I9XX_PIPE_OFFSETS, \
181 I9XX_CURSOR_OFFSETS, \
182 I9XX_COLORS, \
183 GEN_DEFAULT_PAGE_SIZES, \
184 GEN_DEFAULT_REGIONS
185
186 #define I845_FEATURES \
187 GEN(2), \
188 .display.pipe_mask = BIT(PIPE_A), \
189 .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
190 .display.has_overlay = 1, \
191 .display.overlay_needs_physical = 1, \
192 .display.has_gmch = 1, \
193 .gpu_reset_clobbers_display = true, \
194 .hws_needs_physical = 1, \
195 .unfenced_needs_alignment = 1, \
196 .platform_engine_mask = BIT(RCS0), \
197 .has_snoop = true, \
198 .has_coherent_ggtt = false, \
199 .dma_mask_size = 32, \
200 I845_PIPE_OFFSETS, \
201 I845_CURSOR_OFFSETS, \
202 I9XX_COLORS, \
203 GEN_DEFAULT_PAGE_SIZES, \
204 GEN_DEFAULT_REGIONS
205
206 static const struct intel_device_info i830_info = {
207 I830_FEATURES,
208 PLATFORM(INTEL_I830),
209 };
210
211 static const struct intel_device_info i845g_info = {
212 I845_FEATURES,
213 PLATFORM(INTEL_I845G),
214 };
215
216 static const struct intel_device_info i85x_info = {
217 I830_FEATURES,
218 PLATFORM(INTEL_I85X),
219 .display.fbc_mask = BIT(INTEL_FBC_A),
220 };
221
222 static const struct intel_device_info i865g_info = {
223 I845_FEATURES,
224 PLATFORM(INTEL_I865G),
225 .display.fbc_mask = BIT(INTEL_FBC_A),
226 };
227
228 #define GEN3_FEATURES \
229 GEN(3), \
230 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
231 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
232 .display.has_gmch = 1, \
233 .gpu_reset_clobbers_display = true, \
234 .platform_engine_mask = BIT(RCS0), \
235 .has_snoop = true, \
236 .has_coherent_ggtt = true, \
237 .dma_mask_size = 32, \
238 I9XX_PIPE_OFFSETS, \
239 I9XX_CURSOR_OFFSETS, \
240 I9XX_COLORS, \
241 GEN_DEFAULT_PAGE_SIZES, \
242 GEN_DEFAULT_REGIONS
243
244 static const struct intel_device_info i915g_info = {
245 GEN3_FEATURES,
246 PLATFORM(INTEL_I915G),
247 .has_coherent_ggtt = false,
248 .display.cursor_needs_physical = 1,
249 .display.has_overlay = 1,
250 .display.overlay_needs_physical = 1,
251 .hws_needs_physical = 1,
252 .unfenced_needs_alignment = 1,
253 };
254
255 static const struct intel_device_info i915gm_info = {
256 GEN3_FEATURES,
257 PLATFORM(INTEL_I915GM),
258 .is_mobile = 1,
259 .display.cursor_needs_physical = 1,
260 .display.has_overlay = 1,
261 .display.overlay_needs_physical = 1,
262 .display.supports_tv = 1,
263 .display.fbc_mask = BIT(INTEL_FBC_A),
264 .hws_needs_physical = 1,
265 .unfenced_needs_alignment = 1,
266 };
267
268 static const struct intel_device_info i945g_info = {
269 GEN3_FEATURES,
270 PLATFORM(INTEL_I945G),
271 .display.has_hotplug = 1,
272 .display.cursor_needs_physical = 1,
273 .display.has_overlay = 1,
274 .display.overlay_needs_physical = 1,
275 .hws_needs_physical = 1,
276 .unfenced_needs_alignment = 1,
277 };
278
279 static const struct intel_device_info i945gm_info = {
280 GEN3_FEATURES,
281 PLATFORM(INTEL_I945GM),
282 .is_mobile = 1,
283 .display.has_hotplug = 1,
284 .display.cursor_needs_physical = 1,
285 .display.has_overlay = 1,
286 .display.overlay_needs_physical = 1,
287 .display.supports_tv = 1,
288 .display.fbc_mask = BIT(INTEL_FBC_A),
289 .hws_needs_physical = 1,
290 .unfenced_needs_alignment = 1,
291 };
292
293 static const struct intel_device_info g33_info = {
294 GEN3_FEATURES,
295 PLATFORM(INTEL_G33),
296 .display.has_hotplug = 1,
297 .display.has_overlay = 1,
298 .dma_mask_size = 36,
299 };
300
301 static const struct intel_device_info pnv_g_info = {
302 GEN3_FEATURES,
303 PLATFORM(INTEL_PINEVIEW),
304 .display.has_hotplug = 1,
305 .display.has_overlay = 1,
306 .dma_mask_size = 36,
307 };
308
309 static const struct intel_device_info pnv_m_info = {
310 GEN3_FEATURES,
311 PLATFORM(INTEL_PINEVIEW),
312 .is_mobile = 1,
313 .display.has_hotplug = 1,
314 .display.has_overlay = 1,
315 .dma_mask_size = 36,
316 };
317
318 #define GEN4_FEATURES \
319 GEN(4), \
320 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
321 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
322 .display.has_hotplug = 1, \
323 .display.has_gmch = 1, \
324 .gpu_reset_clobbers_display = true, \
325 .platform_engine_mask = BIT(RCS0), \
326 .has_snoop = true, \
327 .has_coherent_ggtt = true, \
328 .dma_mask_size = 36, \
329 I9XX_PIPE_OFFSETS, \
330 I9XX_CURSOR_OFFSETS, \
331 I965_COLORS, \
332 GEN_DEFAULT_PAGE_SIZES, \
333 GEN_DEFAULT_REGIONS
334
335 static const struct intel_device_info i965g_info = {
336 GEN4_FEATURES,
337 PLATFORM(INTEL_I965G),
338 .display.has_overlay = 1,
339 .hws_needs_physical = 1,
340 .has_snoop = false,
341 };
342
343 static const struct intel_device_info i965gm_info = {
344 GEN4_FEATURES,
345 PLATFORM(INTEL_I965GM),
346 .is_mobile = 1,
347 .display.fbc_mask = BIT(INTEL_FBC_A),
348 .display.has_overlay = 1,
349 .display.supports_tv = 1,
350 .hws_needs_physical = 1,
351 .has_snoop = false,
352 };
353
354 static const struct intel_device_info g45_info = {
355 GEN4_FEATURES,
356 PLATFORM(INTEL_G45),
357 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
358 .gpu_reset_clobbers_display = false,
359 };
360
361 static const struct intel_device_info gm45_info = {
362 GEN4_FEATURES,
363 PLATFORM(INTEL_GM45),
364 .is_mobile = 1,
365 .display.fbc_mask = BIT(INTEL_FBC_A),
366 .display.supports_tv = 1,
367 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
368 .gpu_reset_clobbers_display = false,
369 };
370
371 #define GEN5_FEATURES \
372 GEN(5), \
373 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
374 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
375 .display.has_hotplug = 1, \
376 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
377 .has_snoop = true, \
378 .has_coherent_ggtt = true, \
379 /* ilk does support rc6, but we do not implement [power] contexts */ \
380 .has_rc6 = 0, \
381 .dma_mask_size = 36, \
382 I9XX_PIPE_OFFSETS, \
383 I9XX_CURSOR_OFFSETS, \
384 ILK_COLORS, \
385 GEN_DEFAULT_PAGE_SIZES, \
386 GEN_DEFAULT_REGIONS
387
388 static const struct intel_device_info ilk_d_info = {
389 GEN5_FEATURES,
390 PLATFORM(INTEL_IRONLAKE),
391 };
392
393 static const struct intel_device_info ilk_m_info = {
394 GEN5_FEATURES,
395 PLATFORM(INTEL_IRONLAKE),
396 .is_mobile = 1,
397 .has_rps = true,
398 .display.fbc_mask = BIT(INTEL_FBC_A),
399 };
400
401 #define GEN6_FEATURES \
402 GEN(6), \
403 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
404 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
405 .display.has_hotplug = 1, \
406 .display.fbc_mask = BIT(INTEL_FBC_A), \
407 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
408 .has_coherent_ggtt = true, \
409 .has_llc = 1, \
410 .has_rc6 = 1, \
411 .has_rc6p = 1, \
412 .has_rps = true, \
413 .dma_mask_size = 40, \
414 .ppgtt_type = INTEL_PPGTT_ALIASING, \
415 .ppgtt_size = 31, \
416 I9XX_PIPE_OFFSETS, \
417 I9XX_CURSOR_OFFSETS, \
418 ILK_COLORS, \
419 GEN_DEFAULT_PAGE_SIZES, \
420 GEN_DEFAULT_REGIONS
421
422 #define SNB_D_PLATFORM \
423 GEN6_FEATURES, \
424 PLATFORM(INTEL_SANDYBRIDGE)
425
426 static const struct intel_device_info snb_d_gt1_info = {
427 SNB_D_PLATFORM,
428 .gt = 1,
429 };
430
431 static const struct intel_device_info snb_d_gt2_info = {
432 SNB_D_PLATFORM,
433 .gt = 2,
434 };
435
436 #define SNB_M_PLATFORM \
437 GEN6_FEATURES, \
438 PLATFORM(INTEL_SANDYBRIDGE), \
439 .is_mobile = 1
440
441
442 static const struct intel_device_info snb_m_gt1_info = {
443 SNB_M_PLATFORM,
444 .gt = 1,
445 };
446
447 static const struct intel_device_info snb_m_gt2_info = {
448 SNB_M_PLATFORM,
449 .gt = 2,
450 };
451
452 #define GEN7_FEATURES \
453 GEN(7), \
454 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
455 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
456 .display.has_hotplug = 1, \
457 .display.fbc_mask = BIT(INTEL_FBC_A), \
458 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
459 .has_coherent_ggtt = true, \
460 .has_llc = 1, \
461 .has_rc6 = 1, \
462 .has_rc6p = 1, \
463 .has_reset_engine = true, \
464 .has_rps = true, \
465 .dma_mask_size = 40, \
466 .ppgtt_type = INTEL_PPGTT_ALIASING, \
467 .ppgtt_size = 31, \
468 IVB_PIPE_OFFSETS, \
469 IVB_CURSOR_OFFSETS, \
470 IVB_COLORS, \
471 GEN_DEFAULT_PAGE_SIZES, \
472 GEN_DEFAULT_REGIONS
473
474 #define IVB_D_PLATFORM \
475 GEN7_FEATURES, \
476 PLATFORM(INTEL_IVYBRIDGE), \
477 .has_l3_dpf = 1
478
479 static const struct intel_device_info ivb_d_gt1_info = {
480 IVB_D_PLATFORM,
481 .gt = 1,
482 };
483
484 static const struct intel_device_info ivb_d_gt2_info = {
485 IVB_D_PLATFORM,
486 .gt = 2,
487 };
488
489 #define IVB_M_PLATFORM \
490 GEN7_FEATURES, \
491 PLATFORM(INTEL_IVYBRIDGE), \
492 .is_mobile = 1, \
493 .has_l3_dpf = 1
494
495 static const struct intel_device_info ivb_m_gt1_info = {
496 IVB_M_PLATFORM,
497 .gt = 1,
498 };
499
500 static const struct intel_device_info ivb_m_gt2_info = {
501 IVB_M_PLATFORM,
502 .gt = 2,
503 };
504
505 static const struct intel_device_info ivb_q_info = {
506 GEN7_FEATURES,
507 PLATFORM(INTEL_IVYBRIDGE),
508 .gt = 2,
509 .display.pipe_mask = 0, /* legal, last one wins */
510 .display.cpu_transcoder_mask = 0,
511 .has_l3_dpf = 1,
512 };
513
514 static const struct intel_device_info vlv_info = {
515 PLATFORM(INTEL_VALLEYVIEW),
516 GEN(7),
517 .is_lp = 1,
518 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
519 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
520 .has_runtime_pm = 1,
521 .has_rc6 = 1,
522 .has_reset_engine = true,
523 .has_rps = true,
524 .display.has_gmch = 1,
525 .display.has_hotplug = 1,
526 .dma_mask_size = 40,
527 .ppgtt_type = INTEL_PPGTT_ALIASING,
528 .ppgtt_size = 31,
529 .has_snoop = true,
530 .has_coherent_ggtt = false,
531 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
532 .display_mmio_offset = VLV_DISPLAY_BASE,
533 I9XX_PIPE_OFFSETS,
534 I9XX_CURSOR_OFFSETS,
535 I965_COLORS,
536 GEN_DEFAULT_PAGE_SIZES,
537 GEN_DEFAULT_REGIONS,
538 };
539
540 #define G75_FEATURES \
541 GEN7_FEATURES, \
542 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
543 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
544 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
545 .display.has_ddi = 1, \
546 .display.has_fpga_dbg = 1, \
547 .display.has_dp_mst = 1, \
548 .has_rc6p = 0 /* RC6p removed-by HSW */, \
549 HSW_PIPE_OFFSETS, \
550 .has_runtime_pm = 1
551
552 #define HSW_PLATFORM \
553 G75_FEATURES, \
554 PLATFORM(INTEL_HASWELL), \
555 .has_l3_dpf = 1
556
557 static const struct intel_device_info hsw_gt1_info = {
558 HSW_PLATFORM,
559 .gt = 1,
560 };
561
562 static const struct intel_device_info hsw_gt2_info = {
563 HSW_PLATFORM,
564 .gt = 2,
565 };
566
567 static const struct intel_device_info hsw_gt3_info = {
568 HSW_PLATFORM,
569 .gt = 3,
570 };
571
572 #define GEN8_FEATURES \
573 G75_FEATURES, \
574 GEN(8), \
575 .has_logical_ring_contexts = 1, \
576 .dma_mask_size = 39, \
577 .ppgtt_type = INTEL_PPGTT_FULL, \
578 .ppgtt_size = 48, \
579 .has_64bit_reloc = 1
580
581 #define BDW_PLATFORM \
582 GEN8_FEATURES, \
583 PLATFORM(INTEL_BROADWELL)
584
585 static const struct intel_device_info bdw_gt1_info = {
586 BDW_PLATFORM,
587 .gt = 1,
588 };
589
590 static const struct intel_device_info bdw_gt2_info = {
591 BDW_PLATFORM,
592 .gt = 2,
593 };
594
595 static const struct intel_device_info bdw_rsvd_info = {
596 BDW_PLATFORM,
597 .gt = 3,
598 /* According to the device ID those devices are GT3, they were
599 * previously treated as not GT3, keep it like that.
600 */
601 };
602
603 static const struct intel_device_info bdw_gt3_info = {
604 BDW_PLATFORM,
605 .gt = 3,
606 .platform_engine_mask =
607 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
608 };
609
610 static const struct intel_device_info chv_info = {
611 PLATFORM(INTEL_CHERRYVIEW),
612 GEN(8),
613 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
614 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
615 .display.has_hotplug = 1,
616 .is_lp = 1,
617 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
618 .has_64bit_reloc = 1,
619 .has_runtime_pm = 1,
620 .has_rc6 = 1,
621 .has_rps = true,
622 .has_logical_ring_contexts = 1,
623 .display.has_gmch = 1,
624 .dma_mask_size = 39,
625 .ppgtt_type = INTEL_PPGTT_FULL,
626 .ppgtt_size = 32,
627 .has_reset_engine = 1,
628 .has_snoop = true,
629 .has_coherent_ggtt = false,
630 .display_mmio_offset = VLV_DISPLAY_BASE,
631 CHV_PIPE_OFFSETS,
632 CHV_CURSOR_OFFSETS,
633 CHV_COLORS,
634 GEN_DEFAULT_PAGE_SIZES,
635 GEN_DEFAULT_REGIONS,
636 };
637
638 #define GEN9_DEFAULT_PAGE_SIZES \
639 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
640 I915_GTT_PAGE_SIZE_64K
641
642 #define GEN9_FEATURES \
643 GEN8_FEATURES, \
644 GEN(9), \
645 GEN9_DEFAULT_PAGE_SIZES, \
646 .display.has_dmc = 1, \
647 .has_gt_uc = 1, \
648 .display.has_hdcp = 1, \
649 .display.has_ipc = 1, \
650 .display.has_psr = 1, \
651 .display.has_psr_hw_tracking = 1, \
652 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
653 .dbuf.slice_mask = BIT(DBUF_S1)
654
655 #define SKL_PLATFORM \
656 GEN9_FEATURES, \
657 PLATFORM(INTEL_SKYLAKE)
658
659 static const struct intel_device_info skl_gt1_info = {
660 SKL_PLATFORM,
661 .gt = 1,
662 };
663
664 static const struct intel_device_info skl_gt2_info = {
665 SKL_PLATFORM,
666 .gt = 2,
667 };
668
669 #define SKL_GT3_PLUS_PLATFORM \
670 SKL_PLATFORM, \
671 .platform_engine_mask = \
672 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
673
674
675 static const struct intel_device_info skl_gt3_info = {
676 SKL_GT3_PLUS_PLATFORM,
677 .gt = 3,
678 };
679
680 static const struct intel_device_info skl_gt4_info = {
681 SKL_GT3_PLUS_PLATFORM,
682 .gt = 4,
683 };
684
685 #define GEN9_LP_FEATURES \
686 GEN(9), \
687 .is_lp = 1, \
688 .dbuf.slice_mask = BIT(DBUF_S1), \
689 .display.has_hotplug = 1, \
690 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
691 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
692 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
693 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
694 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
695 .has_64bit_reloc = 1, \
696 .display.has_ddi = 1, \
697 .display.has_fpga_dbg = 1, \
698 .display.fbc_mask = BIT(INTEL_FBC_A), \
699 .display.has_hdcp = 1, \
700 .display.has_psr = 1, \
701 .display.has_psr_hw_tracking = 1, \
702 .has_runtime_pm = 1, \
703 .display.has_dmc = 1, \
704 .has_rc6 = 1, \
705 .has_rps = true, \
706 .display.has_dp_mst = 1, \
707 .has_logical_ring_contexts = 1, \
708 .has_gt_uc = 1, \
709 .dma_mask_size = 39, \
710 .ppgtt_type = INTEL_PPGTT_FULL, \
711 .ppgtt_size = 48, \
712 .has_reset_engine = 1, \
713 .has_snoop = true, \
714 .has_coherent_ggtt = false, \
715 .display.has_ipc = 1, \
716 HSW_PIPE_OFFSETS, \
717 IVB_CURSOR_OFFSETS, \
718 IVB_COLORS, \
719 GEN9_DEFAULT_PAGE_SIZES, \
720 GEN_DEFAULT_REGIONS
721
722 static const struct intel_device_info bxt_info = {
723 GEN9_LP_FEATURES,
724 PLATFORM(INTEL_BROXTON),
725 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
726 };
727
728 static const struct intel_device_info glk_info = {
729 GEN9_LP_FEATURES,
730 PLATFORM(INTEL_GEMINILAKE),
731 .display.ver = 10,
732 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
733 GLK_COLORS,
734 };
735
736 #define KBL_PLATFORM \
737 GEN9_FEATURES, \
738 PLATFORM(INTEL_KABYLAKE)
739
740 static const struct intel_device_info kbl_gt1_info = {
741 KBL_PLATFORM,
742 .gt = 1,
743 };
744
745 static const struct intel_device_info kbl_gt2_info = {
746 KBL_PLATFORM,
747 .gt = 2,
748 };
749
750 static const struct intel_device_info kbl_gt3_info = {
751 KBL_PLATFORM,
752 .gt = 3,
753 .platform_engine_mask =
754 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
755 };
756
757 #define CFL_PLATFORM \
758 GEN9_FEATURES, \
759 PLATFORM(INTEL_COFFEELAKE)
760
761 static const struct intel_device_info cfl_gt1_info = {
762 CFL_PLATFORM,
763 .gt = 1,
764 };
765
766 static const struct intel_device_info cfl_gt2_info = {
767 CFL_PLATFORM,
768 .gt = 2,
769 };
770
771 static const struct intel_device_info cfl_gt3_info = {
772 CFL_PLATFORM,
773 .gt = 3,
774 .platform_engine_mask =
775 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
776 };
777
778 #define CML_PLATFORM \
779 GEN9_FEATURES, \
780 PLATFORM(INTEL_COMETLAKE)
781
782 static const struct intel_device_info cml_gt1_info = {
783 CML_PLATFORM,
784 .gt = 1,
785 };
786
787 static const struct intel_device_info cml_gt2_info = {
788 CML_PLATFORM,
789 .gt = 2,
790 };
791
792 #define GEN11_DEFAULT_PAGE_SIZES \
793 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
794 I915_GTT_PAGE_SIZE_64K | \
795 I915_GTT_PAGE_SIZE_2M
796
797 #define GEN11_FEATURES \
798 GEN9_FEATURES, \
799 GEN11_DEFAULT_PAGE_SIZES, \
800 .display.abox_mask = BIT(0), \
801 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
802 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
803 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
804 .pipe_offsets = { \
805 [TRANSCODER_A] = PIPE_A_OFFSET, \
806 [TRANSCODER_B] = PIPE_B_OFFSET, \
807 [TRANSCODER_C] = PIPE_C_OFFSET, \
808 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
809 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
810 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
811 }, \
812 .trans_offsets = { \
813 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
814 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
815 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
816 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
817 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
818 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
819 }, \
820 GEN(11), \
821 ICL_COLORS, \
822 .dbuf.size = 2048, \
823 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
824 .display.has_dsc = 1, \
825 .has_coherent_ggtt = false, \
826 .has_logical_ring_elsq = 1
827
828 static const struct intel_device_info icl_info = {
829 GEN11_FEATURES,
830 PLATFORM(INTEL_ICELAKE),
831 .platform_engine_mask =
832 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
833 };
834
835 static const struct intel_device_info ehl_info = {
836 GEN11_FEATURES,
837 PLATFORM(INTEL_ELKHARTLAKE),
838 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
839 .ppgtt_size = 36,
840 };
841
842 static const struct intel_device_info jsl_info = {
843 GEN11_FEATURES,
844 PLATFORM(INTEL_JASPERLAKE),
845 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
846 .ppgtt_size = 36,
847 };
848
849 #define GEN12_FEATURES \
850 GEN11_FEATURES, \
851 GEN(12), \
852 .display.abox_mask = GENMASK(2, 1), \
853 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
854 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
855 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
856 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
857 .pipe_offsets = { \
858 [TRANSCODER_A] = PIPE_A_OFFSET, \
859 [TRANSCODER_B] = PIPE_B_OFFSET, \
860 [TRANSCODER_C] = PIPE_C_OFFSET, \
861 [TRANSCODER_D] = PIPE_D_OFFSET, \
862 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
863 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
864 }, \
865 .trans_offsets = { \
866 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
867 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
868 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
869 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
870 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
871 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
872 }, \
873 TGL_CURSOR_OFFSETS, \
874 .has_global_mocs = 1, \
875 .has_pxp = 1, \
876 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
877
878 static const struct intel_device_info tgl_info = {
879 GEN12_FEATURES,
880 PLATFORM(INTEL_TIGERLAKE),
881 .display.has_modular_fia = 1,
882 .platform_engine_mask =
883 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
884 };
885
886 static const struct intel_device_info rkl_info = {
887 GEN12_FEATURES,
888 PLATFORM(INTEL_ROCKETLAKE),
889 .display.abox_mask = BIT(0),
890 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
891 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
892 BIT(TRANSCODER_C),
893 .display.has_hti = 1,
894 .display.has_psr_hw_tracking = 0,
895 .platform_engine_mask =
896 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
897 };
898
899 #define DGFX_FEATURES \
900 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
901 .has_llc = 0, \
902 .has_pxp = 0, \
903 .has_snoop = 1, \
904 .is_dgfx = 1, \
905 .has_heci_gscfi = 1
906
907 static const struct intel_device_info dg1_info = {
908 GEN12_FEATURES,
909 DGFX_FEATURES,
910 .graphics.rel = 10,
911 PLATFORM(INTEL_DG1),
912 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
913 .require_force_probe = 1,
914 .platform_engine_mask =
915 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
916 BIT(VCS0) | BIT(VCS2),
917 /* Wa_16011227922 */
918 .ppgtt_size = 47,
919 };
920
921 static const struct intel_device_info adl_s_info = {
922 GEN12_FEATURES,
923 PLATFORM(INTEL_ALDERLAKE_S),
924 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
925 .display.has_hti = 1,
926 .display.has_psr_hw_tracking = 0,
927 .platform_engine_mask =
928 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
929 .dma_mask_size = 39,
930 };
931
932 #define XE_LPD_CURSOR_OFFSETS \
933 .cursor_offsets = { \
934 [PIPE_A] = CURSOR_A_OFFSET, \
935 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
936 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
937 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
938 }
939
940 #define XE_LPD_FEATURES \
941 .display.abox_mask = GENMASK(1, 0), \
942 .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
943 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
944 DRM_COLOR_LUT_EQUAL_CHANNELS, \
945 }, \
946 .dbuf.size = 4096, \
947 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
948 BIT(DBUF_S4), \
949 .display.has_ddi = 1, \
950 .display.has_dmc = 1, \
951 .display.has_dp_mst = 1, \
952 .display.has_dsb = 1, \
953 .display.has_dsc = 1, \
954 .display.fbc_mask = BIT(INTEL_FBC_A), \
955 .display.has_fpga_dbg = 1, \
956 .display.has_hdcp = 1, \
957 .display.has_hotplug = 1, \
958 .display.has_ipc = 1, \
959 .display.has_psr = 1, \
960 .display.ver = 13, \
961 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
962 .pipe_offsets = { \
963 [TRANSCODER_A] = PIPE_A_OFFSET, \
964 [TRANSCODER_B] = PIPE_B_OFFSET, \
965 [TRANSCODER_C] = PIPE_C_OFFSET, \
966 [TRANSCODER_D] = PIPE_D_OFFSET, \
967 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
968 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
969 }, \
970 .trans_offsets = { \
971 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
972 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
973 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
974 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
975 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
976 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
977 }, \
978 XE_LPD_CURSOR_OFFSETS
979
980 static const struct intel_device_info adl_p_info = {
981 GEN12_FEATURES,
982 XE_LPD_FEATURES,
983 PLATFORM(INTEL_ALDERLAKE_P),
984 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
985 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
986 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
987 .display.has_cdclk_crawl = 1,
988 .display.has_modular_fia = 1,
989 .display.has_psr_hw_tracking = 0,
990 .platform_engine_mask =
991 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
992 .ppgtt_size = 48,
993 .dma_mask_size = 39,
994 };
995
996 #undef GEN
997
998 #define XE_HP_PAGE_SIZES \
999 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
1000 I915_GTT_PAGE_SIZE_64K | \
1001 I915_GTT_PAGE_SIZE_2M
1002
1003 #define XE_HP_FEATURES \
1004 .graphics.ver = 12, \
1005 .graphics.rel = 50, \
1006 XE_HP_PAGE_SIZES, \
1007 .dma_mask_size = 46, \
1008 .has_64bit_reloc = 1, \
1009 .has_flat_ccs = 1, \
1010 .has_global_mocs = 1, \
1011 .has_gt_uc = 1, \
1012 .has_llc = 1, \
1013 .has_logical_ring_contexts = 1, \
1014 .has_logical_ring_elsq = 1, \
1015 .has_mslices = 1, \
1016 .has_rc6 = 1, \
1017 .has_reset_engine = 1, \
1018 .has_rps = 1, \
1019 .has_runtime_pm = 1, \
1020 .ppgtt_size = 48, \
1021 .ppgtt_type = INTEL_PPGTT_FULL
1022
1023 #define XE_HPM_FEATURES \
1024 .media.ver = 12, \
1025 .media.rel = 50
1026
1027 __maybe_unused
1028 static const struct intel_device_info xehpsdv_info = {
1029 XE_HP_FEATURES,
1030 XE_HPM_FEATURES,
1031 DGFX_FEATURES,
1032 PLATFORM(INTEL_XEHPSDV),
1033 .display = { },
1034 .has_64k_pages = 1,
1035 .needs_compact_pt = 1,
1036 .platform_engine_mask =
1037 BIT(RCS0) | BIT(BCS0) |
1038 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1039 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1040 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1041 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1042 .require_force_probe = 1,
1043 };
1044
1045 #define DG2_FEATURES \
1046 XE_HP_FEATURES, \
1047 XE_HPM_FEATURES, \
1048 DGFX_FEATURES, \
1049 .graphics.rel = 55, \
1050 .media.rel = 55, \
1051 PLATFORM(INTEL_DG2), \
1052 .has_4tile = 1, \
1053 .has_64k_pages = 1, \
1054 .has_guc_deprivilege = 1, \
1055 .has_heci_pxp = 1, \
1056 .needs_compact_pt = 1, \
1057 .platform_engine_mask = \
1058 BIT(RCS0) | BIT(BCS0) | \
1059 BIT(VECS0) | BIT(VECS1) | \
1060 BIT(VCS0) | BIT(VCS2) | \
1061 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1062
1063 static const struct intel_device_info dg2_info = {
1064 DG2_FEATURES,
1065 XE_LPD_FEATURES,
1066 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1067 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1068 .require_force_probe = 1,
1069 };
1070
1071 __maybe_unused
1072 static const struct intel_device_info ats_m_info = {
1073 DG2_FEATURES,
1074 .display = { 0 },
1075 .require_force_probe = 1,
1076 };
1077
1078 #define XE_HPC_FEATURES \
1079 XE_HP_FEATURES, \
1080 .dma_mask_size = 52
1081
1082 __maybe_unused
1083 static const struct intel_device_info pvc_info = {
1084 XE_HPC_FEATURES,
1085 XE_HPM_FEATURES,
1086 DGFX_FEATURES,
1087 .graphics.rel = 60,
1088 .media.rel = 60,
1089 PLATFORM(INTEL_PONTEVECCHIO),
1090 .display = { 0 },
1091 .has_flat_ccs = 0,
1092 .platform_engine_mask =
1093 BIT(BCS0) |
1094 BIT(VCS0) |
1095 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1096 .require_force_probe = 1,
1097 };
1098
1099 #undef PLATFORM
1100
1101 /*
1102 * Make sure any device matches here are from most specific to most
1103 * general. For example, since the Quanta match is based on the subsystem
1104 * and subvendor IDs, we need it to come before the more general IVB
1105 * PCI ID matches, otherwise we'll use the wrong info struct above.
1106 */
1107 static const struct pci_device_id pciidlist[] = {
1108 INTEL_I830_IDS(&i830_info),
1109 INTEL_I845G_IDS(&i845g_info),
1110 INTEL_I85X_IDS(&i85x_info),
1111 INTEL_I865G_IDS(&i865g_info),
1112 INTEL_I915G_IDS(&i915g_info),
1113 INTEL_I915GM_IDS(&i915gm_info),
1114 INTEL_I945G_IDS(&i945g_info),
1115 INTEL_I945GM_IDS(&i945gm_info),
1116 INTEL_I965G_IDS(&i965g_info),
1117 INTEL_G33_IDS(&g33_info),
1118 INTEL_I965GM_IDS(&i965gm_info),
1119 INTEL_GM45_IDS(&gm45_info),
1120 INTEL_G45_IDS(&g45_info),
1121 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1122 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1123 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1124 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1125 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1126 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1127 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1128 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1129 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1130 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1131 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1132 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1133 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1134 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1135 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1136 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1137 INTEL_VLV_IDS(&vlv_info),
1138 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1139 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1140 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1141 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1142 INTEL_CHV_IDS(&chv_info),
1143 INTEL_SKL_GT1_IDS(&skl_gt1_info),
1144 INTEL_SKL_GT2_IDS(&skl_gt2_info),
1145 INTEL_SKL_GT3_IDS(&skl_gt3_info),
1146 INTEL_SKL_GT4_IDS(&skl_gt4_info),
1147 INTEL_BXT_IDS(&bxt_info),
1148 INTEL_GLK_IDS(&glk_info),
1149 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1150 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1151 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1152 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1153 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1154 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1155 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1156 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1157 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1158 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1159 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1160 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1161 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1162 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1163 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1164 INTEL_CML_GT1_IDS(&cml_gt1_info),
1165 INTEL_CML_GT2_IDS(&cml_gt2_info),
1166 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1167 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1168 INTEL_ICL_11_IDS(&icl_info),
1169 INTEL_EHL_IDS(&ehl_info),
1170 INTEL_JSL_IDS(&jsl_info),
1171 INTEL_TGL_12_IDS(&tgl_info),
1172 INTEL_RKL_IDS(&rkl_info),
1173 INTEL_ADLS_IDS(&adl_s_info),
1174 INTEL_ADLP_IDS(&adl_p_info),
1175 INTEL_ADLN_IDS(&adl_p_info),
1176 INTEL_DG1_IDS(&dg1_info),
1177 INTEL_RPLS_IDS(&adl_s_info),
1178 INTEL_RPLP_IDS(&adl_p_info),
1179 INTEL_DG2_IDS(&dg2_info),
1180 {0, 0, 0}
1181 };
1182 MODULE_DEVICE_TABLE(pci, pciidlist);
1183
i915_pci_remove(struct pci_dev * pdev)1184 static void i915_pci_remove(struct pci_dev *pdev)
1185 {
1186 struct drm_i915_private *i915;
1187
1188 i915 = pci_get_drvdata(pdev);
1189 if (!i915) /* driver load aborted, nothing to cleanup */
1190 return;
1191
1192 i915_driver_remove(i915);
1193 pci_set_drvdata(pdev, NULL);
1194 }
1195
1196 /* is device_id present in comma separated list of ids */
force_probe(u16 device_id,const char * devices)1197 static bool force_probe(u16 device_id, const char *devices)
1198 {
1199 char *s, *p, *tok;
1200 bool ret;
1201
1202 if (!devices || !*devices)
1203 return false;
1204
1205 /* match everything */
1206 if (strcmp(devices, "*") == 0)
1207 return true;
1208
1209 s = kstrdup(devices, GFP_KERNEL);
1210 if (!s)
1211 return false;
1212
1213 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1214 u16 val;
1215
1216 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1217 ret = true;
1218 break;
1219 }
1220 }
1221
1222 kfree(s);
1223
1224 return ret;
1225 }
1226
i915_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1227 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1228 {
1229 struct intel_device_info *intel_info =
1230 (struct intel_device_info *) ent->driver_data;
1231 int err;
1232
1233 if (intel_info->require_force_probe &&
1234 !force_probe(pdev->device, i915_modparams.force_probe)) {
1235 dev_info(&pdev->dev,
1236 "Your graphics device %04x is not properly supported by the driver in this\n"
1237 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1238 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1239 "or (recommended) check for kernel updates.\n",
1240 pdev->device, pdev->device, pdev->device);
1241 return -ENODEV;
1242 }
1243
1244 /* Only bind to function 0 of the device. Early generations
1245 * used function 1 as a placeholder for multi-head. This causes
1246 * us confusion instead, especially on the systems where both
1247 * functions have the same PCI-ID!
1248 */
1249 if (PCI_FUNC(pdev->devfn))
1250 return -ENODEV;
1251
1252 /* Detect if we need to wait for other drivers early on */
1253 if (intel_modeset_probe_defer(pdev))
1254 return -EPROBE_DEFER;
1255
1256 err = i915_driver_probe(pdev, ent);
1257 if (err)
1258 return err;
1259
1260 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1261 i915_pci_remove(pdev);
1262 return -ENODEV;
1263 }
1264
1265 err = i915_live_selftests(pdev);
1266 if (err) {
1267 i915_pci_remove(pdev);
1268 return err > 0 ? -ENOTTY : err;
1269 }
1270
1271 err = i915_perf_selftests(pdev);
1272 if (err) {
1273 i915_pci_remove(pdev);
1274 return err > 0 ? -ENOTTY : err;
1275 }
1276
1277 return 0;
1278 }
1279
i915_pci_shutdown(struct pci_dev * pdev)1280 static void i915_pci_shutdown(struct pci_dev *pdev)
1281 {
1282 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1283
1284 i915_driver_shutdown(i915);
1285 }
1286
1287 static struct pci_driver i915_pci_driver = {
1288 .name = DRIVER_NAME,
1289 .id_table = pciidlist,
1290 .probe = i915_pci_probe,
1291 .remove = i915_pci_remove,
1292 .shutdown = i915_pci_shutdown,
1293 .driver.pm = &i915_pm_ops,
1294 };
1295
i915_pci_register_driver(void)1296 int i915_pci_register_driver(void)
1297 {
1298 return pci_register_driver(&i915_pci_driver);
1299 }
1300
i915_pci_unregister_driver(void)1301 void i915_pci_unregister_driver(void)
1302 {
1303 pci_unregister_driver(&i915_pci_driver);
1304 }
1305