1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Amarula Solutions(India)
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_of.h>
9 #include <drm/drm_print.h>
10 #include <drm/drm_mipi_dsi.h>
11
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19
20 #define VENDOR_ID 0x00
21 #define DEVICE_ID_H 0x01
22 #define DEVICE_ID_L 0x02
23 #define VERSION_ID 0x03
24 #define FIRMWARE_VERSION 0x08
25 #define CONFIG_FINISH 0x09
26 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */
27 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */
28 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */
29 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */
30 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */
31 #define RGB_TEST_CTRL 0x1e
32 #define ATE_PLL_EN 0x1f
33 #define HACTIVE_LI 0x20
34 #define VACTIVE_LI 0x21
35 #define VACTIVE_HACTIVE_HI 0x22
36 #define HFP_LI 0x23
37 #define HSYNC_LI 0x24
38 #define HBP_LI 0x25
39 #define HFP_HSW_HBP_HI 0x26
40 #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)
41 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)
42 #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)
43 #define VFP 0x27
44 #define VSYNC 0x28
45 #define VBP 0x29
46 #define BIST_POL 0x2a
47 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4)
48 #define BIST_POL_BIST_GEN BIT(3)
49 #define BIST_POL_HSYNC_POL BIT(2)
50 #define BIST_POL_VSYNC_POL BIT(1)
51 #define BIST_POL_DE_POL BIT(0)
52 #define BIST_RED 0x2b
53 #define BIST_GREEN 0x2c
54 #define BIST_BLUE 0x2d
55 #define BIST_CHESS_X 0x2e
56 #define BIST_CHESS_Y 0x2f
57 #define BIST_CHESS_XY_H 0x30
58 #define BIST_FRAME_TIME_L 0x31
59 #define BIST_FRAME_TIME_H 0x32
60 #define FIFO_MAX_ADDR_LOW 0x33
61 #define SYNC_EVENT_DLY 0x34
62 #define HSW_MIN 0x35
63 #define HFP_MIN 0x36
64 #define LOGIC_RST_NUM 0x37
65 #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */
66 #define BG_CTRL 0x4e
67 #define LDO_PLL 0x4f
68 #define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */
69 #define PLL_CTRL_6_EXTERNAL 0x90
70 #define PLL_CTRL_6_MIPI_CLK 0x92
71 #define PLL_CTRL_6_INTERNAL 0x93
72 #define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */
73 #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */
74 #define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */
75 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */
76 #define PLL_REF_DIV 0x6b
77 #define PLL_REF_DIV_P(n) ((n) & 0xf)
78 #define PLL_REF_DIV_Pe BIT(4)
79 #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5)
80 #define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */
81 #define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */
82 #define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */
83 #define GPIO_OEN 0x79
84 #define MIPI_CFG_PW 0x7a
85 #define MIPI_CFG_PW_CONFIG_DSI 0xc1
86 #define MIPI_CFG_PW_CONFIG_I2C 0x3e
87 #define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */
88 #define IRQ_SEL 0x7d
89 #define DBG_SEL 0x7e
90 #define DBG_SIGNAL 0x7f
91 #define MIPI_ERR_VECTOR_L 0x80
92 #define MIPI_ERR_VECTOR_H 0x81
93 #define MIPI_ERR_VECTOR_EN_L 0x82
94 #define MIPI_ERR_VECTOR_EN_H 0x83
95 #define MIPI_MAX_SIZE_L 0x84
96 #define MIPI_MAX_SIZE_H 0x85
97 #define DSI_CTRL 0x86
98 #define DSI_CTRL_UNKNOWN 0x28
99 #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3)
100 #define MIPI_PN_SWAP 0x87
101 #define MIPI_PN_SWAP_CLK BIT(4)
102 #define MIPI_PN_SWAP_D(n) BIT((n) & 0x3)
103 #define MIPI_SOT_SYNC_BIT_(n) (0x88 + ((n) & 0x1)) /* 0..1 */
104 #define MIPI_ULPS_CTRL 0x8a
105 #define MIPI_CLK_CHK_VAR 0x8e
106 #define MIPI_CLK_CHK_INI 0x8f
107 #define MIPI_T_TERM_EN 0x90
108 #define MIPI_T_HS_SETTLE 0x91
109 #define MIPI_T_TA_SURE_PRE 0x92
110 #define MIPI_T_LPX_SET 0x94
111 #define MIPI_T_CLK_MISS 0x95
112 #define MIPI_INIT_TIME_L 0x96
113 #define MIPI_INIT_TIME_H 0x97
114 #define MIPI_T_CLK_TERM_EN 0x99
115 #define MIPI_T_CLK_SETTLE 0x9a
116 #define MIPI_TO_HS_RX_L 0x9e
117 #define MIPI_TO_HS_RX_H 0x9f
118 #define MIPI_PHY_(n) (0xa0 + ((n) & 0x7)) /* 0..5 */
119 #define MIPI_PD_RX 0xb0
120 #define MIPI_PD_TERM 0xb1
121 #define MIPI_PD_HSRX 0xb2
122 #define MIPI_PD_LPTX 0xb3
123 #define MIPI_PD_LPRX 0xb4
124 #define MIPI_PD_CK_LANE 0xb5
125 #define MIPI_FORCE_0 0xb6
126 #define MIPI_RST_CTRL 0xb7
127 #define MIPI_RST_NUM 0xb8
128 #define MIPI_DBG_SET_(n) (0xc0 + ((n) & 0xf)) /* 0..9 */
129 #define MIPI_DBG_SEL 0xe0
130 #define MIPI_DBG_DATA 0xe1
131 #define MIPI_ATE_TEST_SEL 0xe2
132 #define MIPI_ATE_STATUS_(n) (0xe3 + ((n) & 0x1)) /* 0..1 */
133 #define MIPI_ATE_STATUS_1 0xe4
134 #define ICN6211_MAX_REGISTER MIPI_ATE_STATUS(1)
135
136 struct chipone {
137 struct device *dev;
138 struct regmap *regmap;
139 struct i2c_client *client;
140 struct drm_bridge bridge;
141 struct drm_display_mode mode;
142 struct drm_bridge *panel_bridge;
143 struct mipi_dsi_device *dsi;
144 struct gpio_desc *enable_gpio;
145 struct regulator *vdd1;
146 struct regulator *vdd2;
147 struct regulator *vdd3;
148 bool interface_i2c;
149 };
150
151 static const struct regmap_range chipone_dsi_readable_ranges[] = {
152 regmap_reg_range(VENDOR_ID, VERSION_ID),
153 regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)),
154 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
155 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
156 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
157 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
158 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY_(5)),
159 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
160 regmap_reg_range(MIPI_DBG_SET_(0), MIPI_DBG_SET_(9)),
161 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS_(1)),
162 };
163
164 static const struct regmap_access_table chipone_dsi_readable_table = {
165 .yes_ranges = chipone_dsi_readable_ranges,
166 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges),
167 };
168
169 static const struct regmap_range chipone_dsi_writeable_ranges[] = {
170 regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)),
171 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
172 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
173 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
174 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
175 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY_(5)),
176 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
177 regmap_reg_range(MIPI_DBG_SET_(0), MIPI_DBG_SET_(9)),
178 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS_(1)),
179 };
180
181 static const struct regmap_access_table chipone_dsi_writeable_table = {
182 .yes_ranges = chipone_dsi_writeable_ranges,
183 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges),
184 };
185
186 static const struct regmap_config chipone_regmap_config = {
187 .reg_bits = 8,
188 .val_bits = 8,
189 .rd_table = &chipone_dsi_readable_table,
190 .wr_table = &chipone_dsi_writeable_table,
191 .cache_type = REGCACHE_RBTREE,
192 .max_register = MIPI_ATE_STATUS_(1),
193 };
194
chipone_dsi_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)195 static int chipone_dsi_read(void *context,
196 const void *reg, size_t reg_size,
197 void *val, size_t val_size)
198 {
199 struct mipi_dsi_device *dsi = context;
200 const u16 reg16 = (val_size << 8) | *(u8 *)reg;
201 int ret;
202
203 ret = mipi_dsi_generic_read(dsi, ®16, 2, val, val_size);
204
205 return ret == val_size ? 0 : -EINVAL;
206 }
207
chipone_dsi_write(void * context,const void * data,size_t count)208 static int chipone_dsi_write(void *context, const void *data, size_t count)
209 {
210 struct mipi_dsi_device *dsi = context;
211
212 return mipi_dsi_generic_write(dsi, data, 2);
213 }
214
215 static const struct regmap_bus chipone_dsi_regmap_bus = {
216 .read = chipone_dsi_read,
217 .write = chipone_dsi_write,
218 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
219 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
220 };
221
bridge_to_chipone(struct drm_bridge * bridge)222 static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
223 {
224 return container_of(bridge, struct chipone, bridge);
225 }
226
chipone_readb(struct chipone * icn,u8 reg,u8 * val)227 static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)
228 {
229 int ret, pval;
230
231 ret = regmap_read(icn->regmap, reg, &pval);
232
233 *val = ret ? 0 : pval & 0xff;
234 }
235
chipone_writeb(struct chipone * icn,u8 reg,u8 val)236 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
237 {
238 return regmap_write(icn->regmap, reg, val);
239 }
240
chipone_configure_pll(struct chipone * icn,const struct drm_display_mode * mode)241 static void chipone_configure_pll(struct chipone *icn,
242 const struct drm_display_mode *mode)
243 {
244 unsigned int best_p = 0, best_m = 0, best_s = 0;
245 unsigned int mode_clock = mode->clock * 1000;
246 unsigned int delta, min_delta = 0xffffffff;
247 unsigned int freq_p, freq_s, freq_out;
248 unsigned int p_min, p_max;
249 unsigned int p, m, s;
250 unsigned int fin;
251 bool best_p_pot;
252 u8 ref_div;
253
254 /*
255 * DSI byte clock frequency (input into PLL) is calculated as:
256 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 8
257 *
258 * DPI pixel clock frequency (output from PLL) is mode clock.
259 *
260 * The chip contains fractional PLL which works as follows:
261 * DPI_CLK = ((DSI_CLK / P) * M) / S
262 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider
263 * register PLL_REF_DIV[4] is extra 1:2 divider
264 * M is integer multiplier, register PLL_INT(0) is multiplier
265 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider
266 *
267 * It seems the PLL input clock after applying P pre-divider have
268 * to be lower than 20 MHz.
269 */
270 fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) /
271 icn->dsi->lanes / 8; /* in Hz */
272
273 /* Minimum value of P predivider for PLL input in 5..20 MHz */
274 p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U);
275 p_max = clamp(fin / 5000000, 1U, 31U);
276
277 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */
278 if (p > 16 && p & 1) /* P > 16 uses extra /2 */
279 continue;
280 freq_p = fin / p;
281 if (freq_p == 0) /* Divider too high */
282 break;
283
284 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */
285 freq_s = freq_p / BIT(s + 1);
286 if (freq_s == 0) /* Divider too high */
287 break;
288
289 m = mode_clock / freq_s;
290
291 /* Multiplier is 8 bit */
292 if (m > 0xff)
293 continue;
294
295 /* Limit PLL VCO frequency to 1 GHz */
296 freq_out = (fin * m) / p;
297 if (freq_out > 1000000000)
298 continue;
299
300 /* Apply post-divider */
301 freq_out /= BIT(s + 1);
302
303 delta = abs(mode_clock - freq_out);
304 if (delta < min_delta) {
305 best_p = p;
306 best_m = m;
307 best_s = s;
308 min_delta = delta;
309 }
310 }
311 }
312
313 best_p_pot = !(best_p & 1);
314
315 dev_dbg(icn->dev,
316 "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in=%d Hz ; DPI f_out=%d Hz\n",
317 best_p >> best_p_pot, best_p_pot, best_m, best_s + 1,
318 min_delta, fin, (fin * best_m) / (best_p << (best_s + 1)));
319
320 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s);
321 if (best_p_pot) /* Prefer /2 pre-divider */
322 ref_div |= PLL_REF_DIV_Pe;
323
324 /* Clock source selection fixed to MIPI DSI clock lane */
325 chipone_writeb(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK);
326 chipone_writeb(icn, PLL_REF_DIV, ref_div);
327 chipone_writeb(icn, PLL_INT(0), best_m);
328 }
329
chipone_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)330 static void chipone_atomic_enable(struct drm_bridge *bridge,
331 struct drm_bridge_state *old_bridge_state)
332 {
333 struct chipone *icn = bridge_to_chipone(bridge);
334 struct drm_atomic_state *state = old_bridge_state->base.state;
335 struct drm_display_mode *mode = &icn->mode;
336 const struct drm_bridge_state *bridge_state;
337 u16 hfp, hbp, hsync;
338 u32 bus_flags;
339 u8 pol, id[4];
340
341 chipone_readb(icn, VENDOR_ID, id);
342 chipone_readb(icn, DEVICE_ID_H, id + 1);
343 chipone_readb(icn, DEVICE_ID_L, id + 2);
344 chipone_readb(icn, VERSION_ID, id + 3);
345
346 dev_dbg(icn->dev,
347 "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n",
348 id[0], id[1], id[2], id[3]);
349
350 if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) {
351 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");
352 return;
353 }
354
355 /* Get the DPI flags from the bridge state. */
356 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
357 bus_flags = bridge_state->output_bus_cfg.flags;
358
359 if (icn->interface_i2c)
360 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);
361 else
362 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
363
364 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
365
366 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
367
368 /*
369 * lsb nibble: 2nd nibble of hdisplay
370 * msb nibble: 2nd nibble of vdisplay
371 */
372 chipone_writeb(icn, VACTIVE_HACTIVE_HI,
373 ((mode->hdisplay >> 8) & 0xf) |
374 (((mode->vdisplay >> 8) & 0xf) << 4));
375
376 hfp = mode->hsync_start - mode->hdisplay;
377 hsync = mode->hsync_end - mode->hsync_start;
378 hbp = mode->htotal - mode->hsync_end;
379
380 chipone_writeb(icn, HFP_LI, hfp & 0xff);
381 chipone_writeb(icn, HSYNC_LI, hsync & 0xff);
382 chipone_writeb(icn, HBP_LI, hbp & 0xff);
383 /* Top two bits of Horizontal Front porch/Sync/Back porch */
384 chipone_writeb(icn, HFP_HSW_HBP_HI,
385 HFP_HSW_HBP_HI_HFP(hfp) |
386 HFP_HSW_HBP_HI_HS(hsync) |
387 HFP_HSW_HBP_HI_HBP(hbp));
388
389 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
390
391 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
392
393 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
394
395 /* dsi specific sequence */
396 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);
397 chipone_writeb(icn, HFP_MIN, hfp & 0xff);
398
399 /* DSI data lane count */
400 chipone_writeb(icn, DSI_CTRL,
401 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
402
403 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);
404 chipone_writeb(icn, PLL_CTRL(12), 0xff);
405 chipone_writeb(icn, MIPI_PN_SWAP, 0x00);
406
407 /* DPI HS/VS/DE polarity */
408 pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |
409 ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |
410 ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0);
411 chipone_writeb(icn, BIST_POL, pol);
412
413 /* Configure PLL settings */
414 chipone_configure_pll(icn, mode);
415
416 chipone_writeb(icn, SYS_CTRL(0), 0x40);
417 chipone_writeb(icn, SYS_CTRL(1), 0x88);
418
419 /* icn6211 specific sequence */
420 chipone_writeb(icn, MIPI_FORCE_0, 0x20);
421 chipone_writeb(icn, PLL_CTRL(1), 0x20);
422 chipone_writeb(icn, CONFIG_FINISH, 0x10);
423
424 usleep_range(10000, 11000);
425 }
426
chipone_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)427 static void chipone_atomic_pre_enable(struct drm_bridge *bridge,
428 struct drm_bridge_state *old_bridge_state)
429 {
430 struct chipone *icn = bridge_to_chipone(bridge);
431 int ret;
432
433 if (icn->vdd1) {
434 ret = regulator_enable(icn->vdd1);
435 if (ret)
436 DRM_DEV_ERROR(icn->dev,
437 "failed to enable VDD1 regulator: %d\n", ret);
438 }
439
440 if (icn->vdd2) {
441 ret = regulator_enable(icn->vdd2);
442 if (ret)
443 DRM_DEV_ERROR(icn->dev,
444 "failed to enable VDD2 regulator: %d\n", ret);
445 }
446
447 if (icn->vdd3) {
448 ret = regulator_enable(icn->vdd3);
449 if (ret)
450 DRM_DEV_ERROR(icn->dev,
451 "failed to enable VDD3 regulator: %d\n", ret);
452 }
453
454 gpiod_set_value(icn->enable_gpio, 1);
455
456 usleep_range(10000, 11000);
457 }
458
chipone_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)459 static void chipone_atomic_post_disable(struct drm_bridge *bridge,
460 struct drm_bridge_state *old_bridge_state)
461 {
462 struct chipone *icn = bridge_to_chipone(bridge);
463
464 if (icn->vdd1)
465 regulator_disable(icn->vdd1);
466
467 if (icn->vdd2)
468 regulator_disable(icn->vdd2);
469
470 if (icn->vdd3)
471 regulator_disable(icn->vdd3);
472
473 gpiod_set_value(icn->enable_gpio, 0);
474 }
475
chipone_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)476 static void chipone_mode_set(struct drm_bridge *bridge,
477 const struct drm_display_mode *mode,
478 const struct drm_display_mode *adjusted_mode)
479 {
480 struct chipone *icn = bridge_to_chipone(bridge);
481
482 drm_mode_copy(&icn->mode, adjusted_mode);
483 };
484
chipone_dsi_attach(struct chipone * icn)485 static int chipone_dsi_attach(struct chipone *icn)
486 {
487 struct mipi_dsi_device *dsi = icn->dsi;
488 struct device *dev = icn->dev;
489 struct device_node *endpoint;
490 int dsi_lanes, ret;
491
492 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
493 dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
494 of_node_put(endpoint);
495
496 /*
497 * If the 'data-lanes' property does not exist in DT or is invalid,
498 * default to previously hard-coded behavior, which was 4 data lanes.
499 */
500 if (dsi_lanes >= 1 && dsi_lanes <= 4)
501 icn->dsi->lanes = dsi_lanes;
502 else
503 icn->dsi->lanes = 4;
504
505 dsi->format = MIPI_DSI_FMT_RGB888;
506 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
507 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
508
509 ret = mipi_dsi_attach(dsi);
510 if (ret < 0)
511 dev_err(icn->dev, "failed to attach dsi\n");
512
513 return ret;
514 }
515
chipone_dsi_host_attach(struct chipone * icn)516 static int chipone_dsi_host_attach(struct chipone *icn)
517 {
518 struct device *dev = icn->dev;
519 struct device_node *host_node;
520 struct device_node *endpoint;
521 struct mipi_dsi_device *dsi;
522 struct mipi_dsi_host *host;
523 int ret = 0;
524
525 const struct mipi_dsi_device_info info = {
526 .type = "chipone",
527 .channel = 0,
528 .node = NULL,
529 };
530
531 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
532 host_node = of_graph_get_remote_port_parent(endpoint);
533 of_node_put(endpoint);
534
535 if (!host_node)
536 return -EINVAL;
537
538 host = of_find_mipi_dsi_host_by_node(host_node);
539 of_node_put(host_node);
540 if (!host) {
541 dev_err(dev, "failed to find dsi host\n");
542 return -EPROBE_DEFER;
543 }
544
545 dsi = mipi_dsi_device_register_full(host, &info);
546 if (IS_ERR(dsi)) {
547 return dev_err_probe(dev, PTR_ERR(dsi),
548 "failed to create dsi device\n");
549 }
550
551 icn->dsi = dsi;
552
553 ret = chipone_dsi_attach(icn);
554 if (ret < 0)
555 mipi_dsi_device_unregister(dsi);
556
557 return ret;
558 }
559
chipone_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)560 static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
561 {
562 struct chipone *icn = bridge_to_chipone(bridge);
563
564 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
565 }
566
567 #define MAX_INPUT_SEL_FORMATS 1
568
569 static u32 *
chipone_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)570 chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
571 struct drm_bridge_state *bridge_state,
572 struct drm_crtc_state *crtc_state,
573 struct drm_connector_state *conn_state,
574 u32 output_fmt,
575 unsigned int *num_input_fmts)
576 {
577 u32 *input_fmts;
578
579 *num_input_fmts = 0;
580
581 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
582 GFP_KERNEL);
583 if (!input_fmts)
584 return NULL;
585
586 /* This is the DSI-end bus format */
587 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
588 *num_input_fmts = 1;
589
590 return input_fmts;
591 }
592
593 static const struct drm_bridge_funcs chipone_bridge_funcs = {
594 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
595 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
596 .atomic_reset = drm_atomic_helper_bridge_reset,
597 .atomic_pre_enable = chipone_atomic_pre_enable,
598 .atomic_enable = chipone_atomic_enable,
599 .atomic_post_disable = chipone_atomic_post_disable,
600 .mode_set = chipone_mode_set,
601 .attach = chipone_attach,
602 .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts,
603 };
604
chipone_parse_dt(struct chipone * icn)605 static int chipone_parse_dt(struct chipone *icn)
606 {
607 struct device *dev = icn->dev;
608 int ret;
609
610 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
611 if (IS_ERR(icn->vdd1)) {
612 ret = PTR_ERR(icn->vdd1);
613 if (ret == -EPROBE_DEFER)
614 return -EPROBE_DEFER;
615 icn->vdd1 = NULL;
616 DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);
617 }
618
619 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
620 if (IS_ERR(icn->vdd2)) {
621 ret = PTR_ERR(icn->vdd2);
622 if (ret == -EPROBE_DEFER)
623 return -EPROBE_DEFER;
624 icn->vdd2 = NULL;
625 DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);
626 }
627
628 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
629 if (IS_ERR(icn->vdd3)) {
630 ret = PTR_ERR(icn->vdd3);
631 if (ret == -EPROBE_DEFER)
632 return -EPROBE_DEFER;
633 icn->vdd3 = NULL;
634 DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);
635 }
636
637 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
638 if (IS_ERR(icn->enable_gpio)) {
639 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
640 return PTR_ERR(icn->enable_gpio);
641 }
642
643 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
644 if (IS_ERR(icn->panel_bridge))
645 return PTR_ERR(icn->panel_bridge);
646
647 return 0;
648 }
649
chipone_common_probe(struct device * dev,struct chipone ** icnr)650 static int chipone_common_probe(struct device *dev, struct chipone **icnr)
651 {
652 struct chipone *icn;
653 int ret;
654
655 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
656 if (!icn)
657 return -ENOMEM;
658
659 icn->dev = dev;
660
661 ret = chipone_parse_dt(icn);
662 if (ret)
663 return ret;
664
665 icn->bridge.funcs = &chipone_bridge_funcs;
666 icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
667 icn->bridge.of_node = dev->of_node;
668
669 *icnr = icn;
670
671 return ret;
672 }
673
chipone_dsi_probe(struct mipi_dsi_device * dsi)674 static int chipone_dsi_probe(struct mipi_dsi_device *dsi)
675 {
676 struct device *dev = &dsi->dev;
677 struct chipone *icn;
678 int ret;
679
680 ret = chipone_common_probe(dev, &icn);
681 if (ret)
682 return ret;
683
684 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,
685 dsi, &chipone_regmap_config);
686 if (IS_ERR(icn->regmap))
687 return PTR_ERR(icn->regmap);
688
689 icn->interface_i2c = false;
690 icn->dsi = dsi;
691
692 mipi_dsi_set_drvdata(dsi, icn);
693
694 drm_bridge_add(&icn->bridge);
695
696 ret = chipone_dsi_attach(icn);
697 if (ret)
698 drm_bridge_remove(&icn->bridge);
699
700 return ret;
701 }
702
chipone_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)703 static int chipone_i2c_probe(struct i2c_client *client,
704 const struct i2c_device_id *id)
705 {
706 struct device *dev = &client->dev;
707 struct chipone *icn;
708 int ret;
709
710 ret = chipone_common_probe(dev, &icn);
711 if (ret)
712 return ret;
713
714 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);
715 if (IS_ERR(icn->regmap))
716 return PTR_ERR(icn->regmap);
717
718 icn->interface_i2c = true;
719 icn->client = client;
720 dev_set_drvdata(dev, icn);
721 i2c_set_clientdata(client, icn);
722
723 drm_bridge_add(&icn->bridge);
724
725 return chipone_dsi_host_attach(icn);
726 }
727
chipone_dsi_remove(struct mipi_dsi_device * dsi)728 static int chipone_dsi_remove(struct mipi_dsi_device *dsi)
729 {
730 struct chipone *icn = mipi_dsi_get_drvdata(dsi);
731
732 mipi_dsi_detach(dsi);
733 drm_bridge_remove(&icn->bridge);
734
735 return 0;
736 }
737
738 static const struct of_device_id chipone_of_match[] = {
739 { .compatible = "chipone,icn6211", },
740 { /* sentinel */ }
741 };
742 MODULE_DEVICE_TABLE(of, chipone_of_match);
743
744 static struct mipi_dsi_driver chipone_dsi_driver = {
745 .probe = chipone_dsi_probe,
746 .remove = chipone_dsi_remove,
747 .driver = {
748 .name = "chipone-icn6211",
749 .owner = THIS_MODULE,
750 .of_match_table = chipone_of_match,
751 },
752 };
753
754 static struct i2c_device_id chipone_i2c_id[] = {
755 { "chipone,icn6211" },
756 {},
757 };
758 MODULE_DEVICE_TABLE(i2c, chipone_i2c_id);
759
760 static struct i2c_driver chipone_i2c_driver = {
761 .probe = chipone_i2c_probe,
762 .id_table = chipone_i2c_id,
763 .driver = {
764 .name = "chipone-icn6211-i2c",
765 .of_match_table = chipone_of_match,
766 },
767 };
768
chipone_init(void)769 static int __init chipone_init(void)
770 {
771 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
772 mipi_dsi_driver_register(&chipone_dsi_driver);
773
774 return i2c_add_driver(&chipone_i2c_driver);
775 }
776 module_init(chipone_init);
777
chipone_exit(void)778 static void __exit chipone_exit(void)
779 {
780 i2c_del_driver(&chipone_i2c_driver);
781
782 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
783 mipi_dsi_driver_unregister(&chipone_dsi_driver);
784 }
785 module_exit(chipone_exit);
786
787 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
788 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");
789 MODULE_LICENSE("GPL");
790